Currently and Advanced Pixel designs for HEP

1

CURRENTLY AND ADVANCED PIXEL DESIGNS FOR HEP

Patrick Pangaud

Centre de Physique des Particules de MarseilleC.P.P.M

163, avenue de LuminyCase 902

13288 Marseille cedex 09France

[email protected]

USTC, April 11, 2013 Patrick Pangaud - CPPM-IN2P3-CNRS

2

HYBRID PIXELS SENSOR FOR HIGH ENERGY PHYSICSIBM 130nm : FEI4 developmentTSMC 65nm : FEI5 develpmentTEZZARON 3D 130nm: FETC4 developmentsHVCMOS development


3

Hybrid Pixels Detector for LHC/HL-LHC at CERN


LHC : Luminosity of 1034 cm-2.s-1

HL-LHC expected 10 times more luminosity, more pixels, more ionizing particles, more

… !!!

Whatever will be discovered in next years at LHC, need much data to understand what has been discovered.

Higher luminosity allows extending discovery/studies to • higher masses• processes of lower cross-section

LHC has plans of upgrade by increasing luminosity to collect ultimately ~ 3000 fb-1 .This will open new physics possibilities.

Inner Tracking ATLAS detector

USTC, April 11, 2013 Patrick Pangaud - CPPM-IN2P3-CNRS 4

Straw tubes

Silicon strip

Silicon pixel

LHC and ATLAS upgrade


∫ L

dt

Year

phase-0

phase-1

phase-2

2013/14 2018 ~2022

7 TeV →14 TeV

1027 →2x1033cm-2s-1

→ 1x1034cm-2s-1

1x1034 →~2x1034cm-2s-1

Now

~10 fb-1

~50 fb-1

~300 fb-1

3000 fb-1

→ 5x1034cm-2s-1

luminosity leveling

Possible upgrade timeline

T. Kawamoto, TIPP2011, Chicago, USA

ATLAS upgrade


• LHC improves, bulk of luminosity with instantaneous luminosity beyond the nominal luminosity for which the ATLAS detector was designed and built.

• Technology improves, can build better performing detector now.

• Detectors age, after the nominal integrated luminosity has been collected, leading to deterioration of performance during the runs at higher luminosity.

• It will take long time to study and build new detector

• Installation has to be done during the limited number of long shut downs

• Installation has to be planned to be prepared to the new running condition

T. Kawamoto, TIPP2011, Chicago, USA

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IBM 130nm

FE-I4 DEVELOPMENT


HYBRID PIXELS SENSOR FOR HIGH ENERGY

PHYSICS

8

Hybrid Pixels Sensor for HEP The FE-I4 readout chip

50 μ

m50

μm

FE-I3 CMOS technology : 250 nm

400 μm

250 μm

FE-I4 CMOS technology : 130 nm

Done : ATLAS/LHC(2008/2009)

Under ProductionATLAS/LHC upgrade project(2013-2014)


• Participating institutes:Bonn: D. Arutinov, M. Barbero, T. Hemperek, A. Kruth, M. Karagounis.CPPM: D. Fougeron, M. Menouni.Genova: R. Beccherle, G. Darbo.LBNL: S. Dube, D. Elledge, M. Garcia-Sciveres, D. Gnani, A. Mekkaoui.Nikhef: V. Gromov, R. Kluit, J.D. Schipper

160

18FE-I3

FE-I4

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FE-I4 : Motivation for Redesign of FE


• Need for a new FE?• Smaller b-layer radius + potential luminosity increase higher hit rate.

FE-I3 column-drain architecture saturated.

FE-I4 new digital architecture: local regional memories,stop moving hits around (unless RO).

FE-I4 has smaller pixel (reduced cross-section).

• New technology: Higher integration density for digital circuits, rad-hard, availibility.

0.25 μm130 nm

FE-I3FE-I4

Hit prob. / DC

Ineff

icie

ncy

[%

]

LH

C

IBL sL

HC

FE-I3 at r=3.7 cm!

The “inefficiency wall”

EOC

100

80

60

40

20

00 1 2 3 4 5 6 7 8 9 10

M. Backhaus, FEI4 course, Desy, Germany

Future FE-I4-Based Module and Consequences for FE-I4


• Increased active area: from less than 75 % to ~90 %: Reduced periphery; bigger IC; cost down for sLHC (main driver is flip-chip costs per chip).

• No MCC: More digital functionality in the IC.

• Power: Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.] power routing.

FE-Chip FE-Chip

Sensor

MCC

FE-Chip

Sensor

Flex

11

22

33

4

1) Big chip (periphery on one side of module).2) Reduce size of periphery (2.8 mm2 mm).3) Thin down FE chips (190 μm90 μm).4) Thin down the sensor (250 μm 200 μm)?5) Less cables (powering scheme)?

5

challenging: power (routing, start-up), clk. distrib., simulation / management, yield

4


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Motivation for Redesign of FE


• Need for a new FE?• Accommodate higher hit rate (smaller b-layer radius + luminosity

increase) Architecture based on local memories (no column-drain mechanism).

• Smaller pixel size: enhanced granularity and reduced cross-section.• Reduced periphery & bigger chip: higher active area fraction (<75%

~90%); cost down for sLHC (main driver is flip-chip, costs per chip).Big chip a challenge: power (routing, start-up), clk. distrib., yield…

• Simple module: No Module Controller More digital functions into the FE.

• Power efficient design & new concepts: Analog design for reduced currents; decrease of digital activity (digital logic sharing for neighbor pixels); new powering concepts. 8 metal layers [2 thick Alu.] Power routing.

• New technology:• Higher integration density for digital circuits, radiation-hardness (no

Enclosed Layout Transistor), availability on timescales of our experiments.


12

FE-I4 : architecture


pixel array:336×80 pixels

periphery

digital 4-pix

analog 1-pix

4-pixel region

EODCL

DDC

Power

DOB

EOCHL

Pads

CLKGEN

CMD DCD

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FE-I4 : Digital Region (simplified)


- Hit Processing- ToT Counter- ToT Memory- Latency Counter- Triggering/Readout

Receiving hit

Start ToT counter

Assign first free memory and latency counter

Generate trailing edge

Store ToT value

Check for trigger when latency counter finished

Indicate ready to read status (release token)

Release memory after read

Read memory

Generate leading edge


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TSMC 65NM

FE-I5 DEVELOPMENT



PHYSICS

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65nm motivations• For the HL-LHC (Phase 2) a new pixel detector is planned

• 2 removable internal layers are planned ( 3.9 cm – 7.5 cm)• The event rate is high and the FE-I4 architecture is not adapted• The Total Dose is ~ 1GRad

• A new design is required• Reduction of the pixel size for the inner layers

• R&D : CMOS 65 nm, 3D, Monolithic designCMOS 65 nm is an attractive solution for the development of high-density readout IC.


16

65nm prototyping TSMC 65 nm process allows good tolerance to SEU. However the tolerance of TSMC-ARM digital cells have to be

investigated for high dose level : 1000 Mrad

Dose effect : Simulations are in progress to check if there are “sensitive” devices inside the Library DFF cell.

New designs are in development : different structures of configuration memories, IP blocs : ADC, Voltage reference

First submission of 65nm CMOS IP blocks (plus individual narrow test transistors) is foreseen at CPPM in June or September 2013.


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TEZZARON 3-D 130nm

FE-TC4 DEVELOPMENT



PHYSICS

19

3-D motivations for ATLAS read-out chip upgrades

• Improve spatial resolution• Deal with an increasing counting rate Decrease pixel size


• 50

μm

250 μm

FE-I4 , 130nm

Technology shrinking

3-D benefits :Pixel size reductionFunctionalities splittingTechnologies mixing

Vertical stacking

125 μm• 5

0

μm

FE-TC4 , 130 nm

DIGITALANALO

G

400 μm

• 50

μm

FE-I3 , 250 nm

First MPW run for High Energy Physics organized byFNAL with a consortium of 15 institutes.

The proposed 3-D process combines : GLOBAL FOUNDRY 130nm technologyTEZZARON 3D technology

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Context : Pixel trackers for high luminosity• HL LHC : high luminosity, high pile up, high dose

To keep the tracker performance one need to improve pixel granularity : • reduce occupancy , improve resolution (and 2 tracks separation) , reduce

inefficiencies in the readout.• Several ways for hybrid pixels detectors

• move to higher density technologies like 65 nm (shrinking technology )• move to 3D electronics with in-pixel TSVs (vertical stacking)• move to CMOS HV (where the sensor can be in the same circuit as the

analog amplification)

50

μm

50

μm

250 μm

FE-I4 CMOS 130 nm

125 μm

FE-TC4 CMOS 130 nm 2 layers

3D goal : Reduce pixel area without shrinking technology by association of 2 or more layers staked by 3D technologies. Needs in-pixel communication

between the 2 tiers small TSV

Main 3D advantage : Adequate techno selection for the various functions

Main 3D drawback : Not so easy at the moment


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• Moore’s law by scaling conventional CMOS involves huge investments.• 3D IC processes : An opportunity for another path towards continuing the scaling, involving less investments.• Like for conventional CMOS, infrastructures are needed to promote 3D-IC integration, making it available for prototyping at “reasonable” costs.

Source IBM http://www.research.ibm.com/journal/rd/526/knickerbocker.html

3D-IC Integration The Other Path for

Scaling


22

Why 3-D ?More than Moore…


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3-D methods : Through Silicon Vias


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1) Bonding between Die/ Wafersa) Adhesive bond

b) Oxide bond (SiO2 to SiO2)

c) CuSn Eutectic

d) Cu thermocompression

e) DBI (Direct Bond Interconnect)

For (a) and (b), electrical connections between layers areformed after bonding. For (c), (d), and (e), the electricaland mechanical bonds are formed at the same time.

Polymer(BCB)

SiO2bond

Cu SnCu3Sn

(eutectic bond)

CuCubond

Metal

Oxidebond

Metal bond

3-D methods : Bonding Choices


25

Understanding the Basic Principles of 3-D Integration

• Vias• Via First – done at foundry, lowest cost• Via last – after wafers are made, often done by third party

vendors.• General movement in industry toward via first approach

• Bonding options • Mechanical bond only, electrical connections later

• Oxide to oxide bonding• Adhesive such as BCB

• Mechanical and electrical connection formed together• CuSn Eutectic• CuCu Fusion • Direct Bond Interconnect – combination of oxide bonding and metal

fusion• Thinning• Alignment


26

3-D methods : Areas of Interest to HEP

• Major Markets being pursued by Industry for 3D integration• Pixel arrays for imaging• Memory• Microprocessors• FPGAs• …

• 3-D Pixel arrays with high functionality and smaller form factor for particle tracking

• 3-D bonding technology to replace bump bonds in hybrid pixel assemblies.


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Through silicon Via formation is done either before or after CMOS devices (Front End of Line)

processing

IBM, NEC, Elpida, OKI, Tohoku, DALSA….

Tezzaron, ZiptronixChartered, TSMC,RPI, IMEC……..

Form vias before transistors

Form transistors before vias

3-D integration : Via First Approach


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Via last approach occurs after wafer fabrication and either before or after wafer bonding

Zycube, IZM,Infineon, ASET…

Samsung, IBM,MIT LL, RTI, RPI….

Notes: Vias take space away from all metal layers. The assembly process is streamlined if you don’t use a carrier wafer.

3-D integration : Via Last Approach


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3-D project steps


Submission / Test

March 08 / Summer 08

February 09 / April 09

FEI4_P1 design : IBM 130nm, 8 metals14x61 "analogue" pixel matrixPixel size : 50x166µmRad-hard and SEU tolerance

FEC4_P1 circuit : 2D Chartered 130nm, 8 metalsPixel structure : identical to FEI4_P1

(due to schedule no optimization has been done)

Objectives : test Chartered technology (functionalities, performances, radiation…)

FEC4_P2 circuit : 2D Chartered, 8 metalsBased on FEC4_P1 circuit, plus :Optimization of transistorsNew latches for irradiation testsNew PadRing strategy and ground/substrate

separation

FEC4_P3 : 2D Chartered, 8 metals but only 5 are used)

Smaller pixel size : 50µm x 125µmDesign of new sub-circuits and functionalities : Analogue multiplexor and Triple redundancy memory

Calibration (pulse generator) PLL LVDS and ESD I/O Pads

Nov 09 / Jan 10

Nov 10 / Nov 11

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3-D project stepsFirst 3-D design (MPW organized by FNAL) FE-TC4_P1 project• Global Foundries 130 nm (5 metal levels)

+ Tezzaron• One Tier for the analogue pixel part :

• 14x61 pixel matrix• Pixel size : 50x166µm

• One Tier for the digital part• Two versions have been designed :

• one dedicated for test, (FE-TC4-DS)• one “FE-I4-like”.,(FE-TC4-DC)


July 09 / now

Submission / Test

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Tezzaron-Chartered 3-D technology


Main characteristics : 2 wafers (tier 1 and tier 2)

are stacked face to face with Cu-Cu thermo-compression bonding

Via Middle technology : Super-Contacts (Through Silicon contacts) are formed before the BEOL of Chartered technology.

Wafer is thinned to access Super-Contacts

Chartered 130nm technology limited to 5 metal levels

Back-side metal for bonding (after thinning)

M5 M4 M3 M2 M1

M6

Super- Contact

Bond Interface

2.5µm min

12µm 1.2µm

One tier

5µm

10µm

Bond interface layout

Wafer to wafer bonding

32

Tezzaron-Chartered (130nm) 3D run• 3D consortium created in 2008 (with MAPS and Hybrid pixels communities) and 3D MPW run in 2009Main technology features

130 nm Large reticle (≈26 x 30 mm) 6 metal levels (M6 is the bond

interface) Wafer to wafer, face to face

bonding TSV Vias 1.2 µm diameter with

3.8 µm recommended pitch (Via Middle Techno)

Bond interface : copper (regular pattern)

Upper tier thinned down to 10 µm

M5M4M3M2M1

M6

Super Contact

M1M2M3M4M5

M6

Super Contact

Bond Interface

Tie

r 2

Tie

r 1

(th

inn

ed

wa

fer)

Back Side Metal

sensor


33

Fermilab 3-D Multi-Project Run

Fermilab has planned a dedicated 3-D multi project run using Tezzaron for HEP during 2009

There are 2 layers of electronics fabricated in the Chartered 0.13 um process, using only one set of masks. (Useful reticule size 15.5 x 26 mm)

The wafers are bonded face to face.

ATLAS/SLHCSub-part


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FE-TC4-P1 Bonn/CPPM reticles

• The reticles contains : • the analog tier : FE-TC4-AE : Pixel matrix of 14 x 61 pixels , pixel

size 50x166 µm. Analog tier is very close to FE-C4-P1 (GF version of FE-I4-P1)• 2 flavors of digital tier :

• FE-TC4-DS : digital tier with simple read-out (one-bit latch/ pixel), dedicated for studying coupling between tiers

• FE-TC4-DC : digital tier with complex readout “a la FEI4” (Bonn)• SEU3D : SEUless memory blocks• General Test structures : TSV + BI Daisy chain , transistors, etc…


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Delay due to production difficulties

Analog tier completely removed during thinning

+ misalignment of bond interface between two tiers

First 3D assemblies AE-DC and AE-DS arrived in September 2011 with damages.

First tests in 2011 :

Analog tier, DC tier, DS tier tested separately in standard thicknesses (February 2011)

First 3D working chips in 2012 !

First 3D wafers with defects visible to the naked eye


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FE-TC4-AE analogue tier


Based on FE-C4_P1 chip + all adds for 3-D connection

Input signal from sensor via the Super-Contacts

Bonding pad in Back-side metal

2 possible ways for discriminator output read-out:

With the simple read-out part existing yet into the pixel

With the tier 2 (via the Bond Interface)

Additional switch for read-out

37

3D Test results : FETC4_AE results

The analogue Tier is thinned. The output of the comparator can be read directly in the analog tier or in the digital tier via the bond interface (in the same time!)

Noise < 100 e- rms

The 10 µm thick analog pixel behaves as un-thinned one .


FE-C4_P1FE-TC4_AE_3

FE-TC4_AE_1FE-TC4_AE_2

Mean Noise versus dose

0

10

20

30

40

50

60

0,1 1 10 100 1000

Dose (MRad)

Mean

Nois

e (

e-)

38

FE-TC4-DS digital tier for test


Analogue tier and digital tier are face to face (sensitive part facing digital part).

FE-TC4-DS : dedicated for parasitic coupling studies between the 2 tiers.

3 functions : Read the discriminator output Generate noise (digital

commutations) in front of 11 specific areas of the analogue pixel (preamplifier, feed-back, amplifier2, DAC…)

Test different shielding configurations.

Analogue pixel layout : 11 specific areas

M5 M4 M3 M2 M1

M6

SuperContact

M1 M2 M3 M4 M5

M6

SuperContact

Bond Interface

Tier 2

Tier 1 (thinned wafer)

Back Side Metal for bonding

ANALOGUE

DIGITAL

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3D Test results : FE-TC4-AEDS chipAnalogue and Digital Simple tiers communicate !


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3D Test results : FE-TC4-AEDS chipShielding studies with Digital Simple

• The DS chip contains :• a simple readout system

(one-bit latch/ pixel), a counter,

• 11 DRUM cells (noise generators to study the coupling between tiers) which can be activated individually. Each DRUM cell layout is facing one

specific area (sub-part) of the analog pixel. To test the

intra-pixel sensitivity.

A simple way to generate noise and test the influence on the analogue Tier.


41

3D Test results : FE-TC4-AEDS chipShielding studies with Digital Simple• Moreover, to determine the best shielding strategy, different metal

shielding have been implemented on the DS chip :

Sh

ield M

etal 3 a

nd

Metal 5

Sh

ield M

etal 5

No

Sh

ield

Sh

ield M

etal 3

No

Sh

ield

Shielding configuration depending on column numbers :

Col 0 and 1 => shield in Metal 3 and Metal 5

Col 2, 3, 4, 5 => shield in Metal 5 Col 6, 7, 8 => no shield Col 9 and 10 => shield in Metal 3 Col 11, 12, 13 => no shielded


42

3D Test results : FE-TC4-AEDS chipShielding studies with Digital Simple

• First try Comparison No Drums / All Drums• S curves measurements

noise

=

116 e

- 15

0 e-

250

e-

350

e-

800

e-

A shielding is necessary.

Shielding with only M3 is not enough efficient.

Metal 5 appears to be the best solution.


43

3D Test results : FE-TC4-AEDS chipShielding studies with Digital Simple Studying the intra-pixel sensitivity

Each drum is separately activated. The noise is measured on column 7 (without any shield) (noise of 116e- with all drum OFF).

The most sensitive parts are those directly connected to the input (bump area, injection capacitor) : Not a big surprise but it confirms that the others parts are not sensitive to the digital tier.

119 e-

400 e-

200

e-

119 e-

500

e-

350 e-

120 e-

121

e-

124 e-

119 e-

120 e-


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3D Test results : FE-TC4-AEDC chip

• Digital Complex chip offers a complex read-out "A la FE-I4” (with 4 pixel regions).• The FE-TC4-AEDC is fully tested by Bonn University :

Threshold~2400e- Noise~94e-

The tuned threshold can

reach a dispersion of 50e-.

The AE tier and DC tier communicates wells.

The analogue performances are as expected.

The readout with TOT information has been tested and works as expected.


45

3D Test results : FE-TC4-AEDC chipStudy of crosstalk between pixel• Test procedure:

• Inject charge to two pixels and read out only the pixel in between.

• Cover the matrix with a 16 Step mask. • Configuration : Tuned threshold around ~ 2800 electrons (for the

pixel in the middle)• The injection is increased until reach the crosstalk threshold for

which the middle pixel is affected.Crosstalk threshold = Normal Threshold / Threshold Measured with crosstalk mask

16 Step MaskFirst stepInject

InjectRead


46

3D Test results : FE-TC4-AEDC chipStudy of crosstalk between pixel

Threshold ~31680 e- Threshold ~31810 e- Crosstalk threshold ~ 4,42% Crosstalk threshold ~ 4,40%

Read analog tier Read digital tier

• The crosstalk threshold is the same if the readout is done via the analog shift register or the digital shift register :• The main crosstalk path is on the analog tier only.• No addition of crosstalk through the digital tier is

observed.


47

3D Project : test structures • From the first 3D prototype made for the ATLAS Project, some test were done to measure TSV and Bond-Interface performance.

• The TSV (Through Silicon Via) consists of a vertical conductor, often referred to as “nail” or “plug”, entirely crossing the Si substrate of the stacked dies. Measure the TSV

daisy chain(51520 tsv), to understand

its electrical properties.


48

FE-TC4-P1 TSV and BI test • We measured 19 chips, which show good tsv daisy chain interconnection. Yielding ~84%.

• Single tsv resistance is . Agree with reference value <600mohm(Tezzaron report)

• Single tsv capacitance(metal-insulator-semiconductor) in inversion region is around 5.5fF. The calculated value is 3.6fF. In addition, we cannot measure accumulation region capacitance because ESD diodes limit bias voltage.

• The BI test results reveal some problems. Only 1 chip shows good interconnection. Perhaps the alignment issues and chip surface irregularities lead to these problems.

m24603


49

Single 2D FE-C4_Px test results

All prototypes showed excellent results• Un-tuned FEC4_P1 threshold dispersion around 200 e-• FEC4_P1 Noise lower than 100 e- rms• FEC4_P1 Power consumption 27µA/pixel


Irradiation zone

LVDS signals

~20 meters

IrradiatedSampleIn the beam

LVDS to LVTTL translator

~4 meters

Single ended

Outside the beamIntermediate board

Control room

USB link

Power Supply

DE2 board

Synchronization signalsfrom the machineIrradiation

performed at CERN/PS facility (24 GeV protons)

50

FEC4-P3 test results under radiation• Third 2D chip in Chartered 130nm ( submitted in

2011) :• Smaller pixel size (50µm x 166µm => 50µm x 125µm)• Design of new sub-parts : analogue buffer, analogue multiplexor

….• Radiation Hardness improvement (optimized latches, substrate

separation, guard-ring…)

• Tests under radiation at CERN/PS :• The test was made up to 650 MRads.• The chip resists well :

• up to 300 MRads for the Analog Part • and up to the end of the campaign for the Digital Part.

• The chip is not broken after irradiation, and works.• The Analog Part shows a good annealing recovering after 6

months (after irradiation: 78% of dead pixels, after 6 months of annealing: 18% of dead pixels).

• The new small analog pixel is now completely ready for a next 3D integration.


51

FEC4-P3 : Analog behavior before protons beam


At 0 MradSigma Threshold = 674 e-Mean Noise = 339 e-

The nominal noise is 100e-, but we ever detected some excess noise by using the USBPix card (200e-)

52

FEC4-P3 : Analog behavior under protons beam


At 594MradsSigma Threshold = ?????Mean Noise = ?????

3/05

/201

2

10/0

5/20

12

17/0

5/20

12

24/0

5/20

12

Beam Fluence

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FEC4-P3 : Analog behavior after 203 days annealing


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The FE-TC4 ATLAS full-scale chip


• FE-TC4, run 3-D • Very large matrix size : 336 x 160

pixels Chip size of 18.8 x 20.1 mm. 1.95 mm End Of Column width.

• Small pixel size : 125µm x 50µm• Bump bond pads compatible with

250 µm sensor pitch (FE-I4 project)• The FE-TC4 re-uses main blocks of

FE-I4 to be compatible for sensors, bump bonding , module/stave integration, testing tools, software, mechanics

160

18FE-I3

FE-TC4 160

55

Conclusions and prospects• The Global Foundry 130nm is a good candidat with good

electrical performance under protons radiation• Despite the (very) poor yield the Tezzaron-Chartered

technology is finally working and gives very good results.

• Substantial efforts have to be made by vendors to improve yield and delivery schedule.

• Next step : Hybridization of a sensor in such a 3D wafer• If the sensor hybridization on a 10µm thinned tier works, this

3D process will be a success.

• In parallel, we work with HV-CMOS technology which can allow to perform 3D stacking without the sensor hybridization step (reduce of cost, time and complexity).

• We are working firstly with the Chartered HV technology (BCDlite) in view of a Chartered-Tezzaron 3D processing (2D MPW run in May 2012). But if this technology would appear to be not suitable, we could try to use Tezzaron process with another HV technology (as allowed in 3D process).

Sensor layout :Anna Macchiolo,

Max-Planck-Institut für Physik, Munich


56

HVCMOS DEVELOPMENT



PHYSICSMonolith

ic

57

SMART Diode in CMOS technology

The CMOS signal processing electronics are placed inside the deep-n-well. PMOS are placed directly inside n-well, NMOS transistors are situated in their p-wells that are embedded in the n-well as well.

P-substrate

NMOS transistorin its p-well

PMOS transistor

Particle

E-field

Deep n-well

Pixel electronics in the deep n-well

The sensor is based on the “deep” n-well in a p-

substrate

Ivan Peric, FEE2011, Bergamo, Italy


58USTC, April 11, 2013 Patrick Pangaud - CPPM-IN2P3-CNRS

59USTC, April 11, 2013 Patrick Pangaud - CPPM-IN2P3-CNRS

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A new 3D approach for HEP community

M6 M6

TSV

Bond Interface

Tie

r 2

Smart Sensor

Tie

r 1

(th

inn

ed

w

afe

r)

Back Side Metal

M5M4M3M2M1

M1M2M3M4M5

M5M4M3M2M1

M1M2M3M4M5

particle

Global Foundries BCDLite technology 0,13µm

Electrical field

• TSV technologies (Via last or middle or first)

• GlobalFoundries 0,13µm BCDLite technology• The BCDLite include the Low

power option plus the High Voltage option.

• Bond Interface : regular Redistribution Layer made with last thick Cu Top Metal (1µm)

• 6 metal levels • Large reticle (≈26 x 30 mm)• Upper tier thinned down

The HV-CMOS technology allows to perform 3D stacking without the sensor hybridization step (reduce of cost, time and complexity). Because the Tezzaron-Chartered technology is a good rad-hard candidate, we will use the enhanced

GlobalFoudry BCDLite technology to design a new chip in spring 2013

Can we mix the smart diode and the 3D Integrated technology?


61

IBM 130nm: Possible well-substrate configuration

NwellPwell

Deep Nwell

P- (1-2 Ohm-cm)

Nwell Pwell

T3 “Burried n”

P- (1-2 Ohm-cm)

P-

Nwell Pwell

P- (1-2 Ohm-cm)

Conventional

T3: True isolation. NMOS and PMOS on top of sensor. Substrate can be biased.Proposed prototype to study such a sensor!

Deep Nwell: more flexible - sub can be biased

VSUB 0 to -10V


62

Conclusion• Time to R&D, between LHC phases• Several approach for the same goal : Compactness

information on less mass material.• Using the 3-D electronic integration approach• Using very deep submicronic technology (65nm technology…)• Using the HVCMOS• …. Or all in one

• We need to create, design and test to qualify these new approaches• New technologies (deeper submicronic, 3D ways, Smart pixels…)

• New industrial, academic partners, new alliances • Novel architecture (analog detection and digital post-processing)• Radiation hardness ( protons beam, Gamma ray, etc…)• Robustness by test

• We would like to thank the fruitful collaboration withWei Wei, Lei Zhao, Luo Jianping, Wang Zheng

Na Wang, Jiang Xiaoshan, Fu Wei, Jian Lu


Currently and Advanced Pixel designs for HEP

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