*Based on text by S. Mourad "Priciples of Electronic Systems"Digital Testing: Current Testing

Problem 1a) Use Boolean difference to find all tests for E s-a-1 and Es-a-0 fault.b) Find all tests that distinguish between E s-a-0 and D s-a-1 faults.

Problem 2For the circuit shown compute the combinational controllability and observability in all the signal lines. Use the following notation (CC0,CC1)CO to indicate your results. For instance, if the signal x1 has CC0=1, CC1=1 and CO=5, write (1,1)5 next to the signal name on the figure. Make sure that you consider all signals (including the branch signals a,b,c,d,e, and f).

Problem 3Use the critical signal approach to detect C s-a-1 fault. What other faults can you detect using this run of the critical signal setting? Hint: start with the output signal Y = 1.ABCDEFGH26158910Y

Problem 4Use D-algorithm to find test vector for s-a-0 fault on the fanout branch h in the circuit shown.

Fab. 2, 2001Copyrights(c) 2001, Samiha Mourad*Outline Why current testing Effect on propagation delays Measurement of current Test pattern generation Subthreshold current Effect of deep submicron From http://www.amplifier.cd/Test_Equipment/Tektronix/Tektronix_other/576_applications/30_2219.jpg

Copyrights(c) 2001, Samiha Mourad

MotivationEarly 1990s Fabrication Line had 50 to 1000 defects per million chipsConventional way to reduce defects:Increasing test fault coverageIncreasing burn-in coverageIncrease Electro-Static Damage awarenessNew way to reduce defects:IDDQ Testing also useful for Failure Effect Analysis

What is Current Testing? Also called IDDQ Testing Measurement of the supply, VDD, quiescent currentthe sum of all off-state transistors Useful only for CMOS circuits Limitation due to shrinking technology

Basic Principle of IDDQ TestingMeasure IDDQ current through Vss bus

Current Testing Basics CMOS circuits operate with normally negligible static current (power) But, a defect that causes an appreciable static current can be detected by measuring the supply current, IDDQ Technique used since inception of CMOS technology Limitation due to shrinking technology

IDDQ TestingIDD --- Current flow through VDD Q --- Quiescent stateIDDQ Testing --- Detecting faults by monitoring IDDQNormal IDDQ: ~10-9Amp.Abnormal IDDQ: >10-5Amp.CMOScircuitInputsOutputsVDDIDD

Advantages of IDDQ TestingFault effect is easy to detectMany realistic faults are detectableATPG is relatively simpleTest length is shorterBuilt-in current sensing is possible

IDDQ Distribution MgMdIDDQDefectiveGoodFrequency(Md - Mg) should be an easily measurable quantity

How Does it Work?Apply a test patternWait for the transient to settle downMeasure the currentNeeded:How to generate the patternsHow to measure the current But, first current characteristics

Dynamic Current

Inverter: Good and Faulty IDDQ

A NAND TreeMeasurement requires the current settling downThe effect of the delays shown on the next slide

Current for the NAND Tree

IDDQ MeasurementMeasurement may interfere with the measured currentA successful measurement should be:easily placed between the CUT and the bypass Capacitor of the power pinCapable of measuring small currentsNon intrusive, no drop of VDDFast measurement few ns per patternTwo types: on- and off-chip

External MeasurementProblem: CUT sensitive to power supply drop on R

Current Sensing StructuresSense amplifiers designed to minimize the VDD voltage drop

Shunting by diode limits the voltage drop to 0.7V

Another option is to use pass transistor

Internal MeasurementWhen large IDDQ exists, V>VR and Fail flag is set.

BICS Based on Bipolar Transistor The switching circuit may switch off a faulty module to prevent large power consumptionV

Analysis of a ShortFor the shorted pMOS transistor, find: a path form VDD to GND through this transistor, then AB = 11 is needed to detect this short using IDDQ

Consider p-MOS with input B stuck-on (B s/0)Transistor is always on

Detecting Short FaultsTo detect leakage between gate and source B set A=0 and C=1To detect leakage between gate and drain B set A=1 and C=0

Test Pattern Generation (TPG)Mainly two methods:based on switch level using graph representation as for layoutbased on leakage fault models

Graph or Switch Based TPGPath A,A,B to test shorts on A transistors Path B,A,B to test shorts on B transistors

Leakage Fault ModelIO bg bd bs ds gd gs NAssuming all possible shorts between the four nodes, bulk, source, gate, and drain results in 6 tuples of faults (bg bd bs ds gd gs )Consider various I/O patternsOnly correct logic signal values are used for leakage models. Some I/O combinations are impossible for a given logic, for instance 00, 11The 6 tuples are represented by octal numbers as shown in column N of the tableFor instance for I/O=10 transistorfault code is N=438=100011and represents the following faults:bg, gd, gspMOS model

Characterizing a NANDI/O octal code, eg.:6=110=>A=1,B=1,O=0Octal fault vector codefor each transistor The leakage fault model notation is used to characterize a 2-input NAND

Characterizing a NOR

IDDQ Vector Selection

Characterize each logic component using switch-level simulation relate input/output logic values & internal states to: leakage fault detectionweak fault sensitization and propagationStore information in leakage and weak fault tablesGenerate complete stuck-at fault testsLogic simulate stuck-at fault tests use tables to find faults detected by each vector to select vectors for current measurement

Impact of Deep SubmicronDeep submicron transistors work at lower VtThe lower Vt the higher IDDQThe discrepancy between the faulty and non-faulty IDDQ is narrowing

Controlling leakage IDDQReverse biasing the substrateCooling the devicesUsing dual threshold voltagePartitioning the circuit to manageable IDDQ

Change of Current with Body Bias and Temperature

Stuck-open Faults ABCDOutT1 =11110T2 =0001?When T2 is applied (and transistor A is open), charge sharing among x, y and Out occurs, and logic state is undetermined.Yet the following inverter will draw a significant current and IDDQ detects this fault.BCxyDOutCBADATo test a/1 use vectorsA stuck opentransistor is always off

Other Faults Detectable by IDDQGate-oxide short Most stuck-at faultsLatch-upDelay faultsAny other fault due to extra conductor, missing isolating layer, excess well/substrate leakage, etc.

Circuit Constraints To ensure IDDQ detectability, two conditions must be satisfied:1. Normal IDDQ must be small2. Faults must result in large IDDQ

A Good Circuit that may be identified as FaultyProblem due to high impedance nodeWhen the third pattern AB=10 is applied, change sharing between x, z occurs, and a large current may exist in the inverter. However the output is still correct.

A bridging fault (BF) that cannot be Detected by IDDQProblem due to feedback loop=1: a=0, b=1=1: Eventually x=y (and will set to full VDD or GND value as one signal will dominate), no big current

Problems with Dynamic LogicProblems: 1. Large current in normal circuits due to charge sharing 2. Very few faults are detected because of the precharge property (no direct path VDD-GND) 3. Fault masking of BF(a, b) due to BF(o, p)InputsxyfffoabpO

Transistor GroupTransistor group (TG) --- "Channel-connected component"Connections between two TGs are unidirectional Control direction or loop can be definedABCDOutputG3G2G1E

A Minimum Set of Design & Test Rule for IDDQ Testing A1. Gate and drain (or source) nodes of a transistor are not in the same TG.A2. No conducting path exists from VDD to GND during steady state.A3. Each output of a TG is connected to VDD or GND during steady state.A4. No control loops among TGs exist.A5. The bulk (or well) of an n-(p-)type transistor is connected to GND (VDD).A6. During testing, each PI is controlled by a monitored power source.

Results of Design & Test RulesTheorem 1: All irredundant single BFs in a circuit satisfying A1-A6 can be detected using IDDQ testing.Theorem 2: For a circuit satisfying A1-A6, a test detecting a single BF f also detects all multiple BFs that contain f.Theorem 3: If any one of A1-A6 is removed, then circuits exist for which IDDQ testing cannot give correct test results.Strategies for dealing with circuits not satisfying each rule are required to ensure IDDQ detectability.

Fault Simulation in IDDQ1. Fault models --- Bridging, break, stuck-open, stuck-at ?2. Fault list generation --- need inductive fault analysis3. Fault coverage ?4. Easy for bridging and stuck-on faults5. Difficult for break and stuck-open faults6. Stuck-at faults may or may not be modeled as short to VDD or GND

Fault simulation for BFsIf A1-A6 are satisfied, then fault simulation is quite simple

1. Perform a good circuit simulation for the given test pattern.2. Any BF between a node with logic 1 and a node with logic 0 is detected.

No simulation on faulty circuit is needed.No fault list enumeration is needed.

Test Generation1. Conventional test generation for stuck-at faults can be modified to detect BFs.2. No fault propagation.3. Must make sure the faults result in a conducting path between VDD and GND. Switch level test generation may be necessary.4. Break and stuck-open faults are difficult to detect.

Test generator for bridging faultsAgain, assume A1-A6 are satisfied1. For the bridging fault BF (a, b) to be detected, add an XOR gate with its inputs connected to a and b. 2. The test generator work is simply to set the output of the XOR gate to 1.No Fault propagation.

Current monitoring TechniquesCUTBICSCurrent SupplyMonitorExternalmonitoringTestFixtureBuilt-In Current Sensor

External DevicesProblems: 1. Current resolution is limited. 2. Test equipment must be modified. 3. Current cannot be measured at the full speed of the tester. 4. Cannot partition circuit.Transistor conducts in normal mode and is open in test mode

Built-in Current Sensors (BICSs)ORCUTBICSInputsOutputsTestPass /FailVDDSometimes called ISSQ testing

BICS Based on Logic ThresholdNormal : t = 1Test : t = 0For correct operationNo path to VDD from gates of MTD transistorstout = 1 if no fault = 0 if fault exists

Improvement on Favalli's design

Using BiCMOS designPull- upPull- downPull- upPull- downPull- upPull- downMTMTDGndtoutVDDVDDVDDinputs......Improvement on Favalli's Design

BICS Based on Dual Power Supply & Operational Amplifier-+Vin=3VThreshold detectorFault indicationCUTVDD=3VRSVout+Vout-VDD'=5VVSSI-I+VirtualShortIDDVirtual short VDD~VinInfinite input impedance of OP I-=0 and IRS=IDD

BICS Based on Current ConveyorVirtualShortV'DD=5VIzIxVDDCUTCurrent ConveyorIyFail/PassThresholdDetectorVirtual short VDD ~ VDD'Current Conveying Iy ~ Ix

Advantages of Built-In Current Sensors (BICS) Higher test rate compared to external devices Easier to partition circuits Easier to control current resolution Suitable for mixed-mode circuits Built-In self test capability achievable Lower test equipment cost On-Line testing possible

Disadvantages of BICS Impact on circuit performance Reliability of itself Area overhead Power consumption

Company

HP

SandiaIDDQ

Without IDDQWith IDDQ

Without IDDQWith IDDQNoTest16.460.80OnlyFunct.6.360.09OnlyScan6.040.11Both5.800.00Functional Tests5.5620Reject ratio (%)HP and Sandia Lab DataHP static CMOS standard cell, 8577 gates, 436 FFSandia Laboratories 5000 static RAM testsReject ratio (%) for various tests:

Failure Distribution in Hewlett-Packard Chip

Sematech StudyIBM Graphics controller chip CMOS ASIC, 166,000 standard cells0.8 static CMOS, 0.45 lines (Leff), 40 to 50 MHz clock, 3 metal layers, 2 clocksFull boundary scan on chipTests:Scan flush 25 ns latch-to-latch delay test99.7 % scan-based stuck-at faults (slow 400 ns rate)52 % SAF coverage functional tests (manually created)90 % transition delay fault coverage tests96 % pseudo-stuck-at fault coverage IDDQ tests

Sematech ConclusionsHard to find point differentiating good and bad devices for IDDQ & delay testsHigh # passed functional test, failed all othersHigh # passed all tests, failed IDDQ > 5 mALarge # passed stuck-at and functional testsFailed delay & IDDQ testsLarge # failed stuck-at & delay testsPassed IDDQ & functional testsDelay test caught failures in chips at higher temperature burn-in chips passed at lower temperature

Current Limit SettingShould try to get it < 1 mAHistogram for 32 bit microprocessor

Delta IDDQ Testing (Thibeault)Use derivative of IDDQ at test vector i as current signatureIDDQ (i) = IDDQ (i) IDDQ (i 1)Leads to a narrower histogramEliminates variation between chips and between wafersSelect decision threshold def to minimize probability of false test decisions

|IDDQ| and |DIDDQ|

Setting Threshold

IDDQIDDQMean (good chips)0.696 A-210-4 AMean (bad chips)1.096 A0.4 AVariance0.039 (A)20.004 (A)2defError Prob.Error Prob.0.30.0597.310-40.40.0324.410-50.50.0171.710-6

SummaryIDDQ test is used as a reliability screenCan be a possible replacement for expensive burn-in testIDDQ test method has difficulties in testing of sub-micron devicesGreater leakage currents of MOSFETs Harder to discriminate elevated IDDQ from 100,000 transistor leakage currentsIDDQ test may be a better choiceBuilt-in current (BIC) sensors can be useful

***********In general a CMOS circuit consumes very small steady state current.Many CMOS faults result in large IDDQ , typically ranged from tens of mA to mA.*Large difference between faulty and fault free circuit.Faults detectable include bridging, break, transistor stuck-on, gate-oxide short, latch-up , etc..No fault propagation is needed.Many built-in current sensors have been developed.***********The first design for BICS.The sensing device is a bipolar transistor which has the property that when I is small, dV/dI is large, hence can give good current resolution. When I is large, dV/dI is small, then V is limited.The basic idea is to compare the voltage drop on the bipolar transistor with a reference voltage VR and use a differential amplifier to provide the error indication.When an excess current exists, the Pass/Fail flag is set, and the switching circuit will turn off the bipolar transistor to prevent further current consumption.Bipolar or lateral NPN process is needed. ************To detect A stuck-open , we need two vectors, the first one setting output o to logic 0 and the second one trying to set up a conducting path that must go though A such that in the fault-free circuit , o become 1 and in the faulty circuit o retains o.T1 and T2 are two vectors that satisfy the above condition. However it is possible that due to charge sharing the voltage value at o become an intermediate voltage in the faulty circuit and hence logic testing can not detect this fault.Fortunately if IDDQ testing is available, this fault can still be detected.*Many delay faults can be detected by IDDQ testing because a circuit with a delay fault may imply that some transitions still exist in the circuit during steady state.*Though many faults are IDDQ detectable, we still have to be very carefully when employing this method.In the following, several examples indicating the problems are given.*Due to some don't care terms in the function to be designed , a designer may consider the circuit to be correct. However leakage current may occur during normal operation.*To detect BF (x, y), different logic values must be applied to x and y, respectively.Due to the self control loop, either x dominates y or y dominates x. Eventually either (x, y)=(1, 1) or (x, y)= (0,0).*Left side is a typical domino logic gate with a precharge input f.During the evaluation phase, if the precharge node is not connected to ground, then it should retain at 1. However due to charge sharing, it can become an intermediate voltage and hence large current may occur in the inverter.A BF(x, y) inside the n-block is not IDDQ testable because they can never be connected to VDD and Ground simultaneously.Similarly if x is in one n-block and y is in another, the BF(x, y) is not IDDQ testable.A BF between the output of two inverter such as (a, b) in the right figure is IDDQ detectable. However if another undetectable BF(o, p) exists then the fault detection may be invalidated.*From the above examples, it becomes clear that one must be very careful when using IDDQ testing.A set of design & test rules for IDDQ testing was derived by Lee & Breure in T-CAD'92. To understand these rules, an important concept called transistor grouping must be introduced first.A transistor group is a set of transistors whose channels are connected through drain or source without passing though VDD or GND.After partitioning, the I/O between TGs can be defined by their gate terminal connections, e.g., G2 is an input to G3 and G1 is an input to G2.Through these I/O relationship, control direction or loop can be defined.The concept of TG is widely used in switch level analysis of CMOS circuits.*A1 is used to prevent "self control".A5 is used to prevent "anomalous reverse conducting" effect. See Rajsuman DAC'87 for details.A6 is because a current sensor usually only monitors the VDD line or GND line , but not both. Hence a large current through PI may flow through a power line that is not monitored.*The three theorems are self-explanary.It must be pointed out that the set of rules is sufficient, but not necessary. This is because one may have a circuit that does not satisfy some rule, but is still IDDQ testable, e.g., a cross coupled 6-transistor XOR gate.The set of rules is minimum in the sense that if any of the rules is removed, then problems exist for some circuits, not for all circuit. *The conventional fault coverage concept based on single stuck at faults may need some modifications---IFA is important.Break detection is an important but difficult research topic.*One test vector divides the circuit nodes into two sets, one with logic 1 and the other with logic 0. Any fault between two nodes in different sets is detected. Two test vectors divide the circuit nodes into 4 sets with logic values of 00, 01, 10, 11, respectively. A BF between nodes from any two different sets is detected. Therefore if a test set can distinguish all circuit nodes, the all BFs are detected. => No fault list enumeration is needed.*self-explanary*self-explanary*The most important work in IDDQ testing may be the design of current sensors. There exist three methods.*During normal mode, S turns on the transistor.During test mode, the transistor is off and all current flows through RM. Hence by measuring the voltage drop on RM, the fault effect can be identified.Current resolution is limited because the current of the whole chip must be measured.Existing ATE may have no current sensing capability.Current measurement is usually slow. Mixed-type circuits such as BiCMOS are not easy to applied because Bipolar and CMOS consume different ranges of steady state current.*A BICS can be placed at the VDD line or GND line.*Two transistors are added to each logic gate. Hence overhead is large.*Though the number of transistors is reduced, the total area overhead may not be saved as much because the same current supply (or sink) capacity is required.*self-explanary*VDD is provided by the OP amplifier which is powered by a higher level.The current through Rs is equal to IDD.VDD=Vin, hence very low performance degradation can be achieved.*The current conveyor conveys Ix to Iy for fault effect identification.*self-explanary*A BICS may cause extra circuit delay due to the reduced VDD level.If a BICS is faulty, then the whole circuit may crash.Large power consumption due to analog design such as op and differential amp, etc.*********