Current Programmed Control of a Single Phase

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Current Programmed Control of a Single Phase

Two-Switch Buck-Boost Power Factor Correction

CircuitGert K. Andersen, Frede Blaabjerg

Aalborg University, Institute of Energy Technology, Denmark

[email protected]

Abstrac t - This paper presents a new Current Pro-

grammed Control (CPC) technique for the cascaded two

switch buck-boost converter suitable as a low-cost Power

Factor Correction (pfc) rectifier in a variable speed motor

drive. This new CPC technique, which is an extension of

the conventional C PC m ethod , enables variable output dc-

voltage and is therefore suitable in a Pulse Amplitude Mod-

ulated (PAM) motor drive or as an universal input power

supply. The C PC me thod is very simple and requires only a

constant current reference without any changes at the tran-

sition between boo st and buck operating mode and the line

current is practically unaffected by the topology mode shift.

The presented control technique is verified by simulations

and experimental results and compliance with IEC 61000-3-

2 class A is achieved. The experimental setup is based on a

commercial CPC IC for dc-dc converters.

I. INTRODUCTION

EGULATIONS like IEC-61000-3-2 demand some sortR f input current shaping for single phase equipment [l] .

Active current shaping is usually used in the power range

around 2 kW in order to reduce the volume of the converter

and the converter usually consists of a conventional diode

bridge followed by a dc-dc switch-mode converter which

shapes the current. An active power factor correction (pfc)circuit with variable output dc-voltage as a supply in a low-

cost adjustable speed induction motor drive is interesting

from a drive-design point of view because there exists only

high switching frequency in the rectifier. The pfc control

technique in a low-cost motor drive must be simple and

robust.

There exist a variety of control techniques for switch mode

converters and power factor correction circuits and most of

these techniques are supported by commercial and avail-

able ICs for the basic converter topologies like boost, buck,

buck-boost, push-pull, forward, flyback, sepic, kuk etc. [2],

[3]. Different pfc control techniques are compared in [3].

Average Current Control (ACC) is relative immune to-

wards noise because only average signals are used but ACCrequires a current reference generator which may be expen-

sive. CPC is inherently more sensitive towards noise and

circuit layout must be done very carefully but CPC is a sim-

ple control technique which provides cycle-by-cycle current

limiting, and the use of a wave-shaping reference generator

can be omitted. Stability of CPC has been subjected to in-

tense study in the literature (cf. [2]-[12])but stability is not

an issue if the switch duty cycle is restricted into a range

equal to one half of the switching period. This range can

be 0 2 d 5 1/ 2 or 1/2 2 d 5 1 depending on the control

strategy which will be shown later. Limit cycle, hysteresis

or bang-bang current control is a simple technique which

is sensitive towards noise in the same manner as CPC and

this technique also requires two current reference genera-

tors[l4]. In addition, hysteresis control, in its most simple

structure, has a variable switching frequency. Borderline

control is basically a hysteresis control technique where the

lower boundary is zero. In addition there exist some typesof control techniques which requires no direct current ref-

erence and are therefore relative immune towards input

voltage distortions[151, 161. Compliance with IEC-61000-

3-2 depends strongly on the choice of switching frequency

and switching inductance for CPC whereas ACC and limit

cycle control are able to comply with IEC-61000-3-2 re-

gardless (practically) of the switching frequency and the

switching inductor. A summary of these statements are

listed in Table I.

CPC is an interesting control method when costs and

complexity must be minimized at the expense of line cur-

rent performance.

This paper describes a new simple C PC technique with

constant command current and without ramp compensa-

tion for the two-switch buck-boost pfc converter capable

of complying with IEC-61000-3-2. The output dc-voltage

can be varied by adjusting the command current and the

application used here is a pfc dc voltage supply for a PAM

inverter. Since no commercial IC exists for controlling this

converter topology a control strategy based upon existing

CPC ICs is developed and tested in the laboratory.

11. CURRENT ROGRAMMEDONTROL

Current Programmed Control (CPC) has been described

heavily in the literature (cf. [2]-[12]) and the major issue

has been the stability analysis because conventional CPCinherently becomes unstable, when the switch duty cycle

is greater than 1/2. Ram p compensation can be added in

order to expand the range of stability. F ig. l a depicts the

basic idea behind CPC for continuous conduction mode.

The switch is turned on at the beginning of each switch-

ing period and the switch is turned off at the time instant

when the inductor or switch current equals the command

current IC. This kind of CPC is here denoted as Upper-

Boundary-Current-Programmed-Control (UBCPC).

0-7803-6618-2/01/$10.000 2001 IEEE 350



TABLE I

CONTROL ECHNIQUESOR P F C CIRCUITS. t FOR O N V E N T I O N A L I MP L E ME N T A T I O N . DEPENDSN THE N O M I N A L POWER LEVEL. DCM:

DISCONTINUOUS C O N D U C TIO N MODE , CCM: CONTINUOUS CONDUCTION MODE.

Technique

Average

Current

1 Control 1 1 Frequency t I Operating I Line Current I Cost I Complexity IMode Harmonics

Con stan t DCM+CCM Low High High

PeakCurrent

Current

Consta nt DCM+CCM Low/ Medium Medium

Constant DCM+CCM Low/ Low Low

Medium

Hysteresis

Borderline

Automatic

4 4

Variable DCM+CCM Low Medium Medium

Variable Borderline Low Low Medium

Constant DCMSCCM Medium/High Low Low

O T 2 T t 0 T 2 T t

4 b)

Fig. 1. Waveforms of inductor current ZL and the switch control

signal q for a) Upper-Boundary-CPC and b) Down-Boundary-

C PC

Clamping

Fig. l b shows another CPC technique where the switch

is turned off at the beginning of each switching period and

the switch is turned on at the time instant when the in-

ductor current drops to the command current I,. This

kind of CPC is here denoted as Down-Boundary-Current-

Programmed-Control (DBCPC).

UBCPC correspond to the conventional CPC technique

used in the literature. UBCPC has inherently an over-

current protection and the average inductor current per

switching period is always lower than the command cur-

rent. In contrary, DBCPC needs an addit ional over-current

protection which can be realized by a single comparator.

The average inductor current per switching period is al-

ways higher than the command current for DBCPC. Since

UBCPC detects the current during the on-time of the

switch the switch current can be measured which is not

possible in DBCPC because DBCPC detects the current

during the off-time of the switch. Detecting the switch cur-

rent enables switch protection and the current detecting re-

sistor has lower omich losses because the current only flows

during the on-time. Premature detection of the switch in-

stant can be a problem when detecting the switch current

because the switch current is the sum of the inductor cur-

rent and the diode reverse recovery current during turn-on.

Since DBCPC only detects the current during the off-time

of the switch the noise problems related t o reverse recovery

current are eliminated. Both UBCPC and DBCPC will be

used in this paper.

Medium

Fig. 2. Two switch Buck-boost converte r topology.

111. CONVERTEROPOLOGY

Single phase Power Factor Correction (pfc) in the power

range around 2 (kW) is usually achieved by a conventional

boost converter. If the dc-voltage has to be varied accord-

ing to the actual operating point a buck-boost or buck type

of converter must be utilized. The two switch buck-boost

rectifier shown in Fig 2 is found to the most promising

buck-boost topology in [13] for single phase power fac-

tor correction with variable dc-voltage at the power level

around 2 kW and this topology is therefore selected for

analysis in this paper. This converter is described in [17].

The converter has two operating modes: a buck mode

and a boost mode. Buck mode occurs when the rectified

voltage v r e f is higher than the dc-voltage U&, and boost

mode occur when the rectified voltage is lower than the

dc-voltage. The boost switch (sz) is turned off constantly

in buck mode and only the buck switch (SI) s modulated

in buck mode. The buck switch is turned on constantly

in boost mode and only the boost switch is modulated in

boost mode. A disadvantage of the buck-boost topology is

the need for a mode detection function.

Previously, no reported C PC technique has been adapted

to the present buck-boost topology and commercially con-

trol ICs are only available for UBCPC. The developed CPC

technique will be described here and is shown in Fig. 3.

When the converter operates as a boost converter UBCPC

is used with a constant current command and without ramp

compensation which means that the duty cycle is limited

to 1/2 . The inductor current ripple decreases to zero as the

rectified voltage increases towards the dc-voltage because

the on sta te inductor voltage becomes zero. The boost

351



Fig. 3. Simulated waveform at Vd,= 250 V. Top: rectified voltageMiddle:v,,,), dc-voltage ( v d , ) and converter mode (mode).

Inductor current ( i ~ ) nd bottom: duty cycles.

switch duty cycle also drops to zero.

steady-state

waveform \

r

(W+Z)T wT T t4

Perturbed

(W+i?))T wT T t

The average input current per switch period increases

from the zero crossing towards the point where the dc-

voltage and the rectified voltage becomes equal and the

converter shifts to buck mode. If UBCPC is used in the

buck mode then the average input current per switch pe-

riod will decrease when converter shifts from boost mode

introduces low order harmonics. If DBCPC is used in the

riod will continue to increase as it did in boost mode. Thus,:$ TTQp,,p ,A nQpDp Or _ im

Fig. 4. Definition of waveforms for a) UBCPC and b) DBCPC.

and the current at the switching instant i ~ ( w T )s

to buck mode if the same current command is used which i~ (urT )= i~(O)+m,wT * (1)

(2 )i ~ ( w T )i~(0)

w =buck mode then the average input current per switch pe- m,T

,--,, where i~(0)s the current at the beginning of the switchingAI VUWL w aiiu UYWA w mc UDGU ALL U U U D ~ auu U U L ~uvus . . m m. . . .. . I .. .. . . .respectively and the command current is constant then the

average input current per switch period will be unaffected

by the topology mode shift. Fig. 3 also shows the duty

cycles and it appears that the buck duty cycle decreases

smoothly from unity at the topology mode shift but the

buck switch duty cycle is higher than 1 / 2 in the entire

buck range. Conventional CPC without ramp compensa-

tion becomes unstable when the duty cycle exceeds 1 / 2 and

the next section will describe the stability in a generalized

manner regardless if UBCPC or DBCPC is used.

IV . STABILITY

The stability range of CPC is generalized here and the

derivations is based on the simple model as presented in [2].

This known model assumes constant current slopes and ne-

glects the effects of the modulator. The analysis assumes

that the current slopes (man,m, f f )and the command cur-

rent I , are constant during a switch period.

-

period 1 . i'he current at the end or the switching period

becomes

ZL(T) = i~(urT)+m,uT + (3 )

(4)

Thus in steady state (m , =M,, mu = Mu, = W,U =U ) he volt-second balance yields

(5)= M,WT+M,UT +

This equation shows the volt-second balance in steady

state, where the error is zero. In the ideal case the entire

range of switch duty cycle can be utilized without stability

problems but these ideal considerations are not sufficient in

reality because stability becomes a problem due to noise,delays and other nonideal effects.

The stability will be calculated and analysed by intro-

ducing a small perturbation ~ ( 0 )f the initial inductor

current i~(0)cf. Fig. 4). The current becomes

The slope before the switching instant is denoted m,and the slope after the switching instant is denoted mu

and, consequently, the corresponding duration are denoted

w and U respectively. Fig. 4 show the definition s of the

inductor current steady stat e and perturbed waveforms in iL(o)= I,(o) + E , l ( 0 ) where J E , ~ ( o ) J IIL(o)l (7)

UBCPC (Fig. 4a) and in DBCPC (Fig. 4b).

Where IL (O) is the ideal steady state inductor current

at the beginning and at the end of a switching switchingt first the ideal case is shown where the error is zero

352



TABLE I1

STABILITYOR UBCMC A N D DBCMC.

period. It should be noted that the error relates to the

deviation from steady sta te operation. The current error at

the switching instant and at the end Q(T)of the switching

period are

where G denotes the perturbed value of w . Equation

(8) shows the relation between the initial error and the

error after a switching period. After n-switching periods

the error can be written as

where

When n increases towards infinity the error becomes

Thus, the stability is determined by the variable p which

demands W < 0.5 but there has been no assumption on

whether W is the switch duty cycle D or the complement

of the switch duty Q = 1- D cycle. Table I1 depicts the

stability range without ramp compensation for UBCMC

and DBCMC respectively.

The generalized description shows that the stability

range is inverted when changing between UBCMC and

DBCMC. Thus, stable operation with duty cycles greater

than 0. 5 can be achieved without ramp compensation by

using DBCMC.

V. REALIZATION

Fig. 5 depicts the control diagram of the developed CPC

technique. The control is based on a commercial CPC con-

trol IC for dc-dc converters with limited duty cycle. In

order to implement the DBCPC technique when the con-

verter operates in buck mode the error signal and the gate

signal are both inverted. The error signal is inverted in

buck mode by the multiplier. The signal to the multiplier

from the mode signal is unity in boost mode and is equal to

-1 in buck mode. T h u s the multiplier has no effect in boost

mode. The logic on the output makes the buck switch

353

Fig. 5. Control diagram.

Fig. 6 . Simulated waveforms at U&= 250 v. Top Inductor current

and the reference current. Middle: Error current and topology

mode signal. Bottom: Error current to the comparator.

turned on in the entire boost mode and the boost switch

turned off in the entire buck mode.

Fig. 6 shows simulated waveforms at v d c =250 V and fig.

7 shows measured waveforms at Vd , =250 V. The bottom

plot shows the error signal feed to the current compara-tor and the inversion of the error signal in buck mode is

obvious.

VI . RESULTS

Simulation and experimental results are presented and

compared. Table I11 depicts the nominal system parame-

ter used. It should be noted that no design optimization

has been done in order to select the values listed in table 111.

Fig. 8 shows the inductor current, the rectified voltage,

the dc-voltage and the topology mode signal. It appears

how the converter shifts between UBCPC and DBCPC

when the rectified voltage signal crosses the dc-voltage sig-

nal.

Fig. 9 and 10shows simulated and measured waveforms

at v d c =220 V respectively, and Fig. 11and 12 shows simu-

lated and measured waveforms at V d c =250 v respectively.

From fig. 6-12 it can be seen that simulations and mea-

suremente exhibit similar waveforms and verifies the func-

tionality of this CPC technique developed to the two-switch

buck-boost converter. The line current is practically unaf-



26 ACqSIf ] il e k 1.00MWS

: . . . . . . . . . . .. . : . . . . . . . > , . . : . . . . .

Parameter

L

f s

RLoad

L f

c.fc d

v d c , n o m

fhp

R i n e

---.a

Value Unit

600 pH28 kHz

100 R

400 pH

470 pF320 V

50 Hz

4 PF

230 v,,,

I . . . . . . . . . . . _I

15.00 V M1.00ms Line/ 1O.OV

Ref3 10.0mV 1.00ms

Measured waveforms at U&= 250 V. Top: Indu ctor current

(5 A/div) and th e reference current. Middle: Error current and

topology mode signal (2 A/div). Bottom. Error current to the

comperator (2 A/div).

Fig. 7

TABLE 111

System paramete rs for the buck-boost converter

Tek 500kS/s 2 0 ACqS. ..... - -T ... I ...

I , , : t

Ch l 5 0 0mV Ch2 5OOmV M2 OOms L i n e 1 2. 7 VCh3 5 .OOV rSm 10.0mVR

Fig. 8. Measured waveforms a t v d c =200 V. Top: Inductor current.

Bottom: Rectified voltage, dc-voltage and mode signal.

1

I(I ) 41

II

Fig. 9. Simulated waveforms at u d c = 220 V. Top: Mode signal and

inductor current. Bottom: Line current.

TeK 5 2 Acqs00kS/sT _ _ _..- -..-

I ' '

Fig 10 Measure d waveforms at U&= 220 V Top: Topology mode

signal (High:buck an d 1ow:boost). Middle. Induct or current at2 A/div Botto m. Line current at 2 A/div.

Fig. 11. Simulate d waveforms a t U&= 250 V. Top: Mode signal and

inductor current. Bottom: Line current.

354



Fig. 12. Measured waveforms at U,,= 250 V. Top: Topology mode

signal (High:buck and 1ow:boost). Middle: Inductor current at

2 A/div. Bottom: Line current at 2 A/div.

Stairs:lec61000-3-2 limits circles: Measured3r I

0 10 20 30 40

Harmonic numbern

Harmonic numbern

Fig. 13. Harmonic spectra of th e line current and the IE C 61000-3-2

limits. Top: T he harmonic current for the measurement in fig.

10. Bottom: The harmonic current for the measurement in fig.

12.

fected by the topology mode shift. The small disturbance

in the line current at the topology shift is due to the fact

tha t t he input filter is exposed to a load step because the

buck switch current shifts between continuous and discon-

tinuous as the converter shifts between boost and buck.

Additional damping of the input filter can be added in

order to decrease this disturbance. The dc-voltage can di-

rectly be controlled by the command current which in total

makes it a simple pfc technique.Fig. 13 shows the harmonic currents for the measure-

ments in fig. 10 & 12 and the limits set by IEC 61000-3-2.

It appears that the th is control method complies with IEC

61000-3-2 in both cases.

VII. CONCLUSION

A new Current Programmed Control technique has been

developed to the cascaded two switch buck-boost pfc con-

verter which use constant command current and without

ramp compensation. The control circuit is build on a com-

mercial CPC IC for dc-dc converters with a maximum duty

cycle at 1/2. This new control technique enables a simple

low-cost control circuit for the two switch buck-boost con-

verter which complies with IEC-61000-3-2. This new sim-

ple pfc circuit has inherent inrush and over current protec-

tion.

The new CPC technique described and considered in this

paper is a generalization of the conventional CPC technique

which can be used in many other applications directly. Sim-

ulations and experimental results verify the functionality of

the developed C PC technique where the stability range can

be shifted between 0 5 d 5 1/2 or 1/2 5 d 5 1 without

introducing ramp compensation.

The developed control technique can be advanced by

adding ramp compensation in order to expand the range

of stability. The command current could be modulated to

emulate the rectified voltage in order to provide high power

factor performance.

VIII . ACKNOWLEDGMENTS

The authors wish to thank the Power Electronics Labo-

ratory a t th e Department of Electronics and Informatics at

the University of Padova in Italy where the experimental

part of this paper has been carried out.

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