Current buffer compensation topologies for LDOs with improvedtransient performance

Annajirao Garimella • Paul M. Furth •

Punith R. Surkanti • Nitya R. Thota

Received: 19 January 2011 / Revised: 27 September 2011 / Accepted: 4 November 2011

� Springer Science+Business Media, LLC 2011

Abstract The goal of internal frequency compensation of

a low dropout voltage regulator (LDO) is the selection of a

small-value, ESR-independent output capacitor. Cascode

compensation formed by a common-gate transistor acting

as a current buffer, an optional series resistor, and a com-

pensation capacitor creates a dominant pole and a left-half-

plane (LHP) zero, allowing adequate phase margin and

stable LDO design. To this end, a 1.21 V output, 100 mA,

0.1–10 lF output capacitor, ESR-independent, low voltage

LDO using cascode compensation with replica bias is

designed and fabricated in a 0.5 lm CMOS process with an

area of 0.22 mm2. A line regulation of 0.05% V/V, load

regulation of 0.001% V/mA and dropout voltage of

220 mV were measured. LDO-specific pole-zero analysis

is detailed. In addition to this design, two improved tran-

sient response LDO architectures using cascode compen-

sation with split-length transistors are also explored.

A Power Good feature is discussed, which enables direct

interface between the LDO and a micro-processor.

Keywords Low dropout voltage regulator (LDO) �Miller

compensation � Cascode compensation � Split-length

transistors � Current buffers � Feedback amplifiers �Wide-swing differential amplifier

1 Introduction

Power management circuits are becoming ubiquitous

and challenging, with the proliferation of System-on-Chip

(SoC) integration and functionality. Traditionally the

Power Management Unit (PMU), consisting of regulated

power supply circuits, was implemented as a separate

design or as an off-the-shelf IC. SoCs with an integrated

PMU enable the design of electronic systems with drasti-

cally reduced PCB area, number of external components,

and bill of materials [1].

Low dropout voltage regulators often require a large off-

chip external output capacitor for stability and improved

transient-response, which cannot be integrated on the SoC.

Capacitor-free LDOs completely eliminate the off-chip

capacitor [2]. Alternatively, LDO designs using low-value

and/or wide-range off-chip capacitors are becoming

important [3–6], as the PCB area and bill of materials can

be reduced. The proposed LDO is stable for a wide range of

off-chip output capacitors, in particular 0.1–10 lF ceramic

or MLCC. An additional feature of the LDO is a digital

Power Good output, used for power-up sequencing. It is

asserted digital low when the regulated output voltage falls

below its nominal value. This LDO is aimed for battery-

powered micro-processor systems.

1.1 Outline

In this paper we present a replica-biased two-stage LDO with

cascode compensation which is fabricated in a 0.5 lm CMOS

process and measured. In addition, we also explore two other

LDO topologies using split-length cascode compensation.

Section 2 describes three types of compensation networks:

Miller, cascode and split-length cascode compensation. The

proposed replica-biased LDO design, pole-zero analysis,

A. Garimella (&) � P. M. Furth � P. R. Surkanti � N. R. Thota

Klipsch School of Electrical and Computer Engineering, New

Mexico State University, Las Cruces, NM 88003, USA

e-mail: garimella@ieee.org

P. M. Furth

e-mail: pfurth@nmsu.edu

P. R. Surkanti

e-mail: punith@nmsu.edu

N. R. Thota

e-mail: nityat@nmsu.edu

123

Analog Integr Circ Sig Process

DOI 10.1007/s10470-011-9811-6

phase margin optimization and Power Good output are

explained in Sect. 3. Experimental results of the replica-biased

LDO are summarized in Sect. 4. The design and simulation of

LDO topologies with split-length cascode compensation are

described in Sect. 5. Section 6 details the circuitry of the

Power Good feature. Conclusions are drawn in Sect. 7.

2 Compensation network

The choice of frequency compensation is key for the sta-

bility of an LDO.

2.1 Miller compensation

In conventional Miller compensation, shown in Fig. 1, the

compensation capacitor CMILLER forms a feedforward path

[7] that couples the input node of the second stage V1

directly to the output terminal VOUT, introducing a right-

half-plane (RHP) zero. Circuit analysis of Fig. 1 gives the

location of this RHP zero at

xZ1 ¼ gmp=½CMILLER � RZCMILLERgmp þ Cgd;PASS�: ð1Þ

This RHP zero can be eliminated or moved to the left-half

plane (LHP) by proper selection of RZ.

2.2 Cascode compensation

Cascode compensation, also known as Ahuja compensa-

tion, introduced in [7, 8] and utilized in [3, 4, 9–13], uses

Miller compensation with a common-gate transistor as a

current buffer, obviating the RHP zero, introducing an LHP

zero and thus improving stability. The two-stage op-amp in

[11] utilizes cascode compensation and unconditional sta-

bility is achieved with an output capacitive load from

10 pF (no-load) to 100 nF. This kind of output capacitance

variation is desirable in LDOs.

As shown in Fig. 2, the compensation capacitor CCAS is

connected between VOUT and the internal node V1 through

a common-gate transistor amplifier MCG, eliminating the

feedforward path. IC is a dc bias current entering and

leaving node V1, forming a virtual open at node V1.

The location of the LHP zero is given by

xZ;CAS ¼ �gmCG

CCAS: ð2Þ

In Miller compensation, an external nulling resistor RZ

was used to either eliminate the RHP zero or move it to the

LHP. Instead of a resistor, a current buffer with low input

impedance is used in cascode compensation to create an

LHP zero by removing the feed-forward path. Cascode

compensation also offers a wider range of output capacitor

for the same value of compensation capacitor by a factor of

(CCAS/C1), where C1 is the equivalent capacitance to

ground at node V1 [8].

2.3 Cascode compensation with programmable zero

location

At times, it is not possible to move the LHP zero (to cancel a

pole) due to sizing constraints on the common-gate transistor

MCG and area constraints on CCAS. A simple and effective

method of moving the LHP zero is to place a series resistor

RCAS between the source node of the common-gate transistor

MCG and compensation capacitor CCAS, as illustrated in Fig. 3.

_

+

CMILLER

g

RZ

m1

MPASS

VOUT

VLINE

ILOAD

RF1

RF2

COUT

RESR

VREF

Cgs,PASS

Cgd,PASS

-gmp

V1

Feedforward Path

Fig. 1 Two stage LDO utilizing Miller compensation with nulling

resistor

_

+MCG

CCAS

VOUT

VCG

V1

Feedforward patheliminated

gm1

-gmp

Virtual open

Ic

Ic

CCAS

g1mCG

CAS

mCGZ

C

gω −=

(a)

(b)

VOUT

Fig. 2 a Cascode compensation scheme. b Small-signal model of the

compensation network and equation of LHP zero

CCAS

g1mCG

( ) CASmCGCAS

ZCgR

ω1

1

+−=

RCASMCG

VCG

V1

Ic

CCASRCAS

VOUT

(a) (b)

Fig. 3 a Cascode compensation scheme with series resistor. b Small-

signal model of compensation network and equation of LHP zero

Analog Integr Circ Sig Process

123

The location of the new LHP zero is given by

xZ ¼ �1

1=gmCG þ RCASð ÞCCAS� � 1

RCASCCASð3Þ

As the value of RCAS increases, the LHP zero becomes

more dominant. The technique of adding a series resistor to

cascode compensation networks was recently demonstrated

in [13–16].

2.4 Cascode compensation using split-length

transistors

In [17, 18], the authors introduce the technique of split-

length transistors, in which a low-impedance node is cre-

ated by splitting a transistor of length L into two series

transistors of length L1 and L2, where L1 ? L2 = L, as

shown in Fig. 4(a,b). The bottom transistor always operates

in the triode, or linear, region. The technique of cascode

compensation using split-length transistor can be extended

to include an optional series resistor, as shown in Fig. 4(c).

Assuming MSL1 and MSL2 are matched, the location of

the new LHP zero is given by

xZ;SL ¼ �1

1=gmSL þ RCASð ÞCCAS� � 1

RCASCCASð4Þ

3 Design of the proposed LDO

Figure 5 shows the schematic of the proposed low dropout

voltage regulator [19], which consists of an error amplifier, a

PMOS pass transistor MPASS, a sampling network, a cascode

compensation network with replica bias and bias transistors.

MCG is the common-gate transistor amplifier, or the

cascode transistor, used for compensation. The compen-

sation capacitor CCAS is connected between the output node

VOUT and the source terminal of transistor MCG.

The dc bias current sinking from V1 to ground through

MCG and M7 is IC. A replica bias, similar to the one in [9],

formed by MCGR and M7R is utilized to source IC at node V1.

Current mirror transistors M3 and M4 are reutilized instead

of adding two more PMOS bias transistors. Transistor MCGR

is also a cascode transistor, and reduces VDS mismatch

between M7R and M7 and improves current matching. Rather

than using a separate voltage VCG, as in Fig. 2, the gate

terminals of MCG and MCGR are connected to the voltage

reference VREF. The dc current IC is a scaled version of IBIAS,

in order to reduce the total quiescent current.

Small value capacitors CF1 and CF2 are connected in

parallel with sampling feedback resistors RF1 and RF2,

respectively, to filter high frequency noise and to improve

high frequency response, as described in [5].

Device dimensions of the LDO using cascode compensa-

tion with replica bias are summarized in Table 1. The ratio of

sampling resistors RF1/RF2 determines the output voltage.

The larger the value of RF1 and RF2, the lower the resistor bias

current. Hence, RF1 is chosen as 20 kX and RF2 is chosen as

200 kX for a bias current of 5.5 lA. The size of the PMOS

pass element MPASS is determined by the maximum output

current, 100 mA, and desired dropout voltage of 200 mV.

Transistor length is approximately inversely proportional to

bandwidth and directly proportional to matching and gain.

We selected a default value for transistor length of 1.2 lm,

two times the minimum, for moderate gain, good matching,

and high speed. PMOS transistors have a width of approxi-

mately three times that of NMOS transistors at the same bias

current, so as to achieve the same transconductance.

3.1 Pole-zero analysis

The small-signal equivalent model of the LDO using cas-

code compensation is shown in Fig. 6. The loop-gain

transfer function of the LDO is given by

T sð Þ ¼ vfb

vsðsÞ

¼ ADCð1þ s=xZ1Þð1þ s=xZ2Þð1þ s=xZ3Þð1þ s=xP1Þð1þ s=xP2Þð1þ s=xP3Þð1þ s=xP4Þ

;

ð5Þ

where ADC is the DC loop gain. The system has three zeros

and four poles. R1 is the resistance, C1 is the capacitance and

gm1 is the transconductance associated with node V1. The

transconductance of the common-gate transistor amplifier

MCG is gmCG. R2 is the equivalent output resistance given

by Rds,PASS||(RF1 ? RF2). COUT is the output capacitance.

Cgd,PASS is the gate-drain capacitance and gmP is the

Low Impedance

Node

L = L1 + L2

(a)

(b) (c)

RCASCCASCCAS

MSL1

MSL2

WL

WL1

WL2

Fig. 4 a Split-length NMOS transistor introducing low-impedance

node [17]. b Cascode compensation using split-length transistors [18].

c Split-length cascode compensation with series resistor

Analog Integr Circ Sig Process

123

transconductance of the pass transistor MPASS. Note that

C1 = Cgd4 ? Cgd2 ? Cgs,PASS. Cgd,PASS and CCAS are of the

same order and have typical values of 10–25 pF. As such,

Cgd,PASS cannot be ignored. Capacitors CF1 and CF2 are 1 pF

each and are neglected in the frequency analysis.

The DC loop gain ADC is

ADC ¼ b gm1gmpR1R2; ð6Þ

where the feedback factor b is given by RF2/(RF1 ? RF2).

The dominant LHP zero due to cascode compensation is

xZ1 ¼ �gmCG=CCAS: ð7Þ

This LHP zero helps to increase the bandwidth. The

LHP zero due to the ESR of the output capacitor COUT is

xZ2 ¼ �1=RESR COUT : ð8Þ

The RHP zero due to the parasitic Cgd,PASS is given by

xZ3 ¼ þgmp=Cgd;PASS: ð9Þ

Assuming that the poles and zeros are widely-separated

real poles, their approximate equations and frequency values

for IL = 1 mA and COUT = 0.1 lF are given in Table 2.

Figure 7 illustrates the approximate pole-zero locations.

Referring to the values of Table 2, the first LHP zero xZ1

effectively cancels xP3; xP4 and xZ3 are located at much

higher frequencies than the unity-gain frequency (UGF) and

can be neglected for the purpose of analyzing stability.

3.2 Optimum phase margin

The phase margin u is given by [4, 11]

u ¼ 90� � arctan 1=Sð Þ þ arctanðLÞ; ð10Þ

where larger stability quality factor S corresponds to larger

phase margin. L corresponds to the effect of the LHP zero

xZ2 on the phase margin. The larger the value of L, the

higher the phase margin. S is calculated as

S ¼ xP2=xUGF ¼ xP2=ADCxP1

¼COUT=

ffiffiffiffiffiffiffiffi

gmPp� �

þ ffiffiffiffiffiffiffiffi

gmPp

R1 CCAS þ Cgd;PASS

� �� �2

gm1R21Cgs;PASS COUT þ gmP

gmCGCCAS

h i :

ð11Þ

L is calculated as

L ¼ xUGF=xZ2: ð12Þ

Ignoring the effect of L on phase margin, as xZ2 is more

than a decade higher than xP2, the minimum phase margin

IBias

M1 M2

M3 M4

M5

MPASS

MCG

V1

VOUTgm1

gmPASS

gmCG

CCAS

Cgd,PASS

Cgs,PASS

M7M6

VREFMCGR

M7R

VLINE

RF2

RF1 CF1

CF2

VFB

VFBVREF

iCiC

Bias Stage Replica Bias Error Amplifier Power StageCascode

Compensation

Fig. 5 Proposed low drop-out voltage regulator architecture using cascode compensation with replica bias [19]

Table 1 Device dimensions of the proposed LDO with replica bias

Device Bias current Dimension/value

M1, M2 40 lA 50/1.2, m = 4

M3, M4 50 lA 150/1.2, m = 4

M5 80 lA 50/1.2, m = 8

M6, M7, M7R 10 lA 50/1.2, m = 1

MCG, MCGR 10 lA 12/0.6, m = 1

MPASS 100 mA 33,000/0.6

RF1, RF2 5.5 lA 20 kX, 200 kX

CF1, CF2 – 1 pF, 1 pF

CCAS – 25 pF

m1g mPg v1g +v-fb

vout

RF1

RF2

C

+

-vs

ESRR

OUTC2

Rvs

v1

R1

C1mcgv3

mCGg1

gd,PASS

v3

CCAS

Fig. 6 Small signal equivalent model of the LDO of Fig. 5

Analog Integr Circ Sig Process

123

will occur either at qS/qgmp = 0 or at qS/qCOUT = 0.

Solving for qS/qgmp, the optimum g�mp,

g�mp ¼ COUT=½R1ðCCAS þ Cgd;PASSÞ�: ð13Þ

Substituting (13) into (11),

Smin ¼4

gm1R1

ðCCAS þ Cgd;PASSÞCgd;PASS

: ð14Þ

Solving qS/qCOUT = 0 results in the same Smin as in

(14). The value of the compensation capacitor CCAS is

given by

CCAS ¼ Cgd;PASSgm1R1

4 tanð90� � /Þ � 1

� �

: ð15Þ

From (15) we see that minimizing Cgd,PASS through

careful layout is critical to obtaining a low optimum value

for CCAS. If we were to substitute (11) into (12), we would

see that phase margin increases with COUT. In particular,

the LDO is less stable for 0.1 lF and more stable for

10 lF. Figure 8 shows the simulation of the loop gain and

phase response of the proposed LDO for the worst case

COUT of 0.1 lF.

For simulations, we used Cadence Spectre with 0.5 lm

transistor models from MOSIS. Default values used

in simulations are: VLINE = 2.5 V, VREF = 1.1 V and

IBIAS = 10 lA and typical transistor models at room

temperature.

3.3 Power Good output

A Power Good output VPG is an important feature available

in commercial LDOs [20]. It can be used to implement a

power-on-reset or low-battery indicator in portable appli-

ances and functions as a supply voltage supervisor for the

output voltage. It is asserted digital low when the output of

the LDO falls below its normal regulating level. It is

asserted high when the regulated output voltage is within

x% of its nominal value. The Power Good output can be

obtained by comparing the feedback voltage VFB with a

Power Good reference voltage VPGREF. VPGREF can be

chosen as (1 - x)% of the reference voltage, such that the

power-up sequence [21] of the microprocessor will resume

whenever VOUT is within x% of its nominal value. This

Power Good digital signal, described in detail in Sect. 6,

can be interfaced with SM Bus� or PM Bus� for system

level integration.

4 Experimental results

The proposed LDO has been implemented using a 2P3M

0.5 lm CMOS process with nominal VTP = 0.95 V and

VTN = 0.73 V. Figure 9 shows the micrograph of the LDO.

An external voltage reference VREF of 1.1 V was chosen.

An on-chip compensation capacitor CCAS of 25 pF is used.

The total experimental quiescent current IQ (except for the

Power Good circuitry) is 111 lA with IBIAS = 10 lA.

Figure 10 shows the measured power-up and power-

down response of the proposed LDO. The dropout voltage

is defined as the difference between the input line voltage

VLINE and output voltage VOUT when VOUT drops 100 mV

Table 2 Pole-zero locations

of cascode compensation LDOEquation Approx. location Equation Approx. location

xP1 ¼ � 1

R2COUTþgmpR2R1 CCASþCgd;PASSð Þ 182 Hz xZ1 ¼ � gmCG

CCAS1.34 MHz

xP2 ¼ �COUTþgmpR1 CCASþCgd;PASSð Þ

R1Cgd;PASS COUTþgmpCCAS=gmCGð Þ354 kHz xZ2 ¼ � 1

RESRCOUT16 MHz

xP3 ¼ �gmCG COUTþ gmpCCAS=gmCGð Þ½ �

CCASCOUT

1.4 MHz xZ3 ¼ þ gmP

Cgd;PASS1.1 GHz

xP4 ¼ � 1RESR

1Cgd;PASS

þ 1C1

18 GHz

xUGF ¼ � bgm1

CCASþCgd;PASSþ COUT=gmpR1ð Þ4.1 MHz

Re

ImReplica-biased LDO with Cascode Compensation

ωZ3ωP1ωP2

ωZ1

ωP3

ωZ2

ωP4

Fig. 7 Diagram illustrating pole-zero location of Fig. 5 (not to scale)10

210

410

6

-60-30

03060

Frequency (Hz)

Gai

n (d

B)

102

104

106

0

60

120

180

Frequency (Hz)

Pha

se (

Deg

rees

)

ILOAD

= 100mA

ILOAD

= 1mA

ILOAD

= 100mA

ILOAD

= 1mA

Fig. 8 Loop gain and phase response of the proposed LDO with

COUT = 0.1 lF and ILOAD = 1 and 100 mA

Analog Integr Circ Sig Process

123

below the value measured with VLINE = VOUT ? 1 V [22].

The measured value is 220 mV at a maximum load current

of 100 mA and 45 mV at a minimum load current of 1 mA.

The Power Good output VPG is asserted high whenever the

output voltage VOUT is within 5% of its nominal value.

Figure 11 shows the measured line regulation and line

transient response of the proposed LDO for COUT =

0.1–10 lF and for VLINE changing from 1.5 to 2.5 V with

rise and fall times of approximately 10 ns. The load current

is fixed at 1 mA. The measured steady-state output change

due to a 1 V step in the input voltage is DVOUT = 0.5 mV.

Hence, the line regulation DVOUT/DVLINE = 0.05% V/V.

The line transient response, which is the maximum minus

the minimum transient output voltage, is measured as

91 mV for COUT = 0.1 lF.

Figure 12 shows the measured load transient response of

the proposed LDO for 0.1–10 lF output capacitor values

when ILOAD is varied from 1 mA to 100 mA with rise and

fall times of the pulse signal that are approximately 10 ns.

The input voltage is equal to 2.5 V. The measured steady-

state output change due to a 99 mA change in load current

is DVOUT = 1 mV. Hence, the load regulation DVOUT/

DILOAD = 0.001% V/mA. The load transient response is

measured as 280 mV for COUT = 0.1 lF.

The power supply rejection (PSR), also known as ripple

rejection, measures the regulator’s ability to prevent reg-

ulated output voltage fluctuations caused by input voltage

fluctuations. For a small sinusoidal signal superimposed

on a DC input voltage of 2.5 V, the PSR is measured as

20log10(VOUT,RMS/VLINE,RMS). The measured PSR of the

proposed LDO at 100 Hz is -52.5 dB and at 10 kHz is

-45.2 dB.

Current efficiency is the ratio of the maximum output

load current to the total current supplied by VLINE. The

current efficiency is computed as ILOAD,MAX/(ILOAD,MAX ?

IQ) = 99.89%.

The performance of the proposed LDO is summarized in

Table 3. The proposed LDO provides excellent regulation

and response to line and load transients with an output

capacitor as small as 0.1 lF and with an ESR of as little as

0 X.

5 LDO architectures using current buffers

with improved transient performance

The Figure of Merit (FOM) of [3] is used to compare

different LDO architectures.

Fig. 9 Micrograph of the proposed LDO (762 lm 9 284 lm)

Fig. 10 Measured power-up and power-down response of the

proposed LDO. Input Vin (= VLINE), the off, dropout and regulating

regions of VOUT, and the Power Good output VPG can be seen

Fig. 11 Measured line transient response of the proposed LDO.

ILOAD = 1 mA

Fig. 12 Measured load transient response of the proposed LDO.

VLINE = 2.5 V

Analog Integr Circ Sig Process

123

FOM ¼ COUT DVOUT

ILOAD;MAX

IQ

ILOAD;MAX; ð16Þ

where DVOUT refers to load transient response. The smaller

the FOM, the better is the LDO performance. Fixing

ILOAD,MAX at 100 mA and COUT at 0.1 lF, we set out to

explore, through simulation, LDO architectures that reduce

one or both of DVOUT and IQ.

5.1 Cascode compensation using split-length

transistors

The schematic of Fig. 5 has two additional branch currents

for the particular implementation of cascode compensation:

one on the right of the differential pair that connects to the

compensation capacitor CCAS, and the replica on the left for

good matching. These two branch currents can be elimi-

nated if another suitable node is introduced for cascode

compensation. Figure 4 demonstrates the use of split-

length transistors to create a low impedance node [17, 18],

with the extension of adding an optional series resistor.

Figure 13 shows the schematic of a two-stage LDO that

implements split-length differential-pair (SLDP) cascode

compensation. It is also possible to split the length of the

PMOS transistors in the current-mirror M3–M4. However,

compensation close to the supply rail results in poor PSR.

Thus, for improved PSR, differential pair transistors

M1–M2 have been split [18].

One drawback of SLDP cascode compensation is that

the compensation capacitor CCAS must be larger in order to

obtain a phase margin similar to that of the proposed LDO

with replica bias. Referring to Fig. 13, the majority of

the compensation current iC through CCAS goes directly

through the channel of transistor M2A to node V1. However,

approximately one-fourth of iC goes through the source/

drain terminals of three transistors in series M2B, M1B, and

M1A. This current is then inverted through the PMOS

current mirror before reaching node V1. The result is that as

much as one-half of the compensation current is canceled.

In order to restore the net amount of compensation current

reaching node V1, CCAS must be doubled. An optional

resistor in series with CCAS was found to reduce phase

margin for any resistance value, and was therefore rejected

from this design.

In Fig. 13 the differential pair is scaled such that the

right branch has K times the bias current of the left branch.

This scaling increases phase margin and improves load and

line transient response, as more current is available to drive

the large parasitic capacitances associated with MPASS.

Two other changes in Fig. 13, as compared to Fig. 5, are

in the feedback network. CF2 is eliminated, or more pre-

cisely, replaced with the parasitic capacitances at the gates

of M1A–M1B. And resistor RF1 is split into two elements,

RF1A and RF1B. The advantage is that the newly generated

signal, VPGFB, can be compared directly to VREF in the

Power Good circuit, thereby eliminating the need for a

second reference voltage signal VPGREF from the design.

5.2 SLDP cascode compensation with a wide-swing

differential amplifier

The major drawback of the circuit in Fig. 13 is that the

dropout voltage is increased, as compared to the proposed

LDO with replica bias. There are now three series devices

between node V1 (the gate of MPASS) and ground, M2A,

M2B, and M5. Reducing the number of series devices

between the gate of MPASS and ground can result in sig-

nificantly lower dropout voltage.

The circuit of Fig. 14 employs SLDP cascode com-

pensation with the addition of two current mirrors to create

Table 3 Measured performance summary of the LDO

Input voltage range, VLINE 1.43–3.3 V

Regulated output voltage

VOUT

1.21 V

Load current range, ILOAD 1–100 mA

Line regulation, DVOUT%/

DVLINE

0.05% V/V

Load regulation, DVOUT%/

DILOAD

0.001% V/mA

Max load transient DVOUT 280 mV with COUT = 0.1 lF

Dropout voltage, Vdrop-out 45 mV with ILOAD = 1 mA,

220 mV with ILOAD = 100 mA

PSR –52.5 dB at 100 Hz, –45.2 dB at

10 kHz

Output Cap value, COUT 0.1–10 lF

Output Cap type Ceramic, MLCC

Power Good output, VPG Digital high @ 95% of VOUT

Process 0.5 lm CMOS 2P3M

Area 762 lm 9 284 lm

IBias

M3 M4

M5

MPASSV1

VOUT

CCAS

M6

VREF

VLINE

CF1

VFB

RF2 CF2

VFB

VPGFB

RF1A

RF2B

M1A

M1B

M2A

M2B

1 : K

1 : K

1 : K

iC

Bias Stage Error Amplifier Power Stage

Fig. 13 Schematic of LDO with SLDP cascode compensation

Analog Integr Circ Sig Process

123

a wide-swing differential amplifier (WSDA) [17]. K-times

transistor scaling is moved from the differential pair in

Fig. 13 to the output of the WSDA in Fig. 14. Node V1 is

now pulled towards ground with only one series device,

M11. The dropout voltage is decreased to such an extent

that reducing the size of MPASS and CCAS by 33% becomes

feasible.

The addition of a small-value resistor RCAS in series with

CCAS results in improved load transient response, with lit-

tle-to-no effect on line transient response and PSR. RCAS is

thus included in the design.

A complication arising from the WSDA in Fig. 14 is

poorer line regulation and PSR, as compared to the LDO

with replica bias. This complication can be ameliorated

with the addition of transistor M12, a cascode transistor that

attempts to equalize VSD for the current mirror formed by

transistor M3 and M13. In order to bias the gate of M12, an

additional current branch formed by transistors M7–M9

becomes necessary.

Device dimensions for the LDO employing SLDP cas-

code compensation and the LDO using SLDP cascode

compensation with WSDA are given in Table 4.

The three LDO architectures using current buffer com-

pensation described in this work were simulated for com-

parison purposes. Figure 15 shows the simulated load

transient response for (a) the LDO using replica bias, (b) the

MPASS

1 : K

1 : K

VLINE

RCASCCAS

VOUT

VFB

VCP

VREF

V1IBIAS

M12

M13 M14

M11M10

M3 M4

M5M7M6

M9

M8

M1A M2A

M2BM1B

CF1

RF2 CF2

VFB

VPGFB

RF1A

RF2B

Bias Stage Error Amplifier Power Stage

Fig. 14 Schematic of LDO using SLDP cascode compensation with a WSDA

Table 4 Device dimensions of LDOs with improved transient performance

Bias currents SLDP cascode

compensation (Fig. 13)

Bias currents SLDP cascode

with WSDA (Fig. 14)

M1A, M1B 10 lA 50/0.6, m = 1 10 lA 50/0.6, m = 2

M2A, M2B 80 lA 50/0.6, m = 8 10 lA 50/0.6, m = 2

M3 10 lA 150/1.2, m = 1 10 lA 150/1.2, m = 1

M4 80 lA 150/1.2, m = 8 10 lA 150/1.2, m = 1

M5 90 lA 50/1.2, m = 9 20 lA 50/1.2, m = 2

M6 10 lA 50/1.2, m = 1 10 lA 50/1.2, m = 1

MPASS 100 mA 33,000/0.6 100 mA 22,200/0.6

M7, M10 10 lA 50/1.2, m = 1

M11 80 lA 50/1.2, m = 8

M8, M9, M12, M13 10 lA 150/1.2, m = 1

M14 80 lA 150/1.2, m = 8

RF1A, RF1B 5.5 lA 19 kX, 21 kX 5.5 lA 19 kX, 21 kX

RF2 5.5 lA 400 kX 5.5 lA 400 kX

CF1, CCAS 2 pF, 37.5 pF 2 pF, 25 pF

Analog Integr Circ Sig Process

123

LDO using SLDP cascode compensation, and (c) the LDO

using SLDP cascode compensation with WSDA for the

condition that COUT = 0.1 lF and VLINE = 2.5 V. The total

change in output voltage is the smallest for the LDO using

SLDP cascode compensation with WSDA.

Table 5 compares the hardware and simulated perfor-

mance characteristics of the proposed LDO using cascode

compensation with replica bias (Fig. 5). Simulated per-

formance characteristics are also given for the two LDOs

with improved transient performance. Measured results are

in good agreement with simulated values for the proposed

LDO. The FOM, defined in (16), is 0.311 ns for hardware

measurements and 0.285 ns for simulated measurements,

differing by \10%. FOM decreases to 0.162 ns for the

LDO with SLDP cascode compensation and decreases

further to 0.150 ns with the use of a WSDA.

6 Power Good comparator circuit with hysteresis

The schematic of a Power Good comparator circuit is given

in Fig. 16. A differential amplifier, powered by the unregu-

lated input voltage VLINE, compares the reference voltage

VREF to VPGFB, a signal generated by feedback resistors in

Figs. 12 and 13. Two series inverters, powered by the regu-

lated output voltage VOUT, further amplify the output of the

differential amplifier. By powering the inverters with VOUT,

the output logic levels of VPG are guaranteed to be compatible

with those of the micro-processor that it may be resetting.

The Power Good comparator of Fig. 16 incorporates

hysteresis using an unbalanced differential pair [23, 24].

The amount of hysteresis is adjustable through the bias

current of transistor M11. In order to obtain a hysteresis

voltage of approximately 10 mV, transistor M11 was sized

1/16th the value of M5. Device dimensions for the Power

Good comparator circuit are given in Table 6.

A power-up and power-down transient simulation of the

LDO using SLDP cascode compensation with WSDA is

shown in Fig. 17 under the condition of ILOAD = 100 mA.

5 10 15 20 25 30 35 40

0

0.2

0.4

0.6

0.8

1

1.2

1.4

Time (us)

VO

UT (

V)

ILOAD

1mA

(a)

(b)

(c)

100mAdI

L/dt = 10ns

Fig. 15 Transient load response of LDOs using: a cascode compen-

sation with replica bias, b SLDP cascode compensation, and c SLDP

cascode compensation with WSDA. COUT = 0.1 lF, VLINE = 2.5 V

Table 5 Comparison of

Performance Characteristics of

LDOs

Hardware measurements Simulated measurement results

Replica

biasing

Replica

biasing

SLDP

cascode

SLDP with

WSDA

VOUT (V) 1.21 1.21 1.21 1.21

ILOAD,MAX (mA) 100 100 100 100

VDROP-OUT (mV) 220 262 386 212

Output Cap (lF) 0.1 0.1 0.1 0.1

IQ at full load (lA) 111 111 84.2 113

Load transient DVOUT (mV) 280 256 192 133

FOM (ns) 0.311 0.285 0.162 0.150

Current efficiency at ILOAD,MAX (%) 99.89 99.89 99.92 99.89

Line Transient DVOUT (mV) 91 78.0 64.8 104

PSR

100 Hz (dB) -52.5 -58.7 -70.4 -42.4

10 kHz (dB) -45.2 -55.4 -61.9 -42.3

100 kHz (dB) – -37.0 -42.0 -39.4

Regulation

Line (V/V) 0.05% 0.092% 0.072% 1.38%

Load (V/mA) 0.001% 0.008% 0.007% 0.007%

W/L of MPASS (lm/lm) 33,000/0.6 33,000/0.6 33,000/0.6 22,000/0.6

Total CC (pF) 27 27 39.5 27

Analog Integr Circ Sig Process

123

The Power Good signal VPG is asserted high when VOUT is

within 5% of its nominal output value of 1.21 V. Hysteresis

is measured as 11 mV.

7 Discussion and conclusions

This paper presents a wide-range output capacitor, ESR-

independent, CMOS low drop-out voltage regulator, which

utilizes current buffer compensation in the form of cascode

compensation with replica bias to improve stability. Simu-

lation and experimental results agree in demonstrating the

effectiveness of the proposed approach. Furthermore, two

LDO architectures which utilize cascode compensation with

split-length transistors are explored through simulation,

demonstrating notable improvements in terms of load tran-

sient and FOM, which are summarized in Table 5. The load

transient DVOUT of LDO with SLDP cascode compensation

is 192 mV and DVOUT of LDO with SLDP ? WSDA is

133 mV. The FOM of both LDO architectures is reduced by

as much as 47%, from 0.285 to 0.150 ns.

The LDO with SLDP exhibit an improvement in PSR by

5 dB or higher for a frequency range of 1–100 kHz. The pass

transistor size of the LDO with SLDP ? WSDA is 22,000 lm,

which is 33% less than the other LDOs and the compensation

capacitor is 27.5 pF similar to the proposed replica-biased

LDO, resulting in a modest reduction in the overall area.

The performance of these LDO topologies, in general,

improves with process technologies below 0.5 lm. For

example, a transistor length reduction results in reduced

dropout voltage and reduced parasitic capacitances asso-

ciated with pass transistor. The bandwidth of the LDO

increases, which provides for faster response time for line

and load transients and correspondingly lower DVOUT.

Finally, the area of the compensation capacitors and pass

transistors would be smaller, which results in a reduction of

overall footprint of the LDO.

Acknowledgments The authors thank MOSIS for chip fabrication

support. The authors would like to also thank M. Wasequr Rashid,

Georgia Institute of Technology, GA, Sri Raga Sudha Garimella, Intel

VLINE

VOUT

VPGVREFVPGFB

IBIAS

VPG

M3 M4

M1 M2

M5M6

M12 M13

M11 M7

M8 M10

M9

Bias Stage Differential Amplifier Hysteresis Circuit Inverters

Fig. 16 Power Good comparator with hysteresis using an unbalanced differential pair

Table 6 Device dimensions of

the Power Good comparator

with hysteresis

M1, M2 50/1.2, m = 1

M5 50/1.2, m = 2

M3, M4, M8 150/1.2, m = 1

M6, M7 50/1.2, m = 1

M9 50/1.2, m = 4

M10 150/1.2, m = 4

M11 12/2.4, m = 1

M12, M13 12/0.6, m = 1

0 10 20 30 40 50

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

Time (ms)

1.21V VPG

0V

0V

1.21V VOUT

VLINE

Fig. 17 Simulated power up and power down response of LDO of

Fig. 14, showing the Power Good signal VPG

Analog Integr Circ Sig Process

123

Corporation, Hillsboro, OR, and Sheetal Liddar and Stewe Kwan of Texas

Instruments Inc., Dallas, TX for their support and helpful comments.

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Annajirao Garimella received

the B.E. degree in electrical and

electronics engineering from the

University of Madras, Chennai,

India, in 2000, the M.S. degree

in VLSI from Manipal Univer-

sity, Manipal, India, in 2002,

and the M.S. and Ph.D. degrees

in electrical engineering with a

minor in management from

New Mexico State University,

Las Cruces, NM in 2009 and

2010, respectively. In 2006, he

worked as an intern at Freescale

Semiconductor, Inc., Austin,

TX. In 2007, he held a co-op position at Texas Instruments, Dallas,

TX. He has authored or coauthored more than 30 papers, published in

conferences and journals. His research interests lie in the area of

Circuits and Systems, with emphasis on analog, mixed-signal IC

design, power management IC design, SoC design, and testing. He is

recipient of HENAAC (Hispanic Engineer National Achievement

Award Corporation) AMD Scholarship in 2005 and the HENAAC

DaimlerChrysler Scholarship in 2006. Dr. Garimella received the

Outstanding Ph.D. Graduate Award at New Mexico State University

for Fall 2010. He is on the organizing committee of the 25th Inter-

national Conference on VLSI Design VLSID’ 2012 and also the

publication co-chair. He is a member of IEEE.

Analog Integr Circ Sig Process

123

Paul M. Furth received a B.A.

from Grinnell College, Grinnell,

IA in 1984, the B.S.E.E. degree

from the California Institute of

Technology, Pasadena, CA in

1985 and the M.S. and Ph.D.

degrees in electrical engineering

from the Johns Hopkins Uni-

versity, Baltimore, MD, in 1992

and 1996, respectively. In 1995,

he joined the Klipsch School of

Electrical and Computer Engi-

neering, New Mexico State

University, Las Cruces, where

he is currently an Associate

Professor. He has work experience at Sandia National Labs, Micron,

and Motorola. His areas of interest include analog and mixed-signal

VLSI design, power management circuits, and CMOS image sensors.

Dr. Furth received the Bromilow Teaching Excellence Award in

2008. He was the Technical Program Chair at the 42nd IEEE Midwest

Symposium on Circuits and Systems Conference, MWSCAS 1999.

He has chaired Special Sessions at MWSCAS 2010 and MWSCAS

2011 and currently serves as a Steering Committee Member for

MWSCAS. He is a Senior Member of IEEE.

Punith R. Surkanti is a Ph.D.

candidate in electrical engi-

neering at New Mexico State

University, Las Cruces, NM. He

obtained his B.Tech. from

JNTU, Hyderabad in 2008 and

M.S. degree in electrical engi-

neering from New Mexico State

University, Las Cruces, NM in

2011. He is the recipient of the

Outstanding Graduate Teaching

Assistantship Award from

NMSU in 2011. He was selected

for the Preparing Future Faculty

Graduate Assistantship Award

at NMSU in Fall 2009. His areas of interest include Analog, Mixed-

signal and Power Management IC Design. He is a Student Member of

IEEE.

Nitya R. Thota received the

B.Tech. degree in electronics

and communications engineer-

ing from the Jawaharlal Nehru

Technological University,

Hyderabad, AP, India, in 2009.

She is currently working

towards the M.S. degree in

electrical engineering at New

Mexico State University, Las

Cruces. She was selected for the

Preparing Future Faculty Grad-

uate Assistantship Award at

New Mexico State University

for the 2010–2011 academic

year. Her areas of interest include analog, mixed-signal VLSI design,

power management IC design and ASIC design.

Analog Integr Circ Sig Process

123