Current ASIC Design Flow

Current ASIC Design flow The modern ASIC design flow has evolved and increased in complexity just as the devices that are being designed have dramatically increased in complexity. This design flow is now heavily dependent on EDA tools and many of the tasks that were once carried out manually are now automated by EDA tools with little or no manual intervention. As a function of this increase in complexity it has been necessary for designers and verification engineers to seek out higher levels of abstraction to carry out their respective tasks. This abstraction of the design process means that designers develop their designs in hardware description languages such as Verilog and VHDL. These languages not only al low designers to describe logic gates; they can also specify abstract types, such as the states of a state machine, and complex operations , such as multiply, in a single line of HDL code. So powerful are these hardware description languages that two levels of abstraction in the design flow are now possible; namely, RTL (Register Transfer Level) and Behavioral level. The design flow including these two levels of abstraction is shown in Figure 4-1. Figure 4-1 As with all design projects the flow starts with a specification. Currently there is no universally accepted way of capturing a specification. Usually it is a complex written document that immediately runs the risk of containing ambiguities. It is for this reason that many large design companies employ two teams - a design team and verification team both working from the same specification. The idea here is that any ambiguities are trapped using this two- pronged attack. From the specification a behavioral description of the design is generated. Currently this process has to be done manually. Normally the behavioral description is captured in a hardware description language such as VHDL or Verilog or even C++. Once the behavioral description has been captured the designer has a formal unambiguous circuit description that can be executed and therefore tested against the specification. This is an important stage in the process because already at this early stage the design can be tested for misconceptions. Bringing in verification as early as possible is critical in the modern design process becau se the process is so long sometimes months or even years and discovering a major conceptual error late in the design process would result in significant time and cost over-runs. Whether using VHDL or Verilog - or a combination of both languages, verification is usually carried out using one of the many commercially available HDL simulators. The design is tested by applying a number of stimuli, test vectors or test benches - usually written in the same language as the design - and checking the resulting responses. This may be done either manually or automatically if the simulator allows it and if the expected responses are included in what is then known as a self-checking test bench. Having verified the behavioral design the next step in the process is to decompose this to an RTL description. While RTL is still a level of abstraction above gate level, the design blocks, combinational logic and registers can be clearly identified. In fact 80% of a design''s structur e is typically fixed at the RTL stage. Transforming a design from a behavioral description into

Current ASIC Design Flow

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