Cumulative Design Review: Interactive Teaching Device April 8 th , 2005

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Cumulative Design Cumulative Design Review: Review: Interactive Teaching Interactive Teaching Device Device April 8 April 8 th th , 2005 , 2005 Lance Haney Lance Haney Micah Nance Micah Nance Nathan Young Nathan Young

description

Cumulative Design Review: Interactive Teaching Device April 8 th , 2005. Lance Haney Micah Nance Nathan Young. Important Persons. Client Dr. Aaron Collins Technical Advisor Dr. John Reece Project Manager Dr. Phillip Olivier. Overview. PDR Review Delivered Design Hardware Software - PowerPoint PPT Presentation

Transcript of Cumulative Design Review: Interactive Teaching Device April 8 th , 2005

Page 1: Cumulative Design Review: Interactive Teaching Device  April 8 th , 2005

Cumulative Design Review:Cumulative Design Review:Interactive Teaching DeviceInteractive Teaching Device

April 8 April 8thth, 2005, 2005

Lance HaneyLance HaneyMicah NanceMicah NanceNathan YoungNathan Young

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Important PersonsImportant Persons

ClientClient– Dr. Aaron CollinsDr. Aaron Collins

Technical AdvisorTechnical Advisor– Dr. John ReeceDr. John Reece

Project ManagerProject Manager– Dr. Phillip OlivierDr. Phillip Olivier

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OverviewOverview

PDR ReviewPDR ReviewDelivered DesignDelivered Design– HardwareHardware– SoftwareSoftware

DemonstrationDemonstrationBudgetBudgetConclusionConclusionRecommendationsRecommendations

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Client RequirementsClient Requirements

Update ECE 424 and ECE 426Update ECE 424 and ECE 426

Use state of the art technologyUse state of the art technology

Prepare for new industry trendsPrepare for new industry trends

Deliver teaching deviceDeliver teaching device

Deliver lab manualDeliver lab manual

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Feasibility CriteriaFeasibility Criteria

Low budget ($300 maximum)Low budget ($300 maximum)

Compatible with Win98 or WinXPCompatible with Win98 or WinXP

Applicable to ECE 424 and ECE 426Applicable to ECE 424 and ECE 426

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PDR Design AlternativesPDR Design Alternatives

SOPC with RTOSSOPC with RTOS

SOPC without RTOSSOPC without RTOS

Microcontroller with RTOSMicrocontroller with RTOS

Microcontroller without RTOSMicrocontroller without RTOS

VHDLVHDL

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Design Selected - PDR PhaseDesign Selected - PDR Phase

Selected SOPC with RTOS DesignSelected SOPC with RTOS Design

NIOS II Evaluation EditionNIOS II Evaluation Edition– MicroC/OS-II feature disabledMicroC/OS-II feature disabled

Design ChangeDesign Change– SOPC without RTOSSOPC without RTOS

Design AdditionDesign Addition– Implemented VHDL DesignImplemented VHDL Design

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Why SOPC?Why SOPC?

One chipOne chip– Simplified designSimplified design– Less hardwareLess hardware

Supports VHDL & current curriculumSupports VHDL & current curriculum

Nios II Soft-core ProcessorNios II Soft-core Processor– C/C++C/C++– AssemblyAssembly

Expedite upgradesExpedite upgrades

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Delivered DesignDelivered Design

VHDL ImplementationVHDL Implementation

SOPC with Nios IISOPC with Nios II

UP3 Development BoardUP3 Development Board

External Hardware AssemblyExternal Hardware Assembly

Lab ManualLab Manual

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UP3 Development BoardUP3 Development Board

Cyclone FPGA

External RAM

On BoardPushbuttons

On BoardLEDs LCD Display

Expansion Headers

Parallel Port

Serial Port

USB Port

VGA Port RAM-11.25 KB on-chip-128 KB external

48 MHz clock

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External Hardware AssemblyExternal Hardware Assembly

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Delivered SystemDelivered System

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VHDL VHDL – Efficient use of logic elementsEfficient use of logic elements– 1% Logic Elements Used1% Logic Elements Used

Nios II Soft-core Processor with C codeNios II Soft-core Processor with C code– Embedded Processor Embedded Processor – High Level Language High Level Language – 33% Logic Elements Used33% Logic Elements Used– 49% Total On-chip Memory Used49% Total On-chip Memory Used

System Implementation System Implementation AlternativesAlternatives

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VHDL DesignVHDL Design

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C Code Software DesignC Code Software Design

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Nios II ConfigurationsNios II Configurations

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Nios II Debugging OptionsNios II Debugging Options

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System DemonstrationSystem Demonstration

VHDL DesignVHDL Design

Nios II Soft-core Processor with C Code Nios II Soft-core Processor with C Code DesignDesign

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BudgetBudget

Prototype CostPrototype CostPart Quantity Price per unit Subtotal

UP3 Development Board 1 $0.00 $0.00

Altera Software 1 $0.00 $0.00

IDE Cable 1 $5.00 $5.00

LEDs (1.8V@20mA) 30 $0.20 $6.00

Resistors (150 Ohm) 30 $0.20 $6.00

Resistors (10k Ohm) 30 $0.20 $6.00

Mushroom Pushbutton Switch 2 $18.01 $36.02

Jumper Wires 1 $11.25 $11.25

Breadboard 1 $8.78 $8.78

Mount - Wooden Box 1 $8.00 $8.00

Tax (7%) $6.09

Total $93.14

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Part Allied Electronics # Quantity Price per unit Subtotal

UP3 Board   12 $249.00 $2,988.00

IDE Cable   12 $5.00 $60.00

LEDs (1.8V@20mA) 431-0152 120 $0.15 $18.00

Resistors (150 Ohm) 296-5952 120 $0.35 $42.00

Resistors (10k Ohm) 296-6526 60 $0.25 $15.00

Mushroom Pushbutton Switch 814-0022 24 $18.01 $432.24

Jumper Wires (75 count) 618-3464 12 $10.00 $120.00

Breadboard 761-0010 12 $19.50 $234.00

Tax (7%) $273.65

Total $4,182.89

BudgetBudget

Lab ImplementationLab Implementation

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ConclusionConclusion

Utilize Altera UP3 Development BoardUtilize Altera UP3 Development Board– Low costLow cost– VersatileVersatile– ExpandableExpandable– InnovativeInnovative

Altera Software PackageAltera Software Package– Reasonable learning curveReasonable learning curve– User friendlyUser friendly– VersatileVersatile

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RecommendationsRecommendations

12 Workstations12 Workstations– Altera UP3 Development BoardAltera UP3 Development Board– External HardwareExternal Hardware– Windows XPWindows XP

Integration into ECE 424/426 curriculumIntegration into ECE 424/426 curriculum

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SummarySummary

PDR ReviewPDR Review

Delivered DesignDelivered Design

DemonstrationDemonstration

BudgetBudget

ConclusionConclusion

RecommendationsRecommendations

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Questions?Questions?