CSPLAT for Photolithography Simulationcadlab.cs.ucla.edu/.../CSPLAT_Guongxi.pdfSimulation Tool-----...

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CSPLAT for Photolithography Simulation Guoxiong Wang [email protected] Institute of VLSI Design, Zhejiang University 2001.8.31

Transcript of CSPLAT for Photolithography Simulationcadlab.cs.ucla.edu/.../CSPLAT_Guongxi.pdfSimulation Tool-----...

Page 1: CSPLAT for Photolithography Simulationcadlab.cs.ucla.edu/.../CSPLAT_Guongxi.pdfSimulation Tool----- SPLAT A lithography simulation tool developed in UC Berkeley. Based on the Hopkins

CSPLAT for Photolithography Simulation

Guoxiong [email protected]

Institute of VLSI Design, Zhejiang University2001.8.31

Page 2: CSPLAT for Photolithography Simulationcadlab.cs.ucla.edu/.../CSPLAT_Guongxi.pdfSimulation Tool----- SPLAT A lithography simulation tool developed in UC Berkeley. Based on the Hopkins

Outline

Photolithographic systemResolution enhancement technologiesPhotomask techniques

Optical proximity correctionPhase-shifting mask

Traditional simulation methodSimulation Tool –SPLAT and CSPLATSome examples

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Optical part of photolithographic system

Figure 1 Schematic of a typical stepper

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Schematic of the optical part

Figure 2 Approximation of a projection exposure system

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NAkCD λ

1=

Feature size limit in photolithography processes

Where CD is Critical Dimension,(also refers to the resolution, i.e.,the minimal printable feature size). lambda is wavelength, NA is Numerical Aperture, k1 is a characteristic constant of the specific lithography process. this formula states the CD limit of a certain litho-process.

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Roadmap of illumination source wavelength reduction

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The physical limit of NA is 1.0,maximum for feasible NA is about 0.75 to 0.85.k1 represents lithography aggressiveness (0.75 to 0.35, 0.25 as the theoretical lower limit)

Modified illuminationAnnular illuminationQuadrupole illumination

Photomask techniquesOptical proximity correctionPhase-shifting masks

Pupil filteringMultiple exposuresAntireflective layerTop surface imaging

Photolithography technologies

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Optical proximity correctionIntentionally and systematically distort the mask in such a way as to compensate for optical diffraction limit and process non-idealities.

Enables smaller features with closer proximities to be printed on the same area.Increases the process latitude, decreases the variations of linewidth across a chip and could potentially enhance yield;

�Applicability of combination of OPC and PSM leads to better resolution when the minimum feature dimensions and spacing decrease below the wavelength of the light source.

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Types of Optical Proximity Correction

�Model-based OPC

– use process simulation to determine corrections on-line

– longer design time,increased mask complexity

– suitable for aggressive designs

�Rule-based OPC– apply corrections based on a

set of predetermined rules

– fast design time,lower mask complexity

– suitable for less aggressive designs

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Phase-shifting Masks

(a)Light diffracted by two adjacent apertures constructively interferes, increasing the light intensity in the dark area of the wafer between the apertures.

(b)with the (alternating)phase-shifting mask,the phase shifter reverses the sign of the electric field, and destructive interference minimizes light intensity at the wafer in the dark area between apertures.

Note: E denotes electric field and I denotes intensity

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Types of phase-shifting masks

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Traditional simulation method

Aerial image simulationHopkins partial coherence model

Photoresist exposure/bleaching simulationDill’s exposure model

Photoresist bake/development SimulationPlasma etching and diffusion simulation for different layers.

Page 13: CSPLAT for Photolithography Simulationcadlab.cs.ucla.edu/.../CSPLAT_Guongxi.pdfSimulation Tool----- SPLAT A lithography simulation tool developed in UC Berkeley. Based on the Hopkins

Simulation Tool------ SPLATA lithography simulation tool developed in UC Berkeley.Based on the Hopkins Equation for partially coherent imaging.Use the method of two dimension Fourier transform.Calculates sampling intensities on a line or a rectangular area.Unsuitable to deal with sparse aerial point simulation.

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SPLAT Simulation Flow

Opticalparameters TCC

Maskprofile

Outputimage

intensity

Hopkins equation

The Fourier transform of

intensityFouriertransform

Fourier inverse transform

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New Simulation Tool -----CSPLAT

Written in C, using similar syntax as in SPLAT.Fast sparse aerial points intensity simulation.

Hopkins Equation (Bi-linear )Decomposition of convolution kernelsIntensity lookup table for geometrical primitives.

Post-imaging model.Variable intensity threshold (line width)Gaussian filters set (line end and corner rounding)

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New Simulation Tool -----CSPLATModel training from wafer measurement

Test patternsIsolated line line-widthIsolated line-end spacePitch structure

Regression methodDefinitive searchingNeural network trainingThe goal of model calibration is to capture the CD variations caused by the the process distortions. The more information we have about these sub-processes and the more complex models we use for the simulations,the more accurate the simulation results we should obtain.

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Convolution kernels

Model –based correction is calculated based on predefined kernel functions and the mask patternsA convolution value at any specific point (x,y) is found by:

Centering a “convolution kernel” function over the point (x,y)Multiplying the pattern and the “convolution kernel”Summing the total volume

The shape of a convolution kernel ultimately determines the behavior of a model

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Convolution kernels

1) a partially coherent imaging system with a superposition of coherent imaging system.

2)Reduce to “principal waves”

3)The first few principal wave could meet the accuracy

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CSPLAT Simulation Flow

Opticalparameters

TCC

tables

Set of kernels

Mask profile

Simulatedcontours

Hopkins equation

decomposition

Table calculation

Post-imagingmodel

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Post-imaging model training

Test pattern

Optical simulator

Print onwafer

Aerial image

measurement

VariableThreshold

model

Model param

eters

extraction

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Comparison

a b

c

(a) The error between SPLAT and CSPLAT

(b) The calculation result through SPLAT

(c) The calculation result through CSPLAT

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Layout of a real chip

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A partial layout geometries

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The simulation result of using CSPLAT

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Comparison of layout geometries and simulation result

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Thank You