CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 5: Arithmetic Circuits...

CS/EE 3700 : Fundamentals of Digital System Design

Chris J. Myers

Lecture 5: Arithmetic Circuits

Chapter 5 (minus 5.3.4)

Positional Number Representation

• Decimal:– D = dn-1dn-2...d1d0

– V(D) = dn-1 10n-1 + d n-2 10n-2 + ... + d1 101 + d0 100

• Binary:– B = bn-1bn-2...b1b0

– V(B) = bn-1 2n-1 + b n-2 2n-2 + ... + b1 21 + b0 20 (5.1)

Conversion: Binary to/from Decimal

• Conversion of binary to decimal: use 5.1.– (1101)2 =

• Conversion of decimal to binary:– V = bn-1 2n-1 + b n-2 2n-2 + ... + b1 21 + b0

– V/2 = bn-1 2n-2 + b n-2 2n-3 + ... + b1 + b0/2– Quotient is: bn-1 2n-2 + b n-2 2n-3 + ... + b1 – Remainder is: b0

– If remainder is 0 then b0 = 0, if it is 1 then b0 = 1.– Repeat on quotient to find b1, etc.

Figure 5.1 Conversion from decimal to binary

Convert (857)10 to binary:

Table 5.1 Numbers in different systems

Conversion: Binary to Oct or Hex

• (101011010111)2

• (10111011)2

• (1010111100100101)2

• (1101101000)2

Addition of Unsigned Numbers

x

+ y

----

c s sum

carry

Addition of Unsigned Numbersx y c s

Figure 5.3 An example of addition

(15)10

(10)10

Figure 5.4 Full-adder

Use of XOR Gates

Circuit for Full Adder

Figure 5.5 A decomposed implementation of the full-adder circuit

HA

HAs

c

s

c c i x i y i

c i 1 +

s i

c i

x i y i

c i 1 +

s i

(a) Block diagram

(b) Detailed diagram

Figure 5.6 An n-bit ripple-carry adder

FA

x n – 1

c n c n 1 ”

y n 1 –

s n 1 –

FA

x 1

c 2

y 1

s 1

FAc 1

x 0 y 0

s 0

c 0

MSB position LSB position

7 x 0 y 7 y 0

x 7 x 0 y 8 y 0 y 7 x 8

s 0 s 7

c 7

0

s 0 s 8 c 8

P 9 P 8 P 0 P 3 A = :

(a) Naive approach

a 7 A : a 0

x

Figure5.7 Circuit that multiplies an 8-bit unsigned number by 3

Figure5.7 Circuit that multiplies an 8-bit unsigned number by 3

x 1 x 0 y 8 y 0 y 7 x 8

s 0 s 8 c 8

0 0

a 7 A :

P 9 P 8 P 0 P 3 A = :

(b) Efficient design

a 0

bn 1– b1 b0

MagnitudeMSB

(a) Unsigned number

bn 1– b1 b0

MagnitudeSign

(b) Signed number

bn 2–

0 denotes1 denotes

+– MSB

Sign Magnitude

• Magnitude of positive and negative numbers represented in same way.

• Sign used to distinguish them.

• Simple to understand.

• Complicates hardware design.

1’s Complement

• n-bit negative number found by subtracting its positive form from 2n-1.– K1 = (2n – 1) – P

• Found by just complementing each bit.

• Examples:

2’s Complement

• n-bit negative number found by subtracting its positive form from 2n.– K2 = 2n – P

– K2 = K1 + 1

• Complement each bit and add 1.

• Examples:

Sign Magnitude: Add/Sub

• If both operands have the same sign, then addition is simple.– Add magnitudes and copy the sign.

• If they have opposite sign, then must subtract smaller from the larger.

• This is complicated, so sign magnitude not typically used in computers.

Figure 5.9 Examples of 1’s complement addition

2+( )5–

3- +

5–

7– + 2–

5+( )2+( )

7+( )

+

5+( )

3+( )

+ 2–

Figure 5.10 Examples of 2’s complement addition

2+( )5–

3- +

5–

7– + 2–

5+( )2+( )

7+( )

+

5+( )

3+( )

+ 2–

Figure 5.11 Examples of 2’s complement subtraction

5+( )2+( )

7+( )

–

5+( )

3+( )

– 2–

Figure 5.11 Examples of 2’s complement subtraction

2+( )5–

3- –

5–

7– – 2–

Figure 5.12 Graphical interpretation of four-bit 2’s complement numbers

00000001

0010

0011

0100

0101

0110

01111000

1001

1010

1011

1100

1101

1110

1111

1 + 1 – 2 +

3 +

4 +

5 +

6 + 7 +

2 – 3 –

4 –

5 –

6 – 7 – 8 –

0

Figure 5.13 Adder/subtractor unit

s 0 s 1 s n 1 –

x 0 x 1 x n 1 –

c n n -bit adder

y 0 y 1 y n 1 –

c 0

Add Sub control

Figure 5.14 Examples of determination of overflow

7+( )2+( )

9+( )

+

7+( )

5+( )

+ 2–

2+( )7–

5–

+

7–

9–

+ 2–

Detecting Overflow

• Overflow = c3c4’ + c3’c4

= c3 c4

• For n-bit numbers,• Overflow = cn-1 cn

Performance Issues

• Price/performance ratio is important.• Speed of addition/subtraction has impact on

overall speed of a microprocessor.• Worst-case delay of a ripple carry adder is:

– n t– Assume t = 2 gate delays and xor = 1.– Total delay = 2n + 1 gate delays.

• Must reduce critical path delay.

Carry-Lookahead Adder

• Must determine carry quickly.– ci+1 = xiyi + xici + yici

– ci+1 = xiyi + (xi + yi)ci

– ci+1 = gi+ pici where gi = xiyi (generate)

pi = xi + yi (propagate)– ci+1 = gi+ pi (gi-1+ pi-1ci-1)– ci+1 = gi+ pigi-1+ pipi-1ci-1

– ci+1 = gi+ pigi-1+ pipi-1gi-2 + ...+ pipi-1...p1g0 +

pipi-1...p0c0

x 1 y 1

g 1 p 1

s 1

Stage 1

x 0 y 0

g 0 p 0

s 0

Stage 0

c 0 c 1

c 2

Figure 5.15 A ripple-carry adder with generate/propagate signals

Figure 5.16 The first two stages of a carry-lookahead adder

x 1 y 1

g 1 p 1

s 1

x 0 y 0

s 0

c 2

x 0 y 0

c 0

c 1

g 0 p 0

High Fan-in Issues

• c1 = g0+ p0c0

• c2 = g1+ p1g0+ p1p0c0

• ...

• c8 = g7+ p7g6+ p7p6g5 + p7p6p5g4 + p7p6p5p4g3

+ p7p6p5p4p3g2 + p7p6p5p4p3p2g1

+ p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0

• c8 = (g7+ p7g6+ p7p6g5 + p7p6p5g4) + [(p7p6p5p4)(g3 +

p3g2 + p3p2g1 + p3p2p1g0) + (p7p6p5p4)(p3p2p1p0)c0

Figure 5.17 A hierarchical carry-lookahead adder with ripple-carry between blocks

Block

x3124–

c32 c24

y3124–

s3124–

x158–

c16

y158–

s158–

c8

x7 0– y7 0–

s7 0–

c03Block

1Block

0

Group Propagate/Generate

• c8 = g7+ p7g6+ p7p6g5 + p7p6p5g4 + p7p6p5p4g3

+ p7p6p5p4p3g2 + p7p6p5p4p3p2g1

+ p7p6p5p4p3p2p1g0 + p7p6p5p4p3p2p1p0c0

• P0 = p7p6p5p4p3p2p1p0

• G0 = g7+ p7g6+ ... + p7p6p5p4p3p2p1g0

• c8 = G0 + P0c0

• c16 = G1 + P1G0 + P1P0c0

• c24 = G2 + P2G1 + P2P1G0 + P2P1P0c0

• c32 = G3 + P3G2 + P3P2G1 + P3P2P1G0 + P3P2P1P0c0

Figure 5.18 A hierarchical carry-lookahead adder

Block

x 15 8 – y 15 8 – x 7 0 – y 7 0 –

3 Block

1 Block

0

Second-level lookahead

c 0

s 7 0 –

P 0 G 0 P 1 G 1 P 3 G 3

s 15 8 – s 31 24–

c 8 c 16c 32

x 31 24– y 31 24–

c 24

Figure 5.19 An alternative design for a carry-lookahead adder

x 1 y 1

g 1 p 1

s 1 s 0

c 2

x 0 y 0

c 0

c 1

g 0 p 0

Figure 5.20 Schematic using an LPM adder/subtractor module

Figure 5.21 Simulation results for the LPM adder

Optimized for cost

Optimized for speed

Figure 5.23 VHDL code for the full-adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;

ENTITY fulladd ISPORT ( Cin, x, y : IN STD_LOGIC ;

s, Cout : OUT STD_LOGIC ) ;END fulladd ;

ARCHITECTURE LogicFunc OF fulladd ISBEGIN

s <= x XOR y XOR Cin ;Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;

END LogicFunc ;

Figure 5.24 VHDL code for a four-bit adder


ENTITY adder4 ISPORT ( Cin : IN STD_LOGIC ;

x3, x2, x1, x0 : IN STD_LOGIC ;y3, y2, y1, y0 : IN STD_LOGIC ;s3, s2, s1, s0 : OUT STD_LOGIC ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL c1, c2, c3 : STD_LOGIC ;COMPONENT fulladd

PORT ( Cin, x, y : IN STD_LOGIC ;s, Cout : OUT STD_LOGIC ) ;

END COMPONENT ;BEGIN

stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;stage3: fulladd PORT MAP (

Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;END Structure ;

Figure 5.25 Declaration of a package


PACKAGE fulladd_package ISCOMPONENT fulladd

PORT ( Cin, x, y : IN STD_LOGIC ;s, Cout : OUT STD_LOGIC ) ;

END COMPONENT ;END fulladd_package ;

Figure 5.26 Using a package for the four-bit adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;


x3, x2, x1, x0 : IN STD_LOGIC ;y3, y2, y1, y0 : IN STD_LOGIC ;s3, s2, s1, s0 : OUT STD_LOGIC ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL c1, c2, c3 : STD_LOGIC ;

BEGINstage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;stage3: fulladd PORT MAP (

Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;END Structure ;

STD_LOGIC_VECTOR’s

• SIGNAL C : STD_LOGIC_VECTOR(1 TO 3);

• C <= “100” equivalent to:

– C(1) = ‘1’, C(2) = ‘0’, C(3) = ‘0’

• SIGNAL X : STD_LOGIC_VECTOR(3 DOWNTO 0);

• X <= “1100” equivalent to:

– X(3) = ‘1’, X(2) = ‘1’, X(1) = ‘0’, X(0) = ‘0’

Figure 5.27 A four-bit adder defined using multibit signals

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE work.fulladd_package.all ;


X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(3 DOWNTO 0) ;Cout : OUT STD_LOGIC ) ;

END adder4 ;

ARCHITECTURE Structure OF adder4 ISSIGNAL C : STD_LOGIC_VECTOR(1 TO 3) ;

BEGINstage0: fulladd PORT MAP ( Cin, X(0), Y(0), S(0), C(1) ) ;stage1: fulladd PORT MAP ( C(1), X(1), Y(1), S(1), C(2) ) ;stage2: fulladd PORT MAP ( C(2), X(2), Y(2), S(2), C(3) ) ;stage3: fulladd PORT MAP ( C(3), X(3), Y(3), S(3), Cout ) ;

END Structure ;

Arithmetic Packages

• std_logic_signed package defines signed arithmetic for std_logic type.

• std_logic_unsigned package defines unsigned arithmetic for std_logic type.

• These are built on top of the package std_logic_arith.

Figure 5.28 VHDL code for a 16-bit adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;

ENTITY adder16 ISPORT ( X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;

S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ) ;END adder16 ;

ARCHITECTURE Behavior OF adder16 IS BEGIN

S <= X + Y ;END Behavior ;

Figure 5.29 A 16-bit adder with carry and overflow

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_signed.all ;


X, Y : IN STD_LOGIC_VECTOR(15 DOWNTO 0) ;S : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : STD_LOGIC_VECTOR(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

END Behavior ;

Figure 5.30 Use of the arithmetic package

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_arith.all ;


X, Y : IN SIGNED(15 DOWNTO 0) ;S : OUT SIGNED(15 DOWNTO 0) ;Cout, Overflow : OUT STD_LOGIC ) ;

END adder16 ;

ARCHITECTURE Behavior OF adder16 IS SIGNAL Sum : SIGNED(16 DOWNTO 0) ;

BEGINSum <= ('0' & X) + Y + Cin ;S <= Sum(15 DOWNTO 0) ;Cout <= Sum(16) ;Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;

END Behavior ;

Figure 5.31 A 16-bit adder using INTEGER signals

ENTITY adder16 ISPORT ( X, Y : IN INTEGER RANGE -32768 TO 32767 ;

S : OUT INTEGER RANGE -32768 TO 32767 ) ;END adder16 ;

ARCHITECTURE Behavior OF adder16 IS BEGIN

S <= X + Y ;END Behavior ;

Multiplication

• Binary number can be multiplied by 2 shifting it one position to the left:– B = bn-1 bn-2 ... b1b0

– 2 B = bn-1 bn-2 ... b1b00

• Similarly, multiplying by 2k can be done by shifting left by k bit positions.

• Right shifts divide by powers of 2.

Figure 5.32 Multiplication of unsigned numbers

1 1 1 01 0 1 1

Multiplicand MMultiplier Q

(14)(11)

(a) Multiplication by hand

1 1 1 01 0 1 1


Product P

(11)(14)

Partial product 0

Partial product 1

Partial product 2

(b) Multiplication for implementation in hardware

Array Multiplier

• M = m3m2m1m0 and Q = q3q2q1q0

• Partial product 0:– PP0 = m3q0 m2q0 m1q0 m0q0

• Partial product 1:PP0: 0 pp03 pp02 pp01 pp00

+ m3q1 m2q1 m1q1 m0q0 0---------------------------------------------------------

PP1: pp14 pp13 pp12 pp11 pp10

Figure 5.33 A 4 x 4 multiplier circuit

0

0

0

p 7 p 6 p 5 p 4 p 3 p 2 p 1 p 0

q 2

q 1

q 3

q 0

m 3 m 2 m 1 m 0 0

PP1

PP2

(a) Structure of the circuit

m k

q j

c in

Bit of PPi

FAc out

(c) A block in the bottom two rows

m k

q 1

c inFAc out

(b) A block in the top row

q 0

m k 1 +

0 1 1 1 0 0 1 0 1 1


Product P

(+14) (+11)

(+154)

Partial product 0

Partial product 1

Partial product 2

Partial product 3

(a) Positive multiplicand

x

1 0 0 1 0 0 1 0 1 1


Product P

(–14) (+11)

(–154)

Partial product 0

Partial product 1

Partial product 2

Partial product 3

(a) Negative multiplicand

x

Fixed-Point Numbers

• A fixed-point number consists of an integer and fraction part.– B = bn-1bn-2...b1b0 . b-1b-2...b-k

– V(B) =

• The position of the radix point is fixed.

• Circuits for fixed point same as integer.

Floating-Point Numbers

• Fixed-point numbers range limited by the number of significant digits.

• Floating-point numbers needed to represent very large or very small numbers.– Mantissa RExponent

• Numbers are normalized such that radix point placed to right of first nonzero digit.

Figure 5.35 IEEE standard floating-point formats

Sign

32 bits

23 bits of mantissa excess-127exponent

8-bit

52 bits of mantissa 11-bit excess-1023exponent

64 bits

Sign

S M

S M

(a) Single precision

(c) Double precision

E

+

E

0 denotes – 1 denotes

Table 5.3 Binary-coded decimal digits

Figure 5.36 Addition of BCD digits

+

1 1 0 0

0 1 1 10 1 0 1+

XY

Z

+75

120 1 1 0+

1 0 0 1 0carry

+

1 0 0 0 1

1 0 0 01 0 0 1+

XY

Z

+89

170 1 1 0+

1 0 1 1 1carry

S = 2

S = 7

BCD Addition

• Z = X + Y

• If Z <= 9 then S = Z and carry-out = 0

• If Z > 9 then S = Z + 6 and carry-out = 1

Figure 5.37 Block diagram for a one-digit BCD adder

4-bit adder

Detect if

MUX

4-bit adder

sum 9 >

6 0

X Y

Z

c out

c incarry-out

Adjust

S

0

Figure 5.38 VHDL code for a one-digit BCD adder

LIBRARY ieee ;USE ieee.std_logic_1164.all ;USE ieee.std_logic_unsigned.all ;

ENTITY BCD ISPORT ( X, Y : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;

S : OUT STD_LOGIC_VECTOR(4 DOWNTO 0) ) ;END BCD ;

ARCHITECTURE Behavior OF BCD ISSIGNAL Z : STD_LOGIC_VECTOR(4 DOWNTO 0) ;SIGNAL Adjust : STD_LOGIC ;

BEGINZ <= ('0' & X) + Y ;Adjust <= '1' WHEN Z > 9 ELSE '0' ;S <= Z WHEN (Adjust = '0') ELSE Z + 6 ;

END Behavior ;

Figure 5.39 Functional simulation of the one-digit BCD adder

Figure 5.40 Circuit for a one-digit BCD adder

c out

Four-bit adder

Two-bit adder

s 3 s 2 s 1 s 0

z 3 z 2 z 1 z 0

x 3 x 2 x 1 x 0 y 3 y 2 y 1 y 0

c in

Table 5.4 The seven-bit ASCII code

Parity

• Parity widely used for error-checking.• Data transmitted over long wires may be corrupted

during transit.• Extra parity bit p is added to detect an error.• Even parity: p set to make number of 1’s even.

– p = x3 x2 x1 x0

– c = p x3 x2 x1 x0

• Odd parity: p set to make number of 1’s odd.

Summary

• Positional number representation.

• Addition of unsigned/signed numbers.

• Carry-Lookahead adder.

• Arithmetic circuit design using VHDL.

• Multiplication.

• Other number representations.

CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 5: Arithmetic Circuits...

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