CS/EE 3700 : Fundamentals of Digital System Design

Chris J. Myers

Lecture 4: Logic Optimization

Chapter 4

Motivation

• Algebraic manipulation is not systematic.

• This chapter presents methods that can be automated in CAD tools.

• Although tools used for logic optimization, designers must understand the process.

Figure 4.1 The function f = m(0, 2, 4, 5, 6)

x 2

(a) Truth table (b) Karnaugh map

0

1

0 1

m 0 m 2

m 3 m 1

x 1 x 2

0 0

0 1

1 0

1 1

m 0 m 1

m 3

m 2

x 1

Figure 4.2 Location of two-variable minterms

Figure 2.15 A function to be synthesized

Figure 4.4 Location of three-variable minterms

x 1 x 2 x 3 00 01 11 10

0

1

(b) Karnaugh map

x 2 x 3 0 0

0 1

1 0

1 1

m 0 m 1

m 3

m 2

0

0

0

0

0 0

0 1

1 0

1 1

1

1

1

1

m 4 m 5

m 7

m 6

x 1

(a) Truth table

m 0

m 1 m 3

m 2 m 6

m 7

m 4

m 5

Figure 4.6 A four-variable Karnaugh map

x 1 x 2 x 3 x 4 00 01 11 10

00

01

11

10

x 2

x 4

x 1

x 3

m 0

m 1 m 5

m 4 m 12

m 13

m 8

m 9

m 3

m 2 m 6

m 7 m 15

m 14

m 11

m 10

x 1 x 2 x 3 x 4

0

00 01 11 10

0 0 0

0 0 1 1

1 0 0 1

1 0 0 1

00

01

11

10

x 1 x 2 x 3 x 4

0

00 01 11 10

0 0 0

0 0 1 1

1 1 1 1

1 1 1 1

00

01

11

10

x 1 x 2 x 3 x 4

1

00 01 11 10

0 0 1

0 0 0 0

1 1 1 0

1 1 0 1

00

01

11

10

x 1 x 2 x 3 x 4

1

00 01 11 10

1 1 0

1 1 1 0

0 0 1 1

0 0 1 1

00

01

11

10

Figure 4.8 A five-variable Karnaugh map

x 1 x 2 x 3 x 4 00 01 11 10

1

1 1

1 1

1 1

00

01

11

10

x 5 1 =

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1 1

1 1

00

01

11

10

x 5 0 =

Terminology

• A variable either uncomplemented our complemented is called a literal.

• A product term that indicates when a function is equal to 1 is called an implicant.

• An implicant that cannot have any literal deleted and still be a valid implicant is called a prime implicant.

Figure 4.9 Three-variable function f = m(0, 1, 2, 3, 7)

x 1 x 2 x 3

1 1

1 1

0 0

1 0

00 01 11 10

0

1

Terminology (cont)

• A collection of implicants that accounts for all input combinations in which a function evaluates to 1 is called a cover.

• An essential prime implicant includes a minterm covered by no other prime.

• Cost is number of gates plus number of gate inputs. Assume primary inputs available in both true and complemented form.

Minimization Procedure

• Generate all prime implicants.

• Find all essential prime implicants.

• If essential primes do not form a cover, then select minimal set of non-essential primes.

Figure 4.10 Four-variable function f = m(2, 3, 5, 6, 7, 10, 11, 13, 14)

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1 1

1 1

00

01

11

10 1 1

1

Figure 4.11 The function f = m(0, 4, 8, 10, 11, 12, 13, 15)

x 1 x 2 x 3 x 4 00 01 11 10

1

1 1 1 1 00

01

11

10

1

1

1

Figure 4.12 The function f = m(0, 2, 4, 5, 10, 11, 13, 15)

x 1 x 2 x 3 x 4 00 01 11 10

1

1

1

1

1

1

00

01

11

10 1

1

.

Minimization of POS Forms

• Find a cover of the 0’s and form maxterms.

x 1 x 2 x 3

1

00 01 11 10

0

1

1 0 0

1 1 1 0

Figure 4.14 POS minimization of f = M(0, 1, 4, 8, 9, 12, 15)

x 1 x 2 x 3 x 4

0

00 01 11 10

0 0 0

0 1 1 0

1 1 0 1

1 1 1 1

00

01

11

10

Incompletely Specified Functions

• Often certain input conditions cannot occur.

• Impossible inputs are called don’t cares.

• A function with don’t cares is called an incompletely specified function.

• Don’t cares can be used to improve the quality of the logic designed.

Figure 4.15 Two implementations of f = m(2, 4, 5, 6, 10) + D(12, 13, 14, 15)

x 1 x 2 x 3 x 4

0

00 01 11 10

1 d 0

0 1 d 0

0 0 d 0

1 1 d 1

00

01

11

10

Figure 4.15 Two implementations of f = m(2, 4, 5, 6, 10) + D(12, 13, 14, 15)

x 1 x 2 x 3 x 4

0

00 01 11 10

1 d 0

0 1 d 0

0 0 d 0

1 1 d 1

00

01

11

10

Multiple-Output Circuits

• Necessary to implement multiple functions.

• Circuits can be combined to obtain lower cost solution by sharing some gates.

Figure 4.16 An example of multiple-output synthesis

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1 1

1 1

1 1

00

01

11

10

(a) Function

1

f 1

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1 1

1 1 1

1 1

00

01

11

10

(b) Function f 2

f 1

f 2

x 2 x 3 x 4 x 1 x 3

x 1 x 3 x 2 x 3 x 4

(c) Combined circuit for f 1 f 2 and

Figure 4.17 An example of multiple-output synthesis

x 1 x 2 x 3 x 4 00 01 11 10

1

1 1

1

00

01

11

10

(a) Optimal realization of (b) Optimal realization of

1

f 3 f 4

1

1

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1

1

00

01

11

10

1

1 1

(c) Optimal realization of f 3

x 1 x 2 x 3 x 4 00 01 11 10

1

1 1

1

00

01

11

10

1 1

1

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1

1

00

01

11

10

1

1 1

and togetherf 4

Figure 4.17 An example of multiple-output synthesis

f 3

f 4

x 1

x 4

x 3

x 4

x 1

x 1

x 2

x 2

x 4

x 4

(d) Combined circuit for f 3 f 4 and

x 2

x 1 x 2 x 3 x 4 00 01 11 10

00

01

11

10

(a) Function

0

f 1

x 1 x 2 x 3 x 4 00 01 11 10

00

01

11

10

(b) Function f 2

0

0

0 0

0 0

0

0

0

0

0

0 0

x 1 x 2 x 3 x 4 00 01 11 10

00

01

11

10

(a) Optimal realization of (b) Optimal realization off 3 f 4

x 1 x 2 x 3 x 4 00 01 11 10

00

01

11

100 0 0

0

0

0 0 0 0 0 0 0 0

0

0

0 0 0

Figure 4.18 DeMorgan’s theorem in terms of logic gates

x 1

x 2

x 1

x 2

x 1

x 2

x 1

x 2

x 1

x 2

x 1

x 2

x 1 x 2 x 1 x 2 + = (a)

x 1 x 2 + x 1 x 2 = (b)

Figure 4.19 Using NAND gates to implement a sum-of-products

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

x 1 x 2

x 3 x 4 x 5

Figure 4.20 Using NOR gates to implement a product-of-sums

x 1

x 2

x 3

x 4

x 5

x 1

x 2

x 3

x 4

x 5

x 1

x 2

x 3

x 4

x 5

Multilevel Synthesis

• SOP or POS circuits have 2-levels of gates.

• Only efficient for functions with few inputs.

• Many inputs can lead to fan-in problems.

• Multilevel circuits can also be more area efficient.

Figure 4.21 Implementation in a CPLD

D Q

PAL-like block

(from interconnection wires)

x 1 x 2 x 3 x 4 x 5 x 6 x 7 unused

0 0 1

f

Figure 4.22 Implementation in an FPGA

0 0 0 1

0 1 1 1

x 4

x 5

A

B

C

D

x 1

x 6

x 4 f

0 1 1 1

0 0 0 1

x 3

C

D

E

E

f

x 2

x 7

x 5 x 3

0 0 0 1

x 2

x 7

B

0 0 1 0

x 1

x 6

A

Figure 4.23 Using 4-input AND gates to realize a 7-input product term

7 inputs

Figure 4.24 A factored circuit

x 6

x 4

x 1

x 5

x 2

x 3

x 2

x 3

x 5

Example 4.5

Figure 4.25 A multilevel circuit

x 1

x 2

x 3

x 4

f 1

f 2

Impact on Wiring Complexity

• Space on chip is used by gates and wires.

• Wires can be a significant portion.

• Each literal corresponds to a wire.

• Factoring reduces literal count, so it can also reduce wiring complexity.

Functional Decomposition

• Multilevel circuits often require less area.

• Complexity is reduced by decomposing 2-level function into subcircuits.

• Subcircuit implements function that may be used in multiple places.

Example 4.6

Figure 4.26 A multilevel circuit

x 1

x 2

x 3

x 4

f g

Figure 4.27 The structure of a decomposition

1 x 2

x 3 x 4

f

g

h

x

x 1

x 2

x 3

x 4

f g

x 1 x 2 x 3 x 4 00 01 11 10

00

01

11

10

x 1 x 2 x 3 x 4 00 01 11 10

1 1

1 1

1

1

1

00

01

11

10

1

x 5 0 = x 5 1 =

f

1 1 1 1

1 1 1 1

Figure 4.28 An example of decomposition

x 1 x 2 x 5

x 4

f x 3

g

k

Figure 4.29 a Implementation of XOR

x 2

x 1

x 1 x 2

x 2

x 1

x 1 x 2

(a) Sum-of-products implementation

(b) NAND gate implementation

Example 4.8

x 2

x 1

g x 1 x 2

(c) Optimal NAND gate implementation

Figure 4.29 b Implementation of XOR

f = x1 x2 = x1x2 + x1x2 = x1(x1 + x2) + x2(x1 + x2)

Practical Issues

• Functional decomposition can be used to implement general logic functions in circuits with built-in constraints.

• Enormous numbers of possible subfunctions leads to necessity for heuristic algorithms.

Figure 4.30 Conversion to a NAND-gate circuit

x 2

x 1

x 3

x 4

x 5 x 6

x 7

x 2

x 1

x 3

x 4

x 5 x 6

x 7

f

f

(a) Circuit with AND and OR gates

(b) Inversions needed to convert to NANDs

Figure 4.30 Conversion to a NAND-gate circuit

x 2

x 1

x 3

x 4

x 5 x 6

x 7

f

(b) Inversions needed to convert to NANDs

x 2

x 1

x 3

x 4

x 5

x 6 x 7

f

Figure 4.31 Conversion to a NOR-gate circuit

x 2

x 1

x 3

x 4

x 5 x 6

x 7

f

(a) Circuit with AND and OR gates

x 2

x 1

x 3

x 4

x 5

x 6

x 7

f

(a) Inversions needed to convert to NORs

Figure 4.31 Conversion to a NOR-gate circuit

x 2

x 1

x 3

x 4

x 5

x 6

x 7

f

x 2

x 1

x 3

x 4

x 5

x 6 x 7

f

x 2

x 1

x 3

x 4

x 5

x 6

x 7

f

P 3

P 1

P 4

P 5 P 2

Figure 4.32 Circuit example for analysis

x 1

x 2

x 5

x 4

f x 3

P 1

P 4

P 5

P 6 P 8

P 2

P 3

P 9

P 10

P 7

Figure 4.33 Circuit example for analysis

x1

x2

x4

fx5

(c) Circuit with AND and OR gates

x3

Figure 4.34 Circuit example for analysis

x1

x2

x3

x4

x5f

P1

P2

P3

(a) NAND-gate circuit

x1

x2

x3

x4

x5f

(b) Moving bubbles to convert to ANDs and ORs

x 2 x 3

x 1

x 4

x 5

f

P 3

P 1

P 2

P 4

Figure 4.35 Circuit example for analysis

CAD Tools

• espresso – finds exact and heuristic solutions to the 2-level synthesis problem.

• sis – performs multilevel logic synthesis.

• Numerous commercial CAD packages are available from Cadence, Mentor, Synopsys, and others.

Figure 4.46 A complete CAD system

Design conception

Design correct?

Chip configuration

Timing simulation

No

Yes

Design entry, initial synthesis, and functional simulation(see section 2.8)

Physical design

Logic synthesis/optimization

Figure 4.42 VHDL code for the function f = m(1, 4, 5, 6)

Figure 4.43 Logic synthesis options in MAX+PLUS II

Physical Design

• Physical design determines how logic is to be implemented in the target technology.– Placement determines where in target device a

logic function is realized.– Routing determines how devices are to be

interconnected using wires.

Figure 4.44 Results of physical design

Timing Simulation

• Functional simulation does not consider signal propagation delays.

• After physical design, more accurate timing information is available.

• Timing simulation can be used to check if a design meets performance requirements.

Figure 4.45 Timing simulation results

(a) Timing in an FPGA

(b) Timing in a CPLD

Figure 4.46 A complete CAD system

Design conception

Design correct?

Chip configuration

Timing simulation

No

Yes

Design entry, initial synthesis, and functional simulation(see section 2.8)

Physical design

Logic synthesis/optimization

STD_LOGIC type

• Defined in ieee.std_logic_1164 package.

• Enumerated type with 9 values.• ‘1’ – strong one ‘0’ – strong zero

• ‘X’ – strong unknown ‘Z’ – high impedence

• ‘H’ – weak one ‘L’ – weak zero

• ‘W’ – weak unknown ‘U’ – uninitialized

• ‘-’ – don’t care

• We will almost always use STD_LOGIC.

Figure 4.47 VHDL code using STD_LOGIC

Figure 4.48 VHDL code for the function f = m(0, 2, 4, 5, 6)

Figure 4.49 Implementation of the VHDL code for the function f = m(0, 2, 4, 5, 6)

D Q

PAL-like block

(from interconnection wires)

x 1 x 2 x 3 unused

0

0 1

D Q

PAL-like block

(from interconnection wires)

x 1 x 2 x 3 unused

0 1

Figure 4.50 Implementation using XOR synthesis (f = x3 x1x2x3)

Figure 4.51 VHDL code for f = m(0, 2, 4, 5, 6) implemented in a LUT

0

0

1

1

0

1

0

1

1

0

1

0

f

0

0

1

0

1

0

1

1

1

1 1 0

0

0

0

0

1

1

1

1

d

d

d

d

d

d

d

d

i 1 i 2 i 3 i 4

i 1

i 2

i 3

i 4

x 1

x 2

x 3

0

f

LUT

Figure 4.52 The VHDL code for f = m(2, 3, 9, 10, 11, 13)

Figure 4.53 VHDL code for a 7-variable function

Figure 4.54 Two implementations of a 7-variable function

x 6

x 4

f

x 5

0

x 7

x 2 x 3

x 2

x 7

x 4 x 5

0

x 6

x 1 x 3

x 1 x 4 x 5 x 6

x 1 x 3 x 6

x 2 x 3 x 7

x 2 x 4 x 5 x 7

(a) Sum-of-products realization

x 1

x 7

x 2 x 6

x 1 x 6 x 2 x 7 +

x 5

x 3 x 4

f

(b) Factored realization

x 1

Logic Function Representation

• Truth tables

• Algebraic expressions

• Venn diagrams

• Karnaugh maps

• n-dimensional cubes

Figure 4.36 Representation of f = m(1, 2, 3)

x 1

0 0 1 1

0 1 0 1

f

0 1 1 1

01

00

11

10

x 2

x 1

x1

1x

x 2

Figure 4.37 Representation of f = m(0, 2, 4, 5, 6)

x 2

x 1

x 3

000

001

010

011

110

101

100

111

x10

1x0 0x0

x00

10x

xx0

Figure 4.38 Representation of f = m(0, 2, 3, 6, 7, 8, 10, 15)

0000 1000

1010

0110

0011

0010

0111 1111

0x1x

x0x0

x111

n-Dimensional Hypercube

• Function of n variables maps to n-cube.

• Size of a cube is number of vertices.

• A cube with k x’s consists of 2k vertices.

• n-cube has 2n vertices.

• 2 vertices are adjacent if they differ in one coordinate.

• Each vertex in n-cube adjacent to n others.

Figure 4.39 The coordinate *-operation

o

o 0 0

1 1

1 0 x

1 0 x B i A i

0

1

x

A i B i *

C = A * B such that1. C = if Ai * Bi = for more than one i.2. Otherwise, Ci = Ai * Bi when Ai * Bi and Ci = x for the coordinate where Ai * Bi = .

Using *-operation to Find Primes

• f is specified using a set of cubes, Ck of f.• Let ci and cj be any two cubes in Ck.• Apply *-operation to all pairs of cubes in Ck :

– Gk+1 = ci * cj for all ci, cj in Ck

• Form new cover for f as follows:– Ck+1 = Ck Gk+1– redundant cubes

– A is redundant if exists a B s.t. Ai = Bi or Bi = x for all i.

• Repeat until Ck+1 = Ck.

Example 4.14

Example 4.15

Figure 4.40 The coordinate #-operation

o

0 1

1 0 x B i A i

0

1

x

A i B i #

o

C = A # B, such that1. C = A if Ai # Bi = for some i.2. C = if Ai # Bi = for all i.3. Otherwise, C = i(A1, A2, ..., Bi, ... An), where the union is for all i for which Ai = x and Bi x.

Finding Essential Primes

• Let P be set of all prime implicants.

• Let pi denote one prime implicant in P.

• Let DC denote the don’t cares vertices for f.

• Then pi is an essential prime implicant iff:– pi # (P – pi) # DC

Example 4.16

Example 4.17

Procedure to Find Minimal Cover

• Let C0 = ON DC be the initial cover of f.• Find all primes, P, of C0 using *-operation.• Find the essential primes using #-operation.• If essentials cover ON-set then done else

– Delete any nonessential prime that is more expensive than some other prime.

– Use branching technique to select lowest cost primes which cover ON-set.

Figure 4.41 An example four-variable function

1 x 2 x 3 x 4 00 01 11 10

1

1 1 1

1 1

00

01

11

10

x 1 x 2 x 3 x 4 00 01 11 10

d 1

1

d

d

1 1

00

01

11

10

1

x 5 0 = x 5 1 =

d

x

Summary

• Described 2-level logic synthesis methods.

• Discussed multilevel logic synthesis.

• Introduced CAD tools for logic synthesis.