CSE398: Network Systems Design

CSE398:Network Systems Design

Instructor: Dr. Liang ChengDepartment of Computer Science and Engineering

P.C. Rossin College of Engineering & Applied ScienceLehigh University

March 23, 2005

Instructor: Dr. Liang Cheng CSE398: Network Systems Design 03/23/05

Outline

RecapComplexity of network processor designLab time log

Network processor architecturesSummary and homework


Network Processor Architectures

Primary architecture characteristicsPacket flowSoftware architectureAssigning functionality to processor hierarchy


Primary CharacteristicsProcessor hierarchyMemory hierarchyInternal transfer mechanismsExternal interface and communication mechanismsSpecial-purpose hardwarePolling and notification mechanismsConcurrent and parallel execution supportProgramming model and paradigmHardware and software dispatch mechanisms


Processing Hierarchy

One or more embedded RISC processorsOne or more specialized coprocessorsMultiple I/O processorsOne or more fabric interfacesOne or more data transfer units


Processor Hierarchy – Cont’dType Programmable? On Chip?General purpose CPU y possibleEmbedded processor y typicalI/O processor y tCoprocessor n tFabric interface n tData transfer unit n tFramer n possiblePhysical transmitter n possible


Memory HierarchyMemory measurements

Random access latencySequential access latencyThroughputCostInternalExternal


Internal Transfer Mechanisms

Programmers are free to choose … =>Internal busHardware FIFOsTransfer registersOnboard shared memory


External Interface and Communication Mechanisms

Standard and specialized bus interfacesMemory interfacesDirect I/O interfacesSwitching fabric interface


Special-purpose Hardware

ArbitratorI/O manager


Polling and Notification Mechanisms

Handle asynchronous eventsArrival of packetTimer expirationCompletion of transfer across the fabric

Two paradigmsPollingNotification


Concurrent Execution SupportImproves overall throughputMultiple threads of executionProcessor switches context when a thread blocksEmbedded processor

Standard operating systemContext switching in software

I/O processorsNo operating systemHardware support for context switchingLow-overhead or zero-overhead


Concurrent Support Questions

Local or global threads (does thread execution span multiple processors)?Forced or voluntary context switching (are threads pre-emptable)?


Hardware and Software Dispatch Mechanisms

Refers to overall control of parallel operationsDispatcher

Chooses operation to performAssigns to a processor


Implicit and Explicit Parallelism

Explicit parallelismExposes parallelism to programmerRequires software to understand parallel hardware

Implicit parallelismHides parallel copies of functional unitsSoftware written as if single copy executing



Primary architecture characteristicsArchitecture styles and packet flowSoftware architectureAssigning functionality to processor hierarchy


Architecture Styles

Embedded processor plus fixed coprocessorsEmbedded processor plus programmable I/O processorsParallel (number of processors scales to handle load)Pipeline processors


Embedded Processor Architecture

Single processorHandles all functionsPasses packet on

Known as run-to-completion


Parallel ArchitectureEach processor handles 1/N of total load


Pipeline ArchitectureEach processor handles one functionPacket moves through ‘‘pipeline’’


Clock Rates

Embedded processor runs at > wire speedParallel processor runs at < wire speedPipeline processor runs at wire speed



Primary architecture characteristicsArchitecture styles and packet flowSoftware architectureAssigning functionality to processor hierarchy


Software ArchitectureCentral program that invokes coprocessors like subroutinesCentral program that interacts with code on intelligent, programmable I/O processorsCommunicating threadsEvent-driven programRPC-style (program partitioned among processors)Pipeline (even if hardware does not use pipeline)Combinations of the above


Example Uses of Programmable Processors1. Administrative interface2. Classification3. Control of I/O processors4. Exception and error handling5. Forwarding6. High-level egress (e.g., traffic shaping)7. High-level ingress (e.g., reassembly)8. Higher-layer protocols9. Low-level egress operations10. Low-level ingress operations11. Overall management functions12. Routing protocols13. System control


Example Uses of Programmable Processors

General purpose CPUHighest level functionalityAdministrative interfaceSystem controlOverall management functionsRouting protocols

Embedded processorIntermediate functionalityHigher-layer protocolsControl of I/O processorsException and error handlingHigh-level ingress (e.g., reassembly)High-level egress (e.g., traffic shaping)

I/O processorBasic packet processingClassificationForwardingLow-level ingress operationsLow-level egress operations


Packet Flow through HierarchyTo maximize performance, packet processing tasks should be assigned to the lowest level processor capable of performing the task.


Outline

RecapNetwork processor architecturesSummary and homework

CSE398: Network Systems Design

Documents

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