CSE 477. VLSI Systems Design

Sp12 CMPEN 411 L22 S.1

CMPEN 411VLSI Digital Circuits

Spring 2012

Lecture 22: Memery, ROM

[Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]


Memory Definitions Size – Kbytes, Mbytes, Gbytes, Tbytes

Speed

Read Access – delay between read request and the data available

Write Access – delay between write request and the writing of the data into the memory

(Read or Write) Cycle - minimum time required between successive reads or writes

Read

Write

Data

Read Cycle

Read Access Read AccessWrite Cycle

Data Valid

Write Setup Write Access

Data Written


Second

Level

Cache

(SRAM)

A Typical Memory Hierarchy

Control

Datapath

Secondary

Memory

(Disk)

On-Chip Components

RegF

ile

Main

Memory

(DRAM)

Data

Ca

ch

eIn

str

Ca

ch

e

ITLB

DT

LB

eDRAM

Speed (ns): .1’s 1’s 10’s 100’s 1,000’s

Size (bytes): 100’s K’s 10K’s M’s T’s

Cost: highest lowest

By taking advantage of the principle of locality, we can

present the user with as much memory as is available in the cheapest technology

at the speed offered by the fastest technology.


More Memory Definitions

Function – functionality, nature of the storage mechanism

static and dynamic; volatile and nonvolatile (NV); read only (ROM)

Access pattern – random, serial, content addressable

Read Write Memories (RWM) NVRWM ROM

Random Access Non-Random Access

EPROM Mask-prog. ROM

SRAM (cache, register file)

DRAM (main memory)

CAM

FIFO, LIFO

Shift Register

EEPROM

FLASH Electrically-prog. PROM

Input-output architecture – number of data input and output ports (multiported memories)

Application – embedded, secondary, tertiary


Random Access Read Write Memories

SRAM – Static Random Access Memory

data is stored as long as supply is applied

large cells (6 fets/cell) – so fewer bits/chip

fast – so used where speed is important (e.g., caches)

differential outputs (output BL and !BL)

use sense amps for performance

compatible with CMOS technology

DRAM - Dynamic Random Access Memory

periodic refresh required (every 1 to 4 ms) to compensate for the charge loss caused by leakage

small cells (1 to 3 fets/cell) – so more bits/chip

slower – so used for main memories

single ended output (output BL only)

need sense amps for correct operation

not typically compatible with CMOS technology


64

256

1,000

4,000

16,000

64,000

256,000

1,000,000

4,000,000

16,000,000

64,000,000

10

100

1000

10000

100000

1000000

10000000

100000000

1980 1983 1986 1989 1992 1995 1998 2001 2004 2007 2010

Year

Kb

it c

ap

acit

y/c

hip

Evolution in DRAM Chip Capacity

1.6-2.4 m

1.0-1.2 m

0.7-0.8 m

0.5-0.6 m

0.35-0.4 m

0.18-0.25 m

0.13 m

0.1 m

0.07 m

human memory

human DNA

encyclopedia

2 hrs CD audio

30 sec HDTV

book

page

4X growth every 3 years!


Memory Timing: Approaches

DRAM TimingMultiplexed Adressing

SRAM TimingSelf-timed


6-transistor SRAM Storage Cell

!BL BL

WL

M1

M2

M3

M4

M5

M6Q

!Q

Will cover how the cell works in detail in the next lecture


1D Memory Architecture

Word 0

Word 1

Word 2

Word N-1

Word N-2

Storage

Cell

M bits

S0

S1

S2

S3

SN-2

SN-1

Input/Output

N words N select signals

Word 0

Word 1

Word 2

Word N-1

Word N-2

Storage

Cell

M bits

S0

S1

S2

S3

SN-2

SN-1

Input/Output

A0

A1

Ak-1

Decoder reduces # of inputs

K = log2 N

Sp12 CMPEN 411 L22 S.10

2D Memory Architecture

A0A1

AL-1Sense Amplifiers

bit line (BL)

word line (WL)

storage

(RAM) cell

AL

AL+1

AK-1

Read/Write Circuits

Column Decoder

2K-L

M2L

Input/Output (M bits)

amplifies bit line swing

selects appropriate

word from memory row

Sp12 CMPEN 411 L22 S.11

3D (or Banked) Memory Architecture

Input/Output (M bits)

Advantages:

1. Shorter word and bit lines so faster access

2. Block addr activates only 1 block saving power

A1 A0

Sp12 CMPEN 411 L22 S.12

2D 4x4 SRAM Memory Bank

A0

!BLWL[0]

A1

A2

Column Decoder

sense amplifiers

write circuitry

BL

WL[1]

WL[2]

WL[3]

bit line precharge

2 bit words

clocking and

control

enable

read

precharge

BLi BLi+1

Sp12 CMPEN 411 L22 S.13

Quartering Gives Shorter WLs and BLs

Read Precharge Read Precharge

Precharge Circuit Precharge Circuit

Column Decoder

Sense Amps

Column Decoder

AN-1 … Ai

Ai-1 … A0

Write CircuitrySense Amps

Write Circuitrydata

Sp12 CMPEN 411 L22 S.14

Decreasing Word Line Delay

Drive the word line from both sides

Use a metal bypass

Use silicides

polysilicon word line

metal word line

driverdriver

WL

polysilicon word line

metal bypass

WL

Sp12 CMPEN 411 L22 S.15

Read Only Memories (ROMs)

A memory that can only be read and never altered

Programs for fixed applications that once developed and debugged, never need to be changed, only read

Fixing the contents at manufacturing time leads to small and fast implementations.

WL

BL = 1

WL

BL = 0

WL

BL = 0

WL

BL = 1

Sp12 CMPEN 411 L22 S.17

MOS OR ROM Cell Array

predischarge

WL(0)

WL(1)

WL(2)

WL(3)

VDD

VDD

BL(0) BL(1) BL(2) BL(3)

1

0 0 0 0

0

0

0

0

0

1 on on

1 0 0 1

Sp12 CMPEN 411 L22 S.19

Precharged MOS NOR ROM

VDD

precharge

WL(0)

WL(1)

WL(2)

WL(3)

GND

GND

BL(0) BL(1) BL(2) BL(3)

A1

A2

enable

0 1

0

0

0

0

1on on

1 1 1 10 1 1 0

1

0

Sp12 CMPEN 411 L22 S.20

MOS NOR ROM Layout 1

Memory is programmed by adding transistors where needed (ACTIVE mask – early in the fab process)

WL(0)

WL(1)

WL(2)

WL(3)

GND

GND

cell size of

9.5 x 7

metal1 on top of

diffusion

Sp12 CMPEN 411 L22 S.21

MOS NOR ROM Layout 2

Memory is programmed by adding contacts where needed (CONTACT mask –one of the last processing steps)

All transistors are fabricated

the presence of a metal contact creates a 0-cell

WL(0)

WL(1)

WL(2)

WL(3)

GND

GND

cell size of

11 x 7

Sp12 CMPEN 411 L22 S.22

MOS NAND ROM

All word lines high by default with exception of selected row

WL [0]

WL [1]

WL [2]

WL [3]

VDD

Pull-up devices

BL [3]BL [2]BL [1]BL [0]

Sp12 CMPEN 411 L22 S.23

MOS NAND ROM Layout

No contact to VDD or GND necessary;

Loss in performance compared to NOR ROM

drastically reduced cell size

Polysilicon

Diffusion

Metal1 on Diffusion

Cell (8 x 7)

Programmming using

the Metal-1 Layer Only

Sp12 CMPEN 411 L22 S.24

NAND ROM Layout

Cell (5 x 6)

Polysilicon

Threshold-altering

implant

Metal1 on Diffusion

Programmming using

Implants Only

Sp12 CMPEN 411 L22 S.25

Transient Model for 512x512 NOR ROM

WL

BL

Cbit

precharge

cword

metal1

polyrword

Word line parasitics (distributed RC model)

Resistance/cell: 17.5

Wire capacitance/cell: 0.049 fF

Gate capacitance/cell: 0.75 fF

Bit line parasitics (lumped C model)

Resistance/cell: 0.275 (which is negligible)

Wire capacitance/cell: 0.09 fF

Drain capacitance/cell: 0.8 fF

Sp12 CMPEN 411 L22 S.26

Transient Model for 512x512 MOS NAND ROM

Word line parasitics

Similar to NOR ROM

Bit line parasitics

Resistance of cascaded transistors dominates

Drain/Source and complete gate capacitance

Model for NAND ROM

VDD

CL

rword

cword

cbit

rbit

WL

BL

Bit line parasitics

Resistance/cell: 8.7K (compared to 0.275 in NOR)

Speed: NOR: TLH=1.87 ns TLH= 1.2 us

Sp12 CMPEN 411 L22 S.27

Next Lecture and Reminders

Next lecture

SRAM, DRAM, and CAM cores

- Reading assignment – Rabaey, et al, 12.1-12.2.4

CSE 477. VLSI Systems Design

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