CSE 153 Design of Operating Systems - cs.ucr.edunael/cs153/lectures/lec16.pdfCSE 153 –Lecture 11...
Transcript of CSE 153 Design of Operating Systems - cs.ucr.edunael/cs153/lectures/lec16.pdfCSE 153 –Lecture 11...
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CSE 153Design of Operating
Systems
Winter 2020
Lecture 17: Virtual Memory (2)TLBs and Multi-level page tables
Some slides modified from originals by Dave O’hallaron
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Speeding up Translation with a TLB
! Page table entries (PTEs) are cached in L1 like any other memory wordu PTEs may be evicted by other data referencesu PTE hit still requires a small L1 delay
! Solution: Translation Lookaside Buffer (TLB)u Small hardware cache in MMUu Maps virtual page numbers to physical page numbersu Contains complete page table entries for small number of pages
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TLB Hit
MMU Cache/Memory
PA
Data
CPU VA
CPU Chip
PTE
1
2
4
5
A TLB hit eliminates a memory access
TLB
VPN 3
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TLB Miss
MMU Cache/MemoryPA
Data
CPU VA
CPU Chip
PTE
1
2
5
6
TLB
VPN
4
PTEA3
A TLB miss incurs an additional memory access (the PTE)Fortunately, TLB misses are rare. Why?
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CSE 153 – Lecture 11 – Paging 5
Reloading the TLB! If the TLB does not have mapping, two possibilities:
1. MMU loads PTE from page table in memory » Hardware managed TLB, OS not involved in this step» OS has already set up the page tables so that the hardware can
access it directly2. Trap to the OS
» Software managed TLB, OS intervenes at this point» OS does lookup in page table, loads PTE into TLB» OS returns from exception, TLB continues
! A machine will only support one method or the other! At this point, there is a PTE for the address in the TLB
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CSE 153 – Lecture 11 – Paging 6
Page Faults! PTE can indicate a protection fault
u Read/write/execute – operation not permitted on pageu Invalid – virtual page not allocated, or page not in physical
memory! TLB traps to the OS (software takes over)
u R/W/E – OS usually will send fault back up to process, or might be playing games (e.g., copy on write, mapped files)
u Invalid» Virtual page not allocated in address space
! OS sends fault to process (e.g., segmentation fault)» Page not in physical memory
! OS allocates frame, reads from disk, maps PTE to physical frame
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Multi-Level Page Tables! Suppose:
u 4KB (212) page size, 48-bit address space, 8-byte PTE
! Problem:u Would need a 512 GB page table!
» 248 * 2-12 * 23 = 239 bytes
! Common solution:u Multi-level page tablesu Example: 2-level page table
» Level 1 table: each PTE points to a page table (always memory resident)
» Level 2 table: each PTE points to a page (paged in and out like any other data)
Level 1Table
...
Level 2Tables
...
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A Two-Level Page Table HierarchyLevel 1
page table
...
Level 2page tables
VP 0
...
VP 1023
VP 1024
...
VP 2047
Gap
0
PTE 0
...
PTE 1023
PTE 0
...
PTE 1023
1023 nullPTEs
PTE 1023 1023 unallocated
pages
VP 9215
Virtualmemory
(1K - 9)null PTEs
PTE 0
PTE 1
PTE 2 (null)
PTE 3 (null)
PTE 4 (null)
PTE 5 (null)
PTE 6 (null)
PTE 7 (null)
PTE 8
2K allocated VM pagesfor code and data
6K unallocated VM pages
1023 unallocated pages
1 allocated VM pagefor the stack
32 bit addresses, 4KB pages, 4-byte PTEs
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CSE 153 – Lecture 11 – Paging 9
TLB Misses (2)Note that:! Page table lookup (by HW or OS) can cause a
recursive fault if page table is paged outu Assuming page tables are in OS virtual address spaceu Not a problem if tables are in physical memoryu Yes, this is a complicated situation!
! When TLB has PTE, it restarts translationu Common case is that the PTE refers to a valid page in memory
» These faults are handled quickly, just read PTE from the page table in memory and load into TLB
u Uncommon case is that TLB faults again on PTE because of PTE protection bits (e.g., page is invalid)
» Becomes a page fault…
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Simple Memory System Example! Addressing
u 14-bit virtual addressesu 12-bit physical addressu Page size = 64 bytes
13 12 11 10 9 8 7 6 5 4 3 2 1 0
11 10 9 8 7 6 5 4 3 2 1 0
VPO
PPOPPN
VPN
Virtual Page Number Virtual Page Offset
Physical Page Number Physical Page Offset
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Simple Memory System Page Table
Only show first 16 entries (out of 256)
10D0F1110E12D0D0–0C0–0B1090A1170911308
ValidPPNVPN
0–070–06116050–0410203133020–0112800
ValidPPNVPN
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Simple Memory System TLB
! 16 entries! 4-way associative
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
TLBITLBT
0–021340A10D030–073
0–030–060–080–022
0–0A0–040–0212D031
102070–0010D090–030
ValidPPNTagValidPPNTagValidPPNTagValidPPNTagSet
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Simple Memory System Cache
! 16 lines, 4-byte block size! Physically addressed! Direct mapped
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
03DFC2111167
––––0316
1DF0723610D5
098F6D431324
––––0363
0804020011B2
––––0151
112311991190
B3B2B1B0ValidTagIdx
––––014F
D31B7783113E
15349604116D
––––012C
––––00BB
3BDA159312DA
––––02D9
8951003A1248
B3B2B1B0ValidTagIdx
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Address Translation Example #1Virtual Address: 0x03D4
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____
Physical Address
CO ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
TLBITLBT
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
00101011110000
0x0F 0x3 0x03 Y N 0x0D
0001010 11010
0 0x5 0x0D Y 0x36
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Address Translation Example #2Virtual Address: 0x0B8F
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____
Physical Address
CO ___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
TLBITLBT
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
11110001110100
0x2E 2 0x0B N Y TBD
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Address Translation Example #3Virtual Address: 0x0020
VPN ___ TLBI ___ TLBT ____ TLB Hit? __ Page Fault? __ PPN: ____
Physical Address
CO___ CI___ CT ____ Hit? __ Byte: ____
13 12 11 10 9 8 7 6 5 4 3 2 1 0
VPOVPN
TLBITLBT
11 10 9 8 7 6 5 4 3 2 1 0
PPOPPN
COCICT
00000100000000
0x00 0 0x00 N N 0x28
0000000 00111
0 0x8 0x28 N Mem
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Intel Core i7 Memory System
L1 d-cache32 KB, 8-way
L2 unified cache256 KB, 8-way
L3 unified cache8 MB, 16-way
(shared by all cores)
Main memory
Registers
L1 d-TLB64 entries, 4-way
L1 i-TLB128 entries, 4-way
L2 unified TLB512 entries, 4-way
L1 i-cache32 KB, 8-way
MMU (addr translation)
Instructionfetch
Core x4
DDR3 Memory controller3 x 64 bit @ 10.66 GB/s
32 GB/s total (shared by all cores)
Processor package
QuickPath interconnect4 links @ 25.6 GB/s each
To other cores
To I/Obridge
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End-to-end Core i7 Address Translation
CPU
VPN VPO36 12
TLBT TLBI432
...
L1 TLB (16 sets, 4 entries/set)
VPN1 VPN299
PTE
CR3
PPN PPO
40 12
Page tables
TLBmiss
TLBhit
Physicaladdress
(PA)
Result32/64
...
CT CO40 6
CI6
L2, L3, and main memory
L1 d-cache (64 sets, 8 lines/set)
L1hit
L1miss
Virtual address (VA)
VPN3 VPN499
PTE PTE PTE
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Core i7 Level 1-3 Page Table Entries
Page table physical base address Unused G PS A CD WT U/S R/W P=1
Each entry references a 4K child page tableP: Child page table present in physical memory (1) or not (0).
R/W: Read-only or read-write access access permission for all reachable pages.
U/S: user or supervisor (kernel) mode access permission for all reachable pages.
WT: Write-through or write-back cache policy for the child page table.
CD: Caching disabled or enabled for the child page table.
A: Reference bit (set by MMU on reads and writes, cleared by software).
PS: Page size either 4 KB or 4 MB (defined for Level 1 PTEs only).
G: Global page (don’t evict from TLB on task switch)
Page table physical base address: 40 most significant bits of physical page table address (forces page tables to be 4KB aligned)
51 12 11 9 8 7 6 5 4 3 2 1 0UnusedXD
Available for OS (page table location on disk) P=0
526263
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Summary! Programmer’s view of virtual memory
u Each process has its own private linear address spaceu Cannot be corrupted by other processes
! System view of virtual memoryu Uses memory efficiently by caching virtual memory pages
» Efficient only because of localityu Simplifies memory management and programmingu Simplifies protection by providing a convenient interpositioning
point to check permissions
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CSE 153 – Lecture 11 – Paging 21
Summary (2)Paging mechanisms:! Optimizations
u Managing page tables (space)u Efficient translations (TLBs) (time)u Demand paged virtual memory (space)
! Recap address translation! Advanced Functionality
u Sharing memoryu Copy on Writeu Mapped files
Next time: Paging policies
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CSE 153 – Lecture 11 – Paging 22
Mapped Files! Mapped files enable processes to do file I/O using
loads and storesu Instead of “open, read into buffer, operate on buffer, …”
! Bind a file to a virtual memory region (mmap() in Unix)u PTEs map virtual addresses to physical frames holding file datau Virtual address base + N refers to offset N in file
! Initially, all pages mapped to file are invalidu OS reads a page from file when invalid page is accessedu OS writes a page to file when evicted, or region unmappedu If page is not dirty (has not been written to), no write needed
» Another use of the dirty bit in PTE