CS302 Collection of Old Papers

1

**WARNING: Please note that Virtual University takes serious note of unfair means. Anyone found involved in cheating will get an `F` grade in this course.

Write down all the steps in Subjective Questions. Marks will be deducted for missing steps.

4. Circuit Diagrams, Equations and Truth Tables should be clear.

b. If you believe that some essential piece of information is missing, make an appropriate assumption and use it to solve the problem.

a. If you think that there is something wrong with any of the questions, attempt it to the best of your understanding.

3. Do not ask any questions about the contents of this examination from anyone.

2. Calculators are NOT allowed.

1. Attempt all questions.

Please read the following instructions carefully before attempting any of the questions:

Maximum Time Allowed: (2 Hours)

Date

PVC Name / Code

Name

Student ID / Login ID

Duration:120 Min Total Marks:70

FINALTERM EXAMINATION

SEMESTER FALL 2004

CS302-Digital Logic Design (S1)

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2

Assume the Positive edge triggering. . BQand B Q,AQA,Draw the timing diagram of Q

Marks: 8 Question No: 2

b) Convert the decimal numbers 78 and 34 into Octal. Using octal addition, add the two numbers and convert the octal result back into decimal and verify the answer.

B A B C B C D A B C D+ + + + + + + +A )( )( )( )(a) Convert each of the following POS expression to minimum SOP expression using a Karnaugh Map.

Marks: 8+8 Question No: 1

Marks

Total Q7 Q6 Q5 Q4 Q3 Q2 Q1 Question

For Teacher’s use only

3


Q4

C

J4

K4

C

J 3

K3

Q1

HIGH

Q2

FF0LSB

C

J2

K2

Q0

CLK

C

J0

K0

Q3

C

J1

K1

Show the complete timing diagram for the 5 stage synchronous binary counter.


4

d) What determines the accuracy of quantization process?

c) If the highest frequency component in an analog signal is 20kHz, what is minimum sample frequency?

b) Why you must hold a sampled value? a) What does sampling mean?

Briefly answer the following questions:


Implement a 4-bit Johnson Counter using J-K flip-flops


Data out Q3

SHIFT/LOAD

1 65432CLK

CLKSER

1 0 1 0D0 D3D2D1

Data outQ3

SHIFT/LOAD

C

=0 as shown. Develop the data-output waveform in relation to the inputs.

3=1, D2=0, D1=1, D0

waveform given in the figure. The serial data input (SER) is a 0. The parallel data inputs are D

/SHIFT LOADShow the data output waveform for a 4-bit register with the parallel input data and the clock and


d) How many cores receive at least half-current during a write cycle? c) How many cores receive current during a read cycle? b) How many flip-flops are in the address and buffer registers? a) How many matrices are needed?

It is required to construct a memory with 256 words, 16 bits per word. Cores are available in a matrix of 16 rows and 16 columns.

1










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MIDTERM EXAMINATION

SEMESTER SPRING 2005



2

c) a fuse b) a capacitor a) a flip –flop

5) The storage cell in SRAM is

d) S=0,R=0 c) S=1,R=1 b) S=0,R=1 a) S=1,R=0

4) The invalid state of an SR latch occurs when

d) only after being cleared c) only after a load pulse b) 8 bits at a time a) one bit at a time

3) How will a serial in/serial out shift register accept data serially?

d) 16 c) 4 b) 2 a) 1

2) How many states does a modulus-4 counter have?

d) addition c) division b) subtraction a) multiplication

1) The OR gate performs Boolean ___________.

Select the best possible choice.

Marks: 2+2+2+2+2=10 Question No: 1

Marks

Total Q8 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Question For Teacher’s use only

3

Serial dataoutput

Serial dataoutput

Serialdata input

CLK

FF0 FF1 FF2 FF3

Q3

Q0

C

D Q1

C

D Q2

C

D Q3

C

D

For the data input and clock in figure, determine the states of each flip-flop in the shift register for the diagram and show the Q waveforms. Assume that the register contains all 1s initially.


Design a 2-bit count-down counter. This is a sequential circuit with two flip flops and one input x. when x=0 the state of flip flop doesn’t change. When x=1 the state sequence is 11, 10.01,00,11 and repeat.


Draw the circuit diagram of the 4x1 Multiplexer. Also write down its truth table?

Marks: 10 Question No: 3 c) What is 2’s complement of 0011 1001? b) Define JEDEC file

( , , ) (1,3,5,6,7)F x y z =∑

a) Simplify the Boolean function using k-map and draw the circuit diagram.

Marks: 12+2+2=16 Question No: 2

d) a magnetic domain

4

c) Define ROM and list the types of read-only memories? b) What does SIMM stands for? a) What does DSP stands for?

Marks:2+2+1+5=10 Question No: 8 b) Name any four performance characteristics of Digital-to-Analog Converters.

b. Define noise margin? a. What is current sourcing?

a) Answer the following questions briefly:

Marks: 6+4 Question No: 7

Draw block diagram of 4-bit Johnson Counter?


Serialdata input

Q0

Q1

Q2

Q3

CLK

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FINALTERM EXAMINATION Spring 2009

CS302- Digital Logic Design (Session - 2) Question No: 1 ( Marks: 1 ) - Please choose one The diagram given below represents __________

► Demorgans law

► Associative law ► Product of sum form ► Sum of product form Question No: 2 ( Marks: 1 ) - Please choose one Excess-8 code assigns _______ to “+7” ► 0000 ► 1001 ► 1000 ► 1111 Question No: 3 ( Marks: 1 ) - Please choose one NOR gate is formed by connecting _________ ► OR Gate and then NOT Gate ► NOT Gate and then OR Gate ► AND Gate and then OR Gate ► OR Gate and then AND Gate Question No: 4 ( Marks: 1 ) - Please choose one

A full-adder has a Cin = 0. What are the sum (<PRIVATE

"TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1?

► = 0, Cout = 0

= 0, Cout = 0

► = 0, Cout = 1

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Visit vujannat.ning.Com For Video Lectures ,previous assigmnets ,Papers,Chat, Study discussions and many more.

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► = 1, Cout = 0

► = 1, Cout = 1

Question No: 5 ( Marks: 1 ) - Please choose one adder has -A particular half ► 2 INPUTS AND 1 OUTPUT ► 2 INPUTS AND 2 OUTPUT ► 3 INPUTS AND 1 OUTPUT ► 3 INPUTS AND 2 OUTPUT Question No: 6 ( Marks: 1 ) - Please choose one THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT

MULTIPLEXER, ARE CONNECTED TOGETHER THROUGH A 4-INPUT __________ GATE ► AND ► OR ► NAND ► XOR Question No: 7 ( Marks: 1 ) - Please choose one A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY

THE MANUFACTURER.

► TRUE ► FALSE Question No: 8 ( Marks: 1 ) - Please choose one FLIP FLOPS ARE ALSO CALLED _____________ ► BI-STABLE DUALVIBRATORS ► BI-STABLE TRANSFORMER ► BI-STABLE MULTIVIBRATORS ► Bi-stable singlevibrators Question No: 9 ( Marks: 1 ) - Please choose one A POSITIVE EDGE-TRIGGERED FLIP-FLOP CHANGES ITS STATE WHEN ________________ ► LOW-TO-HIGH TRANSITION OF CLOCK ► HIGH-TO-LOW TRANSITION OF CLOCK ► ENABLE INPUT (EN) IS SET ► PRESET INPUT (PRE) IS SET Question No: 10 ( Marks: 1 ) - Please choose one ___________ IS ONE OF THE EXAMPLES OF SYNCHRONOUS INPUTS. ► J-K INPUT ► EN INPUT

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► Preset input (PRE) ► CLEAR INPUT (CLR) Question No: 11 ( Marks: 1 ) - Please choose one THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A ___________ ► GATED FLIP-FLOPS ► PULSE TRIGGERED FLIP-FLOPS ► POSITIVE-EDGE TRIGGERED FLIP-FLOPS ► NEGATIVE-EDGE TRIGGERED FLIP-FLOPS Question No: 12 ( Marks: 1 ) - Please choose one THE DESIGN AND IMPLEMENTATION OF SYNCHRONOUS COUNTERS START FROM

_________ ► TRUTH TABLE

► K-MAP ► STATE TABLE ► STATE DIAGRAM Question No: 13 ( Marks: 1 ) - Please choose one THE HOURS COUNTER IS IMPLEMENTED USING __________ ► ONLY A SINGLE MOD-12 COUNTER IS REQUIRED ► MOD-10 AND MOD-6 COUNTERS ► MOD-10 AND MOD-2 COUNTERS ► A SINGLE DECADE COUNTER AND A FLIP-FLOP Question No: 14 ( Marks: 1 ) - Please choose one GIVEN THE STATE DIAGRAM OF AN UP/DOWN COUNTER, WE CAN FIND __________

► THE NEXT STATE OF A GIVEN PRESENT STATE ► THE PREVIOUS STATE OF A GIVEN PRESENT STATE ► BOTH THE NEXT AND PREVIOUS STATES OF A GIVEN STATE ► The state diagram shows only the inputs/outputs of a given states Question No: 15 ( Marks: 1 ) - Please choose one In ________ outputs depend only on the current state.

► Mealy machine

► MOORE MACHINE

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► STATE REDUCTION TABLE ► STATE ASSIGNMENT TABLE Question No: 16 ( Marks: 1 ) - Please choose one A SYNCHRONOUS DECADE COUNTER WILL HAVE _______ FLIP-FLOPS ► 3 ► 4 ► 7 ► 10 Question No: 17 ( Marks: 1 ) - Please choose one A MULTIPLEXER WITH A REGISTER CIRCUIT CONVERTS _________ ► SERIAL DATA TO PARALLEL ► PARALLEL DATA TO SERIAL ► Serial data to serial ► PARALLEL DATA TO PARALLEL Question No: 18 ( Marks: 1 ) - Please choose one The alternate solution for a multiplexer and a register circuit is _________

► PARALLEL IN / SERIAL OUT SHIFT REGISTER ► SERIAL IN / PARALLEL OUT SHIFT REGISTER ► PARALLEL IN / PARALLEL OUT SHIFT REGISTER ► SERIAL IN / SERIAL OUT SHIFT REGISTER Question No: 19 ( Marks: 1 ) - Please choose one AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF

REGISTER AFTER THREE CLOCK PULSES? ► 2 ► 4 ► 6 ► 8 Question No: 20 ( Marks: 1 ) - Please choose one A 8-BIT SERIAL IN / PARALLEL OUT SHIFT REGISTER CONTAINS THE VALUE “8”, _____

CLOCK SIGNAL(S) WILL BE REQUIRED TO SHIFT THE VALUE COMPLETELY OUT OF THE

REGISTER. ► 1 ► 2

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► 4 ► 8 Question No: 21 ( Marks: 1 ) - Please choose one 5-BIT JOHNSON COUNTER SEQUENCES THROUGH ____ STATES ► 7 ► 10 ► 32 ► 25 Question No: 22 ( Marks: 1 ) - Please choose one IN ________ Q OUTPUT OF THE LAST FLIP-FLOP OF THE SHIFT REGISTER IS CONNECTED TO

THE DATA INPUT OF THE FIRST FLIP-FLOP OF THE SHIFT REGISTER. ► MOORE MACHINE ► Meally machine ► Johnson counter ► Ring counter Question No: 23 ( Marks: 1 ) - Please choose one DRAM STANDS FOR __________ ► DYNAMIC RAM ► Data RAM ► Demoduler RAM ► None of given options Question No: 24 ( Marks: 1 ) - Please choose one IF THE FIFO MEMORY OUTPUT IS ALREADY FILLED WITH DATA THEN ________

► IT IS LOCKED; NO DATA IS ALLOWED TO ENTER ► IT IS NOT LOCKED; THE NEW DATA OVERWRITES THE PREVIOUS DATA. ► PREVIOUS DATA IS SWAPPED OUT OF MEMORY AND NEW DATA ENTERS ► NONE OF GIVEN OPTIONS Question No: 25 ( Marks: 1 ) - Please choose one LUT is acronym for _________

► LOOK UP TABLE ► LOCAL USER TERMINAL ► LEAST UPPER TIME PERIOD ► NONE OF GIVEN OPTIONS

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Question No: 26 ( Marks: 1 ) - Please choose one ______ OF A D/A CONVERTER IS DETERMINED BY COMPARING THE ACTUAL OUTPUT OF A D/A

CONVERTER WITH THE EXPECTED OUTPUT.

► RESOLUTION ► Accuracy ► Quantization ► Missing Code Question No: 27 ( Marks: 1 ) - Please choose one

In the circuit diagram of 3-bit synchronous counterThe red rectangle would ,shown above be replaced which gate?

► AND ► OR ► NAND ► XNOR Question No: 28 ( Marks: 1 ) - Please choose one WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO

_________ ► THE FLOP-FLOP IS TRIGGERED ► Q=0 AND Q’=1 ► Q=1 AND Q’=0 ► THE OUTPUT OF FLIP-FLOP REMAINS UNCHANGED Question No: 29 ( Marks: 1 ) - Please choose one A FREQUENCY COUNTER ______________

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► Counts pulse width ► COUNTS NO. OF CLOCK PULSES IN 1 SECOND ► Counts high and low range of given clock pulse ► NONE OF GIVEN OPTIONS Question No: 30 ( Marks: 1 ) - Please choose one Stack is an acronym for _________ ► FIFO memory ► LIFO memory ► Flash Memory ► Bust Flash Memory Question No: 31 ( Marks: 1 ) What is the role of MOS transistor in Mask ROM. Question No: 32 ( Marks: 1 ) THE GROUP OF BITS 10110111 IS SERIALLY SHIFTED (RIGHT-MOST BIT FIRST) INTO AN 8-BIT PARALLEL

OUTPUT SHIFT REGISTER WITH AN INITIAL STATE 11110000. WHAT WILL BE THE CONTENTS OF REGISTER

AFTER TWO CLOCK PULSES THE REGISTER CONTAINS?

Question No: 33 ( Marks: 2 ) DRAW THE CIRCUIT DIAGRAM OF GATED S-R LATCH. Question No: 34 ( Marks: 2 ) HOW MANY BYTES WILL BE THERE IN 32 K X 4 MEMORY?

32 X 1024BYTES X 4 = 131072 BYTES Question No: 35 ( Marks: 3 ) THE ________ OF FIRST 74HC163 COUNTER IS CONNECTED TO _______ AND

________ INPUTS OF OTHER 74HC COUNTER TO FORM A SINGLE CASCADED COUNTER

Question No: 36 ( Marks: 3 )

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GIVEN THE FOLLOWING STATEMENT USED IN PLD PROGRAMMING: Y PIN 23 ISTYPE ‘COM’; Explain what does this statement mean? VARIABLE Y AT OUTPUT PIN 23 WHICH IS A COMBINATIONAL OUTPUT AVAILABLE DIRECTLY

FROM THE AND-OR GATE ARRAY OUTPUT. Y = VARIABLE Y PIN 23 = PIN NUMBER 23 ISTYPE “COM” = OUTPUT TYPE COMBINATIONAL

Question No: 37 ( Marks: 3 ) WHAT IS MEMORY EXPANSION PROCESS?

Question No: 38 ( Marks: 5 ) CONSIDER THE TABLE GIVEN BELOW, APPLY THE STATE REDUCTION PROCESS ON THE

STATES GIVEN IN THE TABLE AND REDUCE THE NUMBER OF STATES AS MUCH AS POSSIBLE. PRESENT STATE NEXT STATE OUTPUT X=0 X=1 X=0 X=1 A F B 0 0 B B C 1 1 C A F 0 1 D E D 1 0 E A G 0 1 F D E 0 0 G D E 0 0

Question No: 39 ( Marks: 5 ) PERFORMANCE CHARACTERISTICS OF D/A CONVERTERS ARE DETERMINED BY FIVE

PARAMETERS. NAME THEM. Question No: 40 ( Marks: 10 ) GIVEN BELOW IS THE CIRCUIT DIAGRAM OF BI-DIRECTIONAL 4-BIT SERIAL IN/SERIAL OUT

SHIFT REGISTER. REGISTER SHIFTS DATA LEFT OR RIGHT DEPENDS ON THE

LEFT/RIGHT SIGNAL APPLIED. EXPLAIN HOW THIS CIRCUIT SHIFTS DATA LEFT AND

RIGHT.

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Question No: 41 ( Marks: 10 ) BRIEFLY EXPLAIN ADDRESS MULTIPLEXING IN DRAM.

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MIDTERM EXAMINATION

FALL 2006

CS302 - DIGITAL LOGIC DESIGN (Session - 3 )

Marks: 55

Time: 60min

StudentID/LoginID: ______________________________

Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Wednesday, November 22, 2006









For Teacher's use only Question 1 2 3 4 5 6 7 8 9 Total

Marks

Question No: 1 ( Marks: 2 ) - Please choose one According to rule of Boolean Algebra; A+0

►

0

►

A

►

1

►

A'

Question No: 2 ( Marks: 2 ) - Please choose one If a three-input AND gate has eight input possibilities, how many of those possibilities will result in a HIGH output? ►

1

►

2

►

7

►

8

Question No: 3 ( Marks: 2 ) - Please choose one A multiplexer has ►

one input and several outputs

►

one input and one output

►

several inputs and several outputs

►

several inputs and one output

Question No: 4 ( Marks: 2 ) - Please choose one 8 X 101 + 6 X 100

is equal to

►

8.6

►

86

►

860

►

0.86

Question No: 5 ( Marks: 2 ) - Please choose one OLMC is an acronym for ►

Output Logic Main Cell

►

Optimum Logic Multiple Channel

►

Output Logic Macro Cell

►

Odd-parity Logic Master Check

Question No: 6 ( Marks: 10 ) Consider the following Octal number: (5+5) a) (453)

Convert it into Binary number system. 8

b) Calculate (2394)16 + (7187)

16

Question No: 7 ( Marks: 10 ) Minimize the following problems using the Karnaugh maps method. Z = f(A,B,C) = B + B + BC + A

Question No: 8 ( Marks: 10 ) Draw a circuit diagram of 8-to-3 line Binary Encoder.

Question No: 9 ( Marks: 15 ) Given the following Boolean function. (7+8) F x yz wxy wxy= + +

i) Obtain the truth table of the function. ii) Draw the logical diagram using the original Boolean expression










Maximum Time Allowed: (1 Hour)

Date

PVC Name / Code

Name



MIDTERM EXAMINATION

SEMESTER SPRING 2005



IV. AND III. exclusive-OR II. OR I. NOR

e) Which gate is best used as a basic comparator?

IV. one AND gate III. three AND gates II. three AND gates and four inverters I. three AND gates and three inverters

, it takes one OR gate and BCD ABCD ABCD+ +Ad) To implement the expression

IV. 110 III. 001 II. 111 I. 100

c) The difference of 111 - 001 equals

IV. several inputs and one output III. several inputs and several outputs II. one input and one output I. one input and several outputs

b) A demultiplexer has

IV. all inputs are LOW III. any input is LOW II. any input is HIGH I. all inputs are HIGH

a) A NOR’s gate output is HIGH if

Select the best possible choice.

Marks: : 2+2+2+2+2=10 Question No: 1

Marks

Total Q5 Q4 Q3 Q2 Q1 Question For Teacher’s use Only

BCD ACD BCD ABCD+ + +A

b) Expand each expression to standard SOP form.

11 10 1 01 00 0

1 0 A\B

(Hint) for 2 –variable k-map a) Draw a 4-variable K-map and label each cell according to its binary value.

Marks:6+4=10 Question No: 4

1 1 1 1 1 0 1 1 0 1 0 1 1 0 0 1 0 1 1 0 1 0 1 0 0 1 0 0 1 0 0 0 X C B A

OUTPUTS INPUTS Implement a logic circuit for the truth table given below:


into Binary number system and then take 2’s complement of the resultant binary number. (Show all necessary steps.)

16 Convert (-7A)


Draw a truth table and circuit diagram of 4 bit parallel adder?

Marks: 4+6=10 Question No: 5

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SPRING 2007


Marks: 45

Time: 60min


Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Friday, April 27, 2007










For Teacher's use only Question 1 2 3 4 5 6 7 Total

Marks

http://www.vupages.com/

http://forum.vupages.com/

Question No: 1 ( Marks: 10 ) (a) Convert the decimal number 6789.8 to octal correct to 3 decimal places Marks = 4 (b) Draw the truth table for the following expression F = xy + x’z Marks = 6 Question No: 2 ( Marks: 15 ) Use Quine-McCluskey method to find all prime implicants for the given expression f (a, b, c, d) = Σm(3,7,9,14) +Σd(1,4,6,11 Question No: 3 ( Marks: 8 ) Implement f (A, B, C, D) = AC’D’ + B’D using a 4-to-1 multiplexer. Choose the appropriate control inputs Question No: 4 ( Marks: 3 ) - Please choose one 2’s complement of hexadecimal number B70A is ► B70B ► B709 ► 48F6 ► 48F5

Question No: 5 ( Marks: 3 ) - Please choose one The minterm expansion for F(A,B,C) = (A + B + C)(A + B’ + C’)(A’ + B + C’)(A’ + B’ + C) is ► F(A,B,C) = ΠM(0,3,5,6) ► F(A,B,C) = ∑m(0,3,5,6) ► F(A,B,C) = ΠM(1,2,4,7) ► F(A,B,C) = ∑m(1,2,4,7)

Question No: 6 ( Marks: 3 ) - Please choose one The minimum expression of the logic diagram shown below is:

► (A’D + B) ► ((D +(A’B)’)(B + C)’ )’ ► (AB’D) +B’ +C’ ► B +C

Question No: 7 ( Marks: 3 ) - Please choose one An 8-line to 1-line multiplexer is connected as shown in the following figure

where output Y = F(x, y, z) and z is the least significant input. Which of the following functions does Y generate? ► F(x, y, z) = z ► F(x, y, z) = y ► F(x, y, z) = z' ► F(x, y, z) = x

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Largest Online Community of VU Students FINALTERM EXAMINATION

FALL 2006


Marks: 60

Time: 120min


Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Tuesday, February 13, 2007








For Teacher's use only Question 1 2 3 4 5 6 7 8 9 10 Total

Marks Question No: 1 ( Marks: 2 ) - Please choose one The OR gate performs Boolean ___________. ►

multiplication

►

subtraction

► division

http://www.vupages.com/

http://forum.vupages.com/

►

addition

Question No: 2 ( Marks: 2 ) - Please choose one How many states does a modulus-4 counter have? ►

1

►

2

►

4

►

16

Question No: 3 ( Marks: 2 ) - Please choose one How will a serial in/serial out shift register accept data serially? ►

one bit at a time

►

8 bits at a time

►

only after a load pulse

►

only after being cleared

Question No: 4 ( Marks: 2 ) - Please choose one If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be ►

set

►

reset

►

invalid

►

clear

Question No: 5 ( Marks: 2 ) - Please choose one The storage cell in SRAM is ►

a flip –flop

►

a capacitor

►

a fuse

► a magnetic domain

Question No: 6 ( Marks: 5 ) Convert the following POS expression to minimum SOP expression using K-Map

( ) ( ) ( ) ( )A B A B C B C D A B C D+ + + + + + + +

Question No: 7 ( Marks: 5 ) Draw the circuit diagram of the 4x1 Multiplexer. Question No: 8 ( Marks: 20 ) Design a 2-bit count-down counter. This is a sequential circuit with two flip flops and one input x. when x=0 the state of flip flop doesn’t change. When x=1 the state sequence is 11, 10, 01, 00,11 and repeat. Question No: 9 ( Marks: 10 ) Show a complete timing diagram showing the parallel outputs for the shift register in figure. Use the waveforms in figure below with the register initially clear.

C

D

C

D

C

D

C

DData input

CLK

Q3Q2Q1Q0

CLK

Q0

Q1

Q2

Q3

Serialdata in

Question No: 10 ( Marks: 10 ) Draw block diagram of 4-bit Johnson Counter?

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MIDTERM EXAMINATION

Spring 2009

CS302- Digital Logic Design (Session - 1)

Question No: 1 ( Marks: 1 ) - Please choose one

GAL

can be reprogrammed because instead of fuses _______ logic is used in it

► E2CMOS

► TTL

► CMOS+

► None of the given options


The

device shown here is most likely a

► Comparator

► Multiplexer

► Demultiplexer

► Parity generator


If

“1110” is applied at the input of BCD-to-Decimal decoder which output pin will be activated:

► 2nd

► 4th

► 14th

► No output wire will be activated


Half-Adder Logic circuit contains 2 XOR Gates

► True ► False


A

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particular Full Adder has ► 3 inputs and 2 output

► 3 inputs and 3 output




CBASum ⊕⊕=

ABBACCarryOut +⊕= )(

are the Sum and CarryOut expression of

► Half Adder

► Full Adder

► 3-bit parralel adder

► MSI adder cicuit


A

Karnaugh map is similar to a truth table because it presents all the possible values of input

variables and the resulting output of each value.

► True

► False


The

output A < B is set to 1 when the input combinations is __________

► A=10, B=01

► A=11, B=01

► A=01, B=01 ► A=01, B=10


The

4-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4

► 8

► 12 ► 16


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Generally, the Power dissipation of _______ devices remains constant throughout their operation.

► TTL

► CMOS 3.5 series

► CMOS 5 Series

► Power dissipation of all circuits increases with time.


The

decimal “8” is represented as _________ using Gray-Code.

► 0011 ► 1100

► 1000

► 1010


(A+B).(A+C) = ___________

► B+C ► A+BC

► AB+C

► AC+B


A.(B

+ C) = A.B + A.C is the expression of _________________

► Demorgan’s Law

► Commutative Law

► Distributive Law

► Associative Law


NOR Gate can be used to perform the operation of AND, OR and NOT Gate

► FALSE ► TRUE


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In

ANSI/IEEE Standard 754 “Mantissa” is represented by ___32-bits______ bits

► 8-bits

► 16-bits ► 32-bits

► 64-bits


Caveman number system is Base _5_____ number system

► 2 ► 5

► 10

► 16


Briefly state the basic principle of Repeated Multiplication-by-2 Method.


How

standard Boolean expressions can be converted into truth table format.


What will be the out put of the diagram given below


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When an Input (source) file is created in ABEL a module is created which has three sections. Name

These three sections.


Explain “AND” Gate and some of its uses


Write down different situations where we need the sequential circuits.

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MIDTERM EXAMINATION Spring 2009

CS302- Digital Logic Design (Session - 1) Question No: 1 ( Marks: 1 ) - Please choose one

In

the binary number “10011” the weight of the most significant digit is ____ ► 24

(2 raise to power 4) ► 23 (2 raise to power 3) ► 20 (2 raise to power 0) ► 21 (2 raise to power 1) Question No: 2 ( Marks: 1 ) - Please choose one

An

S-R latch can be implemented by using _________ gates

► AND, OR ► NAND, NOR ► NAND, XOR ► NOT, XOR Question No: 3 ( Marks: 1 ) - Please choose one

A

latch has _____ stable states

► One ► Two ► Three ► Four Question No: 4 ( Marks: 1 ) - Please choose one

Sequential circuits have storage elements

► True ► False Question No: 5 ( Marks: 1 ) - Please choose one

The

ABEL symbol for “XOR” operation is

► $ ► # ► !

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► & Question No: 6 ( Marks: 1 ) - Please choose one

A

Demultiplexer is not available commercially.


Using multiplexer as parallel to serial converter requires ___________ connected to the multiplexer

► A parallel to serial converter circuit ► A counter circuit ► A BCD to Decimal decoder ► A 2-to-8 bit decoder Question No: 8 ( Marks: 1 ) - Please choose one

The

device shown here is most likely a

► Comparator ► Multiplexer ► Demultiplexer ► Parity generator Question No: 9 ( Marks: 1 ) - Please choose one

The

main use of the Multiplexer is to

► Select data from multiple sources and to route it to a single Destination ► Select data from Single source and to route it to a multiple Destinations ► Select data from Single source and to route to single destination ► Select data from multiple sources and to route to multiple destinations

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A

logic circuit with an output consists of ________.

► two AND gates, two OR gates, two inverters ► three AND gates, two OR gates, one inverter ► two AND gates, one OR gate, two inverters ► two AND gates, one OR gate Question No: 11 ( Marks: 1 ) - Please choose one

The

binary value of 1010 is converted to the product term

► True

► False Question No: 12 ( Marks: 1 ) - Please choose one

The

3-variable Karnaugh Map (K-Map) has _______ cells for min or max terms

► 4 ► 8 ► 12 ► 16


Following is standard POS expression


The

output of the expression F=A+B+C will be Logic ________ when A=0, B=1, C=1. the symbol’+’ here represents OR Gate.

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► Undefined ► One ► Zero ► 10 (binary) Question No: 15 ( Marks: 1 ) - Please choose one

The

Extended ASCII Code (American Standard Code for Information Interchange) is a _____ code

► 2-bit ► 7-bit ► 8-bit ► 16-bit Question No: 16 ( Marks: 1 ) - Please choose one

The

diagram given below represents __________

► Demorgans law ► Associative law ► Product of sum form ► Sum of product form Question No: 17 ( Marks: 1 )

How can a PLD be programmed?


How many input and output bits do a Half-Adder contain? Question No: 19 ( Marks: 2 )

Explain the difference between 1-to-4 Demultiplexer 2-to-4 Binary Decoder?


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Name the three declarations that are included in “declaration section” of the module that is created when an Input (source) file is created in ABEL.


Explain with example how noise affects Operation of a CMOS AND Gate circuit. Question No: 22 ( Marks: 10 )

explain the SOP based implementation of the Adjacent 1s Detector Circuit

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http://vujannat.ning.com BEST SITE TO HELP STUDENTS

MIDTERM EXAMINATION

SUMMER 2007


Marks: 50

Time: 120min


Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Friday, August 17, 2007









5. Use of cell phone during the examination is strictly prohibited, otherwise

strict disciplinary action will be taken as per university rules


For Teacher's use only Question 1 2 3 4 5 6 7 8 9 Total

Marks


Convert decimal numbers 79 and 83 into binary. Using binary addition, add the two numbers and convert the binary result back into decimal and verify the answer.

Question No: 2 ( Marks: 12 ) (a) Draw the truth table representing the function defined by the following expression:

)D)CB(A( +

(b) Implement the circuit for the expression using only NAND gates. )D)CB(A( +

Question No: 3 ( Marks: 10 ) Use Karnaugh map to find the minimum SOP form for following expression F = Σ (3, 5, 7, 8, 10, 12, 13, 14, 15)

Question No: 4 ( Marks: 10 ) Write the Boolean expression and draw the truth table representing the function of a 4x2 Encoder. Draw the circuit diagram of the Encoder.

Question No: 5 ( Marks: 2 ) - Please choose one Determine the values of A, B, C, and D that make the sum term equal to zero. ►

A = 1, B = 0, C = 0, D = 0

►

A = 1, B = 0, C = 1, D = 0

►

A = 0, B = 1, C = 0, D = 0

►

A = 1, B = 0, C = 1, D = 1

Question No: 6 ( Marks: 2 ) - Please choose one A NAND gate's output is LOW if ►

all inputs are LOW

►

all inputs are HIGH

►

any input is LOW

►

any input is HIGH

Question No: 7 ( Marks: 2 ) - Please choose one One advantage TTL has over CMOS is that TTL is ►

less expensive

►

not sensitive to electrostatic discharge

►

faster

►

more widely available

Question No: 8 ( Marks: 2 ) - Please choose one Fan-out is specified in terms of ►

voltage

►

current

►

watt

►

unit loads

Question No: 9 ( Marks: 2 ) - Please choose one The power dissipation, PD

, of a logic gate is the product of the

►

dc supply voltage and the peak current

►

dc supply voltage and the average supply current

►

ac supply voltage and the peak current

►

ac supply voltage and the average supply current

Connecting VU Students

FINALTERM EXAMINATION SPRING 2006


Marks: 100

Time: 120min


Student Name: ______________________________

Center Name/Code: ______________________________

Exam Date: Saturday, August 19, 2006










For Teacher's use only Question 1 2 3 4 5 6 7 8 9 10 Total


Marks Question 11 12

Marks Question No: 1 ( Marks: 2 ) - Please choose one What is the decimal value of the terminal count of a 4-bit binary counter? ►

10

►

12

►

15

►

16

Question No: 2 ( Marks: 2 ) - Please choose one The 1's complement of 10110111 is __________. ►

10110111

►

01001011

►

01101011

►

01001000

Question No: 3 ( Marks: 2 ) - Please choose one To serially shift a byte of data into a shift register, there must be? ►

One clock pulse

►

One load pulse.

►

Eight clock pulses.

►

One clock pulse for each 1 in the data.

Question No: 4 ( Marks: 2 ) - Please choose one What is the difference between a D latch and a D flip-flop?


►

The D latch has a clock input.

►

The D flip-flop has an enable input.

►

The D latch is used for faster operation.

►

The D flip-flop has a clock input.

Question No: 5 ( Marks: 2 ) - Please choose one For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will ______ if the clock goes HIGH. ►

toggle

►

set

►

reset

►

not change

Question No: 6 ( Marks: 12 ) Draw the circuit diagram and truth table of the following equation.

( , , )F x y z =∑ (0, 2,3,5,7)

Question No: 7 ( Marks: 10 ) Draw the truth table of a Half-Adder. Draw the logical circuit diagram of a half-adder. Write Boolean expressions for all the output signals of half adder circuit. Question No: 8 ( Marks: 20 ) Design a counter to produce the following sequence using J-K Flip-Flops. 1,4,3,5,7,6,2,1 Question No: 9 ( Marks: 12 ) Draw the circuit diagram of the 2-input 4-bit Multiplexer. Also write down its function table? Question No: 10 ( Marks: 14 )


a) For a gated D latch, determine the and Q Q

outputs for the inputs in figure. Show them in proper relation to the enable input. Assume Q starts LOW.

D

EN

Q

Q

b) What is the difference between Flip-flop and latches? Question No: 11 ( Marks: 12 ) a) What is the difference between SRAM and DRAM? b) What is FIFO? c) What is LIFO? Question No: 12 ( Marks: 10 )

a) What does sampling mean? b) Name any four performance characteristics of Digital-to-Analog Converters. c) Write name of Analog-to-Digital conversion methods

CS302 Collection of Old Papers

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