CS2100: MIPS arithmetic processing unit (Computer Organisation)

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School of Computing

CS2100: Assignment 1


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Introduction

In the course of designing an arithmetic adder/subtractor/negator, there

were several design considerations and difficulties. This document is

separated into different sections:

Creating Basic 4-bit Carry-Look-Ahead Generator (CLAG)

This portion of the document describes the process of building the basic 4-

bit Carry-Look-Ahead Generator, as well as the final Sum-of-Product terms

that have been implemented in the final design.

Creating an 8-bit Block Carry-Look-Ahead Generator (BCLAG)

The 8-bit BCLAG is composed of 3 CLAG. This portion of the document

describes the construction of the circuit that generates the carries for the

individual addition operation.


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Unit Tests

This describes inputs, as well as the desired outputs by the final circuit, aswell as the final observed outputs by the built circuit. This is used to verify

that the final built circuit works as designed, and still continues to work

under special case conditions.

Creating Basic 4-bit Carry-Look-Ahead

Generator (CLAG)

The 4-bit CLAG takes in 9 inputs. The first 8 consists of 4 sets of inputs for

the Propagate and Generate bits as derived from each sets of inputs.

The Propagate bit is defined as: A XOR B, while the Generate bit is defined

as A AND B. In a way, the output of the Propagate bit is the output of a Half

Adders Carry bit, while the Generate bit is the output of the same Half

Adders Sum bit.

The basic purpose of the Carry-Look-Ahead Generator is to decide the

carries for all the weighted positions of the each of the Carry bit without


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can be generated, the expression is duplicated and expressed in C1, such

that

C1 = G1 + P1.C0 = G1 + P1.( G0 + P0.Cin)

= G1 + P1.G0 + P1. P0.Cin

We then link the inputs directly into the AND gates directly, rather than

make use of C0 that is calculated in the previous step.

The equation is expanded for the other Carry.

C2 = G2 + P2.C1 = G2 + P2(G1 + P1.G0 + P1. P0.Cin)

= G2 + P2.G1 + P2. P1.G0 + P2.P1. P0.Cin

The last 2 outputs are used in the block level CLAG in order to pass on the

accumulated signals from the first 4 sets of P and G inputs.

G* = G3 + P3.C2 = G3 + P3(G2 + P2G1 + P2. P1.G0 + P2.P1. P0.Cin)

= G3 + P3.G2 + P3.P2G1 + P3.P2. P1.G0 + P3.P2.P1. P0.Cin

To enable the propagation of the current truth values obtained through the

i t i thi CLAG t th CLAG ( hi h ld b h i d) thi CLAG ill


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Creating an 8-bit Block Carry-Look-Ahead

Generator (BCLAG)

As noticed in designing the CLAG, it is discovered that the later carries

require the use of more logic gates, hence there is a need to put more than

1 CLAG together to generate carries for an 8-bit addition operation.

The initial design simply chains the output of the P* and G* from the first

CLAG to the input of the 2nd

CLAG, and then, the P* and G* from the 2nd

CLAG to the 3rd

CLAG, however that kind of design re-introduces the delay

associated with having to wait for the previous carry to be calculated before

the next carry can be generated.

Although the problem is on a smaller scale versus using a Ripple Carry, it

defeats the original purpose of utilizing a Carry-Look-Ahead design for the

adder; However, from the design of the CLAG, it can be seen that the P*

and G* aggregates the P and G terms for all the inputs respectively, so the

solution is to chain the P* and G* output of 2 different CLAGs to a block-

level CLAG.

The first 2 CLAGs would have the various inputs from the various P and G

i hil h P* d G* f h 2 CLAG h i d P d G i


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having to wait for the lesser binary positions to be calculated before being

finalized.

The design for the zero indicator (Z) is simple: all the weighted positions of

the output R are connected to a NOR gate, such that if any of the weighted

positions are in the 1 position, the output of the NOR gate will be 0. In

effect, the zero indicator is 1 if and only if all the weighted positions are 0.

The error indicator (O) is simply the XOR of the carry-in of the most

significant binary position, with the carry-out of that position. This meansthat when the carry-in does not match the carry-out, the output of the

XOR gate indicates a 1, and thus flags the overflow. This matches the

definition for detecting overflows in 2s-complement addition.

The negative indicator (N) is directly connected to the most significant

binary position of the output, R. The design is premised upon the fact that

the circuit will be doing 2s-complement addition/subtraction/negation, andin this numbering scheme, any binary number with its most significant

binary position set as 1 refers to a negative number.

However, it must be noted that the circuit can still be used for unsigned

operations in binary: the adder still works, with a possible value range of 0

to 255. In this situation, the negative flag should be ignored, as the circuit is

showing the result of unsigned operation. Notice that overflow detection


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The reason for this design is that part C would require the combined

Adder/Subtractor/Negator to be able to do subtraction when E = 1.

The input bits of Q are modified, such that they go through a XOR gate

before they are input to the adder. Each of the XOR gates for each bit is

linked to the S bit, such that when the S-bit is active, any input bit is

inverted. If the input is 1, the output from the XOR gate becomes 0, in

effect, creating a 1s-complement of Q.

This complemented result is then input as the second set of 8-bit input forthe adder. This, together with adding the output of S as the input of the

adder, create a 2-s complement subtracting capable circuit.

The C bit is modified, with an AND gate. The inputs of the gate are the

original C bit from the adder, as well as the negated output of E OR S. This

allows the C bit to work normally for addition operation, while showing 0

for subtraction operation.

There is no need to modify all other the output flags, as it has already been

set-up to handle 2-s complement operations.

Adapting circuit in Question B to provide

i i


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1, regardless from E = 1, or S = 1, the input bits of Q are flipped, and the

carry-in bit for the adder is set to 1.

Thus, this design works for both subtraction, as well as negation.


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Unit Tests

This section describes some of the test cases that would test the proper functioning of the combined Adder/Subtractor/Negator.

To prove compliance with the requirements, all test cases must be passed.

Note that all numbers in brackets are in decimal. P, Q and R are in binary 2s-complements.

Question Input Bits Output Bits Circuit

Matches

Output?

Test Remarks

E S P Q O Z C N R

A.1 - - 00000000 (0) 00000000 (0) 0 1 0 0 00000000 (0) Yes Testing zero

A.2 - - 00000001 (1) 00000001 (1) 0 0 0 0 00000010 (2) Yes Addition test

A.3 - - 10000000 (-128) 00000000 (0) 0 0 0 1 10000000 (-128) Yes Test detection of negative

A.4 - - 10000000 (-128) 00000001 (1) 0 0 0 1 10000001 (-127) Yes Test addition of 1 to most

negative numberA.5 - - 10000000 (-128) 11111111 (-1) 1 0 1 0 01111111 (127) Yes Test negative overflow

A.6 - - 01111111 (127) 00000001 (1) 1 0 0 1 10000000 (-128) Yes Test positive overflow

A.7 - - 11111111 (-1) 00000001 (1) 0 1 1 0 00000000 (0) Yes -1 + 1 = 0 test

A.8 - - 01000000 (64) 00111111 (63) 0 0 0 0 01111111 (127) Yes Test addition of 2 numbers

to reach most positive

number

B.1 0 0 00000000 (0) 00000000 (0) 0 1 0 0 00000000 (0) Yes Testing zero

B.2 0 1 00000000 (0) 00000000 (0) 0 1 0 0 00000000 (0) Yes Testing zero in subtract

operation

B.3 0 0 00000001 (1) 00000001 (1) 0 0 0 0 00000010 (2) Yes Addition test

B.4 0 1 00000001 (1) 00000001 (1) 0 1 0 0 00000000 (0) Yes Subtraction testB.5 0 1 10000000 (-128) 00000000 (0) 0 0 0 1 10000000 (-128) Yes Test subtract 0 from most

negative number

B.6 0 1 00000000 (0) 10000000 (-128) 1 0 0 1 10000000 (-128) Yes Test negating most

negative number

B.7 0 1 00001111 (15) 11110000 (-16) 0 0 0 0 00011111 (31) Yes Addition with negative


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number

C.1 1 0 10111111 (-65) 01111111 (127) 0 0 0 1 10000001 (-127) Yes Test activation of negating

Q

C.2 1 1 10111111 (-65) 01111111 (127) 0 0 0 1 10000001 (-127) Yes Test non-interference by S

bit

CS2100: MIPS arithmetic processing unit (Computer Organisation)

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