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CS139 LECTURE NOTES.PART I

SECTIONS 1THRU 21

PRELIMINARY VERSION

BY

J. EHRMAN

1. INTRODUCTION

These notes are meant to provide an introduction to System/360 which

will help the reader to understand and to make effective use of the

capabilities of both the machinery and some of its associated service

programs. They are largely self-contained, and in general the reader should

need to make only occasional reference to the "System/360 Principles of

Operation" manual (IRM File No. ~360-01, Form A22-6821), and to the

"Operating System/360 Assembler Language" manual (IB4 File No. ~360-21,

Fom ~28;6514).

A digital computer can be considered from a variety of viewpoints; for

convenience we will mention five possible ones, each of which treats the

inner workings of the computer in successively less detail. To an engineer

concerned with the design of its logical circuits, a computer might be

considered basically a collection of devices for controlling and ordering

the flow of electrical impulses. At another level a person concerned with

methods to be used to make these logical circuits perform certain operation8

such as division might treat a computer as a collection of registers, switches,

and control mechanisms which, when provided with the appropriate data, are

to perform a series of steps leading eventually to the computation of a

quotient. At the next level one might consider the basic operations of a ccmputer

to be those operations which perform a single arithmetic operation, a

simple data movement, or a test of a single piece of data. Another viewpoint

(typical of "higher-level languages" such as FORTRAN, ALGOL, and PL/l)

is to consider that the basic operations of interest are the movement of

blocks of data, the evaluation and assignment of mathematical expressions,

and the control of counting and testing operations. At yet another level,

as in certain applications such as traffic or production simulation, data

reduction, and network analysis, the computer is considered as a device

which accepts information in a form which closely approximates that of the

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problem under consideration, an4 produces output directly applicable to

that problem.

Each of these ways of viewing P computer is of course not especially

distinct from its neighbors. In thirr treatment we will be primarily coneem

with the middle level, namely that of considering the basic operations, or

instructions, that we want the computer to perform to be elngle arithmetic

or logical operation*, simple data trannaission operations,. etc. We will

fran time to time have occasion to conrider the canputer fran %eighboring"

viewpoints: in some circumstances it will be useful to know some details of

the internal sequenaing of operations euuh as multiplication and division;

at other times it will be convenient to consider instructions to the machine

which will perform operations in a larger context than that ordinarily

considered.

This level of programming which will be our primary concern is usually

known as "machine language" programming; however, since the process of .

actually getting the desired instructions into the canputer requires the

aid of a number of other programs, the first of which is called an assembler,

the teas "assembler lanmgefl'programming or "assembler coding" are also

used. Thus the service program of most concern will be the Operating

System/360 Assembler; other grograms of interest will be the Linkage Editor

and the Resident Supervisor, each of which will be considered in the

appropriate context.

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2. BINARY AND HEXADECIMAL NUMBERS

System/360, like most other digital computers, makes heavy use of

binary numbers for internal arithmetic. Because digits in a base two

representation can take on only the values 0 and 1, it is relatively simple

to build a mechanical or electrical device which represents the digit. For

example, a 1 digit may be represented by the presence or absence of a

current through a given circuit component or by the presence of a positive

or negative voltage at some point. Because facility with the use of binary

numbers is fundamental to an understanding of-the basic operation of

System/36O, it is useful to summarize the properties of the binary number

representation. For the time being, all numbers will be assumed to be integers.

In base ten, when we write a number such as 1735 we mean the quantity

That is, each digit position as we move to the left is weighted by another

power of the base, ten. SimilarQr, when in binary arithmetiq we write the

number 11010 we mean

which of course is not the same as what is meant by the decimal number

11010, where powers of ten are understood. In fact, the binary number 11010

is the representation (in the number system with base two) of the decimal

number 26, tihich is obtained simply by performing the sum in the above

example.

To clarify which base is intended when we write numbers, it will be

convenient to attach a "subscript" at the right end of the number to

indicate the base being used:

2610 = 110102, 110 = 12,

1010 = 10102, 10002 = 810.

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As the decimal numbers being represented become larger, the number of

binary digits required becomes larger also.

Thus,99910 = 11111001112.

It is therefore convenient to find a more compact notation for binary

numbers. If we consider groups of four binary digits at a time, the possible

decimal values that can be represented run fran zero to fifteen, If we then

choose to represent each of these groups by the digits 0, 1, 2, 3, 4, 5, 6,

7, 8, 9, A, B, C, D, E, I?, we can establish the following table of correspondences:

Binary Digits Decimal Value Base 16 Digit

0000 0 0

0001 1 1

0010 2 2

0011 3 3

0100 4 4

0101 5 5

0110 6 6

0111 7 7

1000 8 8

1001 9 9

1010 10 A

1011 11 B

1100 12 C

1101 13 D

1110 14 E

1111 15 F

TABLE I.

Hexadecimal, Decimal, and Binary Digits

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We will call the base sixteen digits in the third column hexadecimal

digits, and will generally use them in situations when we have occasion to

refer to binary numbers. As before, a "subscript'" of 16 will be used to

indicate that the given set of digits is to be understood to have base 16:

2610 = 110102 = l&6,, 2616.= lCOl102 = 3810, llo = l2 = 116,

1010 = 10102 = Ale, 100~ = 810 = 816, 10010 = 6416 = 11001002.

Converting numbers between binary and hexadecimal representations can

be seen to be quite simple: to convert a hexadecimal number to binary,

simply substitute for each hexadecimal digit the four binary digits it

represents; to convert a binary number to hexadecimal, group the binary digits

four at a time starting from the right, and substitute the corresponding

hexadecimal digit. For example:

DSSJ316 = 1101 0101 10112, (hexadecimal to binary)

11 1110 1002 = 3E816. (binary to hexadecimal)

In the second of these examples it was assumed that two extra binary

zero digits could be added at the left end of the number without affecting

its value; thus we can write

1116 = 100012 rather than 0001 00012.

Conversion between decimal and hexadecimal representations is somewhat

more cumbersome, but if a conversion table such as the one in the Appendix

is not available, the following method is usually sufficient for hand

calculation.

In the positional notation we are accustomed to using, a string of

digits dn dn 1 . . . d2 dl do is the representation in some base D of the

number X:

n

X =c

dkDk = doDo + dlD1 + d2D2 + . . . + dnDn .

k=O

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Suppose we want to cam& from thir representHAm &I bare D to the

representation in a new baod!lt

x=r

bkRk = boB" + b& +b& + ..:+ bmp b

k=O

The known quantities are tha c&a and new basee D and Br aa the digits dk ~

of the ol.d representation; then, to find the digits bk in tbs new representation,

the following scheme is u&I.

Divide X by B; save the quotient, end the remainUer 19 &I. That this

is so can be seen frau the defin'ition of the quotient end rsomalnder:

X = Remainder + BX Quotient = bo + Bx [bl + b2B + bs2 + . . . + bmRm=']'.

Divide the saved quotient by B; save the new quotient, and the new remainderis bl. Continue this process until a zero quotient is obtained, and the

successive remainders are the digits bo, bl, . . . bm; note that they were

obtained in order of increasin. significance.

1. Convert 1910 to base 2.

4 2 1 0ar 2JF- m m

18 8 4boy - - 2 0bl =l b2=0 bs=O bra1

Hence, 1%0 = 100112.

2. Convert 1000~0 to base 16. (Note that the conversion aritbetic is

done in base 10.)

6216JJ

-%-bo =

3 0IQ=- lG3-

48 0bl =For El6 b2 *T

Hence 1ooOlo = 33816.

3.

4.

Convert 6271~ to base ye

bo=

7YE-

63 0bl =6 ba =T

SO that 62710 = 7669.

Convert 7669 to base 7. (This is simple once you've memorized the

multiplication table in base 9, which is the base used for the

conversion arithmetic.)

108 13 1?m-- ?T=- Tm--

7627+

103 0box bl = 5 b2 7 = 5 bl, = 1

Thus 7669 = 1554,.

This can be done in more roundabout (but comprehensible) fashion by

converting to base ten first and then doing the arithmetic in decimal,:

?669 = 7 x 81 + 6 x y + 6 = 567 + 54 -t 6 = 627Lo

89 l2mm-- ?m-

623 84bo= bl = 5

?&- 7%

b2 7 =0

5 b3 = - 1

So that 7669 = 15547 again.

Convert 14135 to base 10. This is most simply done by expanding the

positPona1 notation:

14135 =lxl25+4x25+1~5+3=233~~.

Alternatively, using the fact that 1010 = 205 in base 5 arithmetic,

4320--

130113110

bo = 3

2

206-

40

bl = 3

20$-

0

b2 = 2

giving 14135 = 23310.

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6. Convert 33816 to base 10. In this case it Ys usually simplest to use

the positional notation used earlier:

3~81~ = 3 x 16* + 14 x 16l + 8 x 165

and then this sum can be evaluated in decimal. Thus we find

33816 = 3~256+14~16+8=768+224+8=looo~~~.

This type of conversion is considerably simpllfied by the use of the

table of multiples of powers of ~6 in Table II or (for small numbers)

by the use of the conversion table.

Discussion of binary arithmetic -- addition, subtraction, multipli-

cation, and division -- will be deferred until later.

We will use several abbreviations regularly: a bit will mean a

binary digit, and we will use hex as short for hexadezal.

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Iv

4

<inlCi - ’ ~16~ ~16~ x164 x165 xl66 xl671

2

3

4

5

6

7

8

9

A

B

C

D

E

F

1 16 256 4,096

2 32 512 8,192

3 48 ?a 12,288

4 64 m24 16,384

5 80 1280 20,480

6 96 ' 1536 24,576

7 ll2 1792 28,672

8 128 2048 32,768

9 144 2304 36,864

10 160 2560 40,960

11 176 2816 45,056

12 192 3072 49,152

13 208 3328 53,248

14 224 3584 57,344

15 &o 3840 61,440

65,536

131,072

196,608

262,144

327,680

393,216

458,752

524,288

589,824

655,360

720,896

786,432

851,968

917,504

983,040

1,048,5?6

2,09?,152

3,145,?28

4,194,3o4

5,242,88o

6,291,456

7,34o,o32

8,388,608

9,43?,184

10,485,760

11,534,336

12,582,9=

&631,488

14,680,064

15,728,640

16,777,216 268,435,456

33,554,432 536,870,9=

50,331,648 805,306,368

67~08,864 1,0?3,?41,824

83,886,080 1,342,1??,280

100,663,296 1,610,6~,736

117,440,5l2 1,8?9,o48,192

134,21?,728 2,14?,483,648

150,994,944 2,415,YlY,lo4

167~72,160 2,684,354,56o

184,549,376 2,952,?9o,o16

201,326,592 3,221,225,472

218~03,808 3,489,660,928

234,881,024 3,758,096,384

251,658,240 4,026,531,840

TABLE II.

Multiples of Powers of 16

39 STRUCTURE OF SYSTEM/360

It is usual to describe the structure of most digital computers in

terms of four major components: memory, arithmetic, control, and input-

output units. It should be understood that an actual machine may not

have components which can be separately identified in this way, but that

for conceptual purposes it is possible to think of them as distinct units.

h Memoryc

Unit -

t-Arithmetic Input-Output

Unit Instructions Unit6

kI‘\

Figure 3.1 Structure of a Typical Computer

The solid arrows in the figure represent schematically the possible paths

of data flow among the various units, and the dashed arrows indicate the

flow of control signals. As indicated, the instructions for the control

unit are contained in the same memory as the data used by the arithmetic and

input-output units; this property is what gives modern digital computers

their flexibility and power -- the computer can, on the basis of certain

computed results, modify the instruction sequences which control the way it

will treat other data.

In-the System/360 computers many of the functions performed by the

control and arithmetic units use the same internal components, so that it

is easier to make no special distinction between the two and simply call

the combination the Central Processing Unit, or CPU.

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Memory <Unit .

Instructionsand Data

Jf

CPU,

Input-OutputUnit

.9

Figure 3.2 Structure of System/360

' These units will be described in varying detail: the memory and

arithmetic unit are of major concern to the machine language programmer;

certain features of the control unit will be examined closely while others

will be ignored for the time being; the input-output unit, which is simply

a term which collectively denotes devices such as card readers, printers,

magnetic tape units, etc., will be described only as necessary to make use

_ of the cunputer in certain elementary ways.

The terminology introduced here is by no means fixed in the literature

and everyday usage of the computing profession. For example, it is common

to refer to magnetic drums as memory devices even though they are accessed

through whatwe have called the Input-Output Unit. What we will call

"memory" can be more accurately described by calling it the High-Speed

Randam Access Magnetic Core Memory, but the economy of a single term is

apparent.

Memory

The basic unit of data in System/360 is a group of eight bits called

a byte. The bits in a byte are by custom numbered from 0 to 7, beginning

on the left with the numerically most significant digit. The definition

of the "left" side of a byte will become clear shortly.

. 1 . +

1 1 0 1 0 0 1 0. t0 1 2 3 4 5 6 7 '

Figure 3.3 A byte containing the 8 binary digits 11010010

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The memory unit is arranged so that it will hold a certain number of bytes

in such a way that each byte may be accessed as rapidly as any other. The

bytes may be considered to be individually numbered in order, beginning at

zero; the number associated with each byte is its address or location in

the memory unit. The memory may be thought of as a linear string of bytes

arranged in order of increasing addresses.

6address

. . . 701 702 703 704 705 706 707 708 709 . . .

\byte byte byte byte byte byte byte

1byte byte

Figure 3.4 A portion of memory

Many of the machine instructions which refer to bytes 'in memory"

(which is an abbreviation for 'in the memory unit") actually refer to a

group of consecutive bytes. In such a situation the group, or "operand",

is always addressed by referring to its leftmost member, namely the byte

with the lowest address in the group. Furthermore, certain instructions

require that the address of a group of bytes (which, as stated, is the

address of the leftmost byte) also be a multiple of the length of the

group: the possible values for these instructions are 2, 4, or 8, and in

such cases it is usual to refer to the groups of bytes whose addresses and

lengths satisfy this condition as half'word, fullword, and doubleword data,

respectively.

837 8~8 8129 8~ DEB ~EC 8ED 8~1s 8EF 8~0 8~1 8~2 8~3

~halfword+~+half'word+~thalfword+ Ithalfword-t[+-halfword-t(thal%ord-,I

I t fullword 3 I t fullword +I

t fullword 3

II

t doubleword 4 I

Figure 3.5 A portion of memory

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Note that if (for example) a half'word operand (that is, a group of

two bytes whose address is divisible by 2) were specified for sane operation,

and the address of that 160bit operand were 8EA16, then bit 0 of the byte

at 8~~x6 would be considered to follow immediately after bit 7 of the byte

at 8~~16. It is in this sense that bit 0 is taken to be the 'leftmost'

bit of a byte: it follows (for certain operations) immediately after bit 7

of the byte at the next lower memory address.

The data contained in bytes or groups of bytes in memo&can be

manipulated in many different ways, depending on the intentions of the

programmer. These will be discussed later.

Central Processing Unit

There are three things in the Cpci of interest to the programmer: the

general purpose registers, the floating-point registers, and the Program

Status Word. There are sixteen general purpose (or simply general) registers,

numbered frcxn zero to fifteen, each one of them being 32 bits (or 8 hex

_ digits or 4 bytes or 1 fullword) in length. They are represented schematically

.in the figure below.

E 32 bits numbered 0 to 31

0 31

Figure 3.6 A‘Single General Purpose Register

tRO . Rl

Ii2 R 3R4 R5

R6 R7

R8 R9

RlO Rll

Rl.2 R13R14 R15

Figure 3.7 General Purpose Registers

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Figure 3.7 is arranged with the registers in pairs, the left being

an even-numbered register and the right being the next higher odd-nunibered

register. This is because certain of the machine operations (such as

shifting, multiplication, and division) require the use of a pair of

registers, and in such cases it is always such an even-odd numbered pair.

We will have many occasions to refer to the general registers, so that it

is convenient to introduce a short notation: we will write Rn to refer to

general register n, so that RO means register 0, R14 means register 14,

and so on.

The presence of floating-point registers in the CPU is an option for

certain models, but we will assume that the user of the machine we are

discussing writes his programs for a computer that includes the floating-

point feature. There are four floating-point registers, each 64 bits (or

16 hex digits or 8 bytes or 1 doubleword) in length. They are numbered

0, 2, 4, and 6.

t 64 bits -3

I IFO

c F2

I F4 I

I0

F6

Figure 3.8 Floating-Point Registers

In certain circumstances the floating-point registers are used to

contain operands 32 bits long, in which-case they use only the left half of

the register, and the rightmost 32 bits of the registers are ignored; this

will be discussed in the chapter on floating-point arithmetic. As in the

figure above we will use the abbreviations FO, F2, F4, and F6 to refer to

the four floating-point registers.

In many cases it will be easier to use the term "register" for either

a general purpose register or a floating-point register; which is meant

will be clear from the context of the discussion.

The Program Status Word (or PSW for short) is not of direct concern in

most programming applications, so that we need not be concerned at present

with examining it in detail. The PSW is a double-word (and hence it is

actually a Program Status Doubleword, but nobody really cares about the

difference) which indicates in a compact form certain important details of

the operation of a program in the System/360 CRJ.

System Mask Interruption Code0 78 11 I2 15 16 31

YrogramMask Instruction Address

34 36 40I

32 33 35 39 63

Figure 3.9 Program Status Word

The various pieces of the FSW (which resides in the CPU, not in memory,

and is therefore pretty much inaccessible) will be explained in various

contexts later. For the present, however, the items of interest lie in the

rightmost 32 bits: the portions denoted "IX" (Instruction Length Code),"CC" (Condition Code), and "Instruction Address" (which we will abbreviate

"IA") are the parts of the ESW which will be treated in most detail. The

Condition Code indicates the result of certain operations (e.g., that a sum

is negative) and the two bits of the CC can be tested by certain instructions.

This right-hand portion of the PSW will be of more interest than the first

32 bits for most of the following discussion; the ILC and IA will be dis-

cussed in the next section. -The reader is cautioned that there will be

omissions in the discussion of the I?% until the treatment of interruptions,

where the subject will be covered in greater detail.

Input-Output

The process of data transmission between the memory and external devices

such as card readers, printers, card punches, magnetic tapes, magnetic drums,

disc files, etc., is handled in System/360 by channels. These are capable of

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transmitting bytes of data in such a way that the CPU can continue with the

execution of a processing program at the same time that the channel is

moving information to or from a different area of memory. The problems

involved in synchronizing the transmission of such data with its use by

the processing program in the CPU are quite complex and will be avoided for

the time being, but will be touched upon later during the discussion of

interruptions.

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4. INSTRUCTIONS (I)

As was indicated in the diagrams of the "structure" of a computer in

the previous section (Figs. 3.1 and j.Z?), the instructions obeyed by the

computer are held in memory along with the data to be processed. Instruc!ti0ns

in System/360 can be 2, 4, or 6 bytes long, depending on what the placement

of the data to be operated on happens to be, and on what the instruction

causes to be done with the data. Instructions are always aligned so that

the leftmost byte is on a halfword boundary:- that is, an instruction

address must always be divisible by two. Otherwise, it doesn't matter, for

instance, that a b-byte instruction begins halfway between two fullword

boundaries.

The actual process of performing the instructions in a program may be

visualized as in the following figure.

Figure 4.1 Instruction Cycle

In the "Fetch" portion of the cycle, the CPU causes the instruction

in memory which begins at the byte whose address is contained in the rightmost

24 bits of-the PSW (the Instruction Address or IA) to be brought into the

CPU and placed in an internal holding register where it may be examined.

Though this internal register is not accessible to the programmer, we will

from time to time make reference to it, so we will simply call it the

Instruction Register, or IR for short. There is a simple way for the CPU

circuits to know the length of an instruction and therefore how many bytes

to bring from memory; this will be explained at the end of this section.

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To complete the Fetch portion of the cycle, the Cl3 adds the length in bytes

of the instruction now in the instruction register to the IA in the PEW, so

that it will contain the address of the next instruction to be fetched when

the current instruction has completed its execution. This means of course

that instructions are packed tightly in memory; there are no leftover bytes

between instructions.

To decode the instruction, the CPU examines the bit pattern of the bytes

in the IR to see what action is intended. Since (1) the bytes were brought

from memory and (2) the memory contains both data and instructions, it is

quite possible that the bytes brought to the IR were intended by the programmer

to represent data and not instructions. -The CRJ, however, has no way of

knowing this in advance; it simply goes to the memory address given in the

IA portion of the PSW and puts those bytes into the IR to be interpreted as

an instruction. If this is what was intended, well and good (remember that

in the beginning of Section 3 it was noted that the ability to treat instruc-

tions as data is what gives a computer its power); otherwise strange things

can occur. Because not all of-the possible bit patterns in the IR represent

"legal" instructions (i.e., actions the CPU can actually perform), the

decoding mechanism can occasionally detect a confused situation before too

much damage has been done, and cause the appropriate remedial actions to be

Initiated. '

Assuming that the bytes in the IR do indeed contain a valid instruction,

some further actions may be necessary before the decoding is completed, such

as the calculation of addresses of data to be operated on during the "Becute"

portion of the cycle.

It is during this final‘execution phase that the actual operation is

performed. The operation may be a simple one which could, for example,

cause the contents of one general register to replace the contents of

another, or it may involve many intermediate steps of complicated logic or

arithmetic. If no errors are detected during the execution phase (such as

attempting to divide seething by zero), the CPU then begins the cycle again

by returning to the "fetch" portion of the cycle. It should be noted that

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the time required for all this is very small even for a relatively slow

computer: the entire cycle takes only millionths of a second, so that with

this tremendous rapidity it is possible to perform calculations far too

laborious to be done by hand.

The instructions which can be executed by the System/360 CPU can be

grouped into five general classes:

1) Register-to-Register (RR),

2) Register to Indexed Storage (RX),

3) Register-to-Storage (RS),

4) Storage-Immediate (SI),

5) Storage-to-Storage (SS).

The letters RR, RX, RS, SI, and SS are abbreviations which will be used

regularly to indicate the class of instructions being discussed; the specific

instructions belonging to each class will be treated in later chapters.

RR instructions are always two bytes long.

mRR Operation Register

Code Specification0 78 15

RX, RS, and SI instructions are always four bytes long.

Rx Operation Register AddressingCode Specification Syllable

0 78 15 16 31e

RsOperation Register Addressing

L Code Specification Syllable0 78 15 16

b31

SI Operation Immediate Addressingc - Code _ Operand Syllable0 78 31

The RX and RS instruction formats differ only in the interpretation

given by the CPU to the bits in the "Register Specification" byte.

S$ instructions are always six bytes long.

css Operation Register Addressing

CodeAddressing

Specification Syllable

0 78

Syllable15 16 31 32 47

Figure 4.2 Instruction Formats

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’

.

It can be seen that the operation code, which specifies what action

is to be performed, occupies the first byte of the instruction. The second

byte contains information necessary to the details of the execution of the

instruction; its interpretation differs for instructions in the various

classes. For all instructions except RR instructions an addressing syllable

is used by the CPU to cmpute the address of an operand in memory; this

process will be discussed in the next section.

The first two bits of the operation code contain the information which

tells the CRJ how many bytes are needed from memory to obtain the complete

instruction. Since a minimum of two bytes per instruction must always be

fetched, the CPU can check these two leading bits to tell how many more

bytes are required. The bit patterns are as shown in the figure below;

the xxxxxx is meant to indicate the remaining six bits of the eight-bit

operation code.

RR Rx RS,SI ss

Figure 4.3 Bit Patterns for Each Instruction Type

Thus if the first two bits are 00 the instruction is two bytes long;

if the bits, are 01 or 10 the instruction is four bytes long; and if the bits

are 11 the instruction is six bytes long. Before proceeding with the

decoding phase of the instruction cycle, the CRJ places the number of pairs

of bytes in the instruction in bits 32 and 33 of the PSW (namely in the

position labeled "Instruction Length Code"). If an error is detected during

the decoding or execution of the instruction, and if the PSW at the time of

the error is saved somewhere, then the programmer can determine (by

examining the IA and IX) what instruction caused the error. (This is of

course precfsely what is done; we will note for now that if the IU were

not saved, it would not be possible to determine the exact location of the

offending instruction, since the location of the next instruction to be

executed is what appears in the PSW and the length of the bad instruction is

variable. This is a subject with many ramifications, to be covered later.)

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5* ADDRESSING

To refer to items in memory such as data or instructions, the programmer

must usually make use of one of the general purpose registers. This is due

to the way the CPU uses the information in an "addressing syllable", which

always occupies a half'word in memory.

Base RegisterSpecification

-4 bits-----s, -c

Displacement

12 bits ‘s,,'.

Figure 5.1 Structure of an Addressing Syllable

The b-bit field at the left of the addressing syllable contains a single hex

digit which can take values from 0 to 15, and which specifies a general

purpose register. The 12-bit field in the rest of the addressing syllable

contains a number called the displacement which can take values from 0 to 4095.

To generate the address or‘ an operand, the CPU does the following:

Step 1) The l&bit displacement is put at the right-hand end of a

240bit internal register called the Memory Address Register

(abbreviated MAR), and the leftmost 32 bits of the MAR are

cleared to zeros;

Step 2a) If the base register specification digit is not zero, then

the rightmost 24 bits of the general purpose register

specified are added to the contents of the Memory Address

Register, and carries out the left end of the MAR are

ignored (the register used is called the base register);

Step 2b) If the base register specification digit is zero, nothing

is added to the MAR (so that RO cannot be used as a base

register).

At this point the quantity in the MAR may be used as the address of an

operand in memory. However, if the instruction is of type RX, a further

i,i! 5-l

step called an indexing cycle is needed. The second byte of an RX-type

instruction (labeled "Register Specification" in Fig. 4,2) contains two

b-bit fields, the second of which is called the index register specification:

F Op Code-+-+- 4 bits->-4 bits >-16 bits-',I-&

To be IndexOIkXXXXX Described Register Adldressing

Later Specification Syllable

.b

0 78 11 I2 15 16 31

Figure 5.2 RX Instruction Showing Index Register Specification

Step 3) If the instruction is of type RX, and the b-bit index

register specification digit is not zero, then the right-

most 24 bits of the general purpose register specified by

the index register specification digit are added (again

ignoring carries out the left end) to the contents of the MAR.

The resulting quantity in. the MAR is called the effective address.

(Binary arithmetic will be discussed in detail in Section 7. For the

following examples, it should be sufficient to note that 0 4 0 = 0;

0 + 1 = 1 + 0 = 1; 1 + 1 = 0 and carry 1. These examples go into

considerably more detail than is necessary for a working understanding of

addressing, and the arithmetic is ,included just for the sake of completeness.

Since addressing will reappear in several later places, don't worry about

absorbing all the fine points immediately.)

Examples

1. Suppose the addressing syllable of an SI-type,instruction is 011(00101101010

in binary (or b12D5( in hex)

purpose register ll,o is

1100 0111 0011 1110 1001 0000

Then the effective address of

and hex):

and suppose that the contents of general

1010 1111 in binary (or C73EgOAF in hex).

the instruction is (giving both binary

0000 oooo oooo 0010 1101 0101 0002m displacement+ 0011 1110 1001 0000 1010,11110011 1110 1001 0011 1000 01002

base (from Rll)

5-Q

2. Suppose the addressing syllable of the same instruction is 1-1.

Then the effective address is 00046816, since RO cannot be used for

a base.

39 Suppose an RX-type instruction is , and that the

contents of R7 is 12345678 16 and the contents of RlO is l?EDc~g816.

(Note that the base register specificatiok digit, namely716,

means that R7 will be used. The instru!:i;i.on chosen for this and

the next two examples would, if execu'ced "1~ the CPU, cause the

contents of the byte at the memoq lo~a+:'.orl t:i-len by the effective

address to replace the rightmost byte LX? FiO.11 Then the effective

address is

0000 0000 0000 0100 OllC 1009 OOOW3 displacement+ 0011 0100 0101 0110 0111 1009. + 245678 base (from R7j

0011 0100 0101 1010 1110 3X3 yqAE01101 1100 1011 1010 1001 lOOC! + DXA 8 index (from RN)

+ 0001 0001 0001 0101 01~1 ail_;, 11157 -53 15 efl'ective address

(The carry out the left end IS ignored.)

4. Suppose an RX-type instruction is iFJ=EJ and t&t the contents

of register 7 is as in example 3. Yflt 3 the c;'fc&ive address is

0000 0000 0000 0100 0110 1000 ~00468 displaceme2n-L+ 0011 0100 0101 0110 0111 1000

0011 0100 0101 1010 1110 00002+ Q-j670 -+--. base

345AE:( ‘=X-y efft?ctive address

5* Suppose an RX-type instruction is and that the contents

of register 7 is as in example 3.

0000 0000 0000 0100 0110 1000+ 0000 0000 0000 0000 0000 0000

0000 0000 0000 0100 0110 1000+ 0011 0100 0101 0110 0111 1000-0011 0100 0101 1010 1110 00002

Then the effective address is

000468 displacementi- 000000 base55tzGJ

+ 345678 index-16 effective address

In this example the values of the base and index register specification

digits were interchanged from those in example 4, so that the indexing

cycle was required in example 5 to compute the same effective address.

Or-the smaller models (30, 40, and 50) of the System/360 series, extra

time is required to perform this additional arithmetic, so that in

some cases it may be worth trying to avoid unnecessary indexing cycles.

5-3

In a situation where only one register is used in the calculation of

the effective address (as above, where the base register specification

digit was 0 and the index register specification digit was 7) it is

customary to speak of that register as the base register, even though

it may be the index register in an RX-type instruction. This allows

us to refer to this addressing scheme as a base-displacement addressing

technique.

The effective address in the MAR can have a number of uses, the

primary one being to address operands in memory; it is also used f6r shifting

and branching (which will be discussed later). However, three further

observations may be made about effective addresses which will be used to

refer to data in memory.

First, the presence of 24 bits in the MAR means that a System/360

computer has the capability of addressing 224 or 16,777,216 bytes. Now it

will almost always be the case that the model being used will have a

smaller memory, since memory is one of the more expensive parts of the

computer. Thus, suppose (for example) we are programming for a machine with

- 2= = 1000016 = 6553610 bytes of memory, and use an instruction which

generates an effective memory address-which is larger than lOOOOi6. Since

this effective address cannot refer to anything accessible to the CPU, some

sort of error-recovery procedure must be initiated; this error condition is

known as an addressing exception, and causes a program interruption to

begin the error-handling sequence.

Second, it was noted in the earlier discussion of the memory that

certain instructions which operate on groups of bytes such as fullwords

require that the address of the leftmost byte be divisible by the length

(in bytes) of the operand. -If this condition is not satisfied, another

error condition known as a specification exception is recognized. For

example, the RX-type instruction specifies that a f'ullword

operand is to be transmitted frcm memory and placed in R4. Since the

effective address for this case is 000=316, the proper (i.e., leftmost)

byte of the fullword is not being addressed, so that a specification

exception is recognized during the execute portion of the instruction cycle,

and a program interruption will initiate the error-recovery sequence.

5-4

Third, because the only part of the memory which can be referred to

without the use of a base register is the area with addresses 0 to 40951o=Fl?FL6,

the programmer will almost invariably be required to refer to operands in

memory with the help of a base register. (One might think that he need

only fit his program into those first 4096 bytes and then not have to worry

about all this base-register trouble, but that area of memory and more will

usually be occupied by the routines which provide error handling, input-

output operations, and the like; it's called "The System". So we just have

to live with it.) This means that if we are to address a byte in memory

at address Q, there must be a base register available (that is, one of

registers 1 to 15) which contains a number between Q and Q-4095, since we

could then generate an effective address of Q by using a displacement

between 0 and 4095. If there is no such number in a register, then the

byte at Q is not addressable. Thus, if all the general registers contain

zero, only the first 4~6 bytes of memory are addressable! Usually what

must be done is to place some constant in a register which then allows us

to address the desired regionof memory; that is, that register then provides

addressability for that region. However, if the constant itself is in

another portion of memory which is not currently addressable, we are back

to where we started, needing another constant to address the first constant.

In fact, it is possible for the CPU to be executing instructions in a

portion of memory, and the instructions cannot address themselves!

(Remember that the IA is in the PEW, not in a register.) Fortunately,

there are simple solutions to the problems of addressing, and these will

be the subject of several later discussions.

5-5

6. TWO'S COMP~ REPREE33NTATION

Up to now we have discussed the binary representation only for positive

numbers, in which it was implicit that any positive integer may be preceded

by an arbitrarily long string of zero digits, which are then ignored. The

representation of negative numbers requires further consideration. To use

a practical case, we will illustrate the discussion by using whole numbers

of length 32 bits, corresponding to the length of a fullword in memory and

of a general register.

To begin with, suppose all of the binary digits of the number being

examined are taken to be the rightmost 32 bits of any positive integer.

Then

0 is represented by 00000000~6~

1 is represented by 0000000116,

130 is represented by 00000082~6,

231 is represented by 80000000~~,

232-l is represented by Fl?Fl?Fl?mle,

232+1 is represented by 000000011~~

Thus, if the number is less than 232 its value

in the 32 bits we have made available, and if it is1Q

and so on.

can be correctly held

greater than or equal toAC

2 > some significant bits are lost off the left end. (That is, the value

of the number is represented modulo 232 .) There are machine instructions

which allow the CPU to perform addition and subtraction with operands of

this form; -such arithmetic (modulo 232) is called logical arithmetic.

Hence we call this the logical representation of binary numbers, where all

the bits of the operand are interpreted as having "positive weight". (A

"negative weight" for a digit will appear later in discussing negative

numbers.)- That is, if the 32 bits are (from right to left; note that this

temporary scheme is the reverse of the numbering convention introduced

earlier) bo, bl, . . . b3o, b31, then the value X represented by the digits

bi is31

X = . bi2i.c

(logical representation)

i=O

6-1

This representation ie the most c-on way to interpret a string of bits.

There are several representations used for numbers which can assume both

positive and negative values, the most c-on of which are the sign-magnitude,

one's complement, and two's complement represent&&ions. Since the last of

these representations is used for most integer arithmetic in System/36O,

we will investigate its properties in detail. Actual arithmetic using

binary numbers will be covered in subsequent sections.

The two's complement representation (the name will be explained shortly)

of a positive integer x is (if x satisfies 0 2 x <, 231-l) simply the usual

binary representation with the least significant digit at the right-hand

end; *and is the same as the logical representation. The upper limit of

231-1 is chosen because it is the largest-integer which can be represented

using 31 binary digits; the remaining 32nd digit at the left-hand end is

zero, and will be used for the sign digit. The two's complement representation

of a negative integer x which satisfies -2'l I; x S -1 is the following:

the leftmost bit is now set to 1 to indicate that the number is negative,

-. and the remaining 31 bits are aet to the binary representation of the

positive integer 231 + x, which satisfies 0 s 231 + x L; 231-1. In effect.we have done the following: if xi~ positive, the sum Cbi2?gives the

value of x, because the leftmost bit, being zero, does not contribute to

the SW. If x is negative, the sum of the rightmost 31 bits is 2'l + x and

g the leftmoslt bit is always a one, so that we can canbine these to obtain

30

X’ -2'lb31 +c

bi 2' . (2's complement)

i=O

This forsula is almost the same as that used for the logical representation

except that the leftmost bit (b& contributes negatively to the sum --

that is, has "negative weight". We will occasionally call the two's

cmplement representation, where positive and negative numbers are allowed,

the arithmetic regreaentation.'

The re16tioMhip between the logical and -fi~ob complement representation

is quite simple, which may be seen by rewriting the above sum for X:

30

X = +231b31 +c

biPi b

i=O

6-2

If b31 is zero, the logical and two's complement representations give the31same value, and x = X. If b3i is one, then X = x + 2 X 2 = x + 232.

But because we can only represent numbers less than 232 in the logical

representation, x + 232 for positive x is the same as X, with the extra bit

being lost. Thus, for 0 <, X 5 232-1 and -231 5 x L; 231-1, we have

X = 232 + x (modulo 232).

(The above equation is the original source of the term 'two's ccmplement".

In the earliest computers it was customary to treat such fixed-point

numbers as fractions -- the representation was the same as the one just

deseribed, except that the "binary point" (the binary equivalent of the

decimal point) was assumed to lie just to the right of the sign bit rather

than at the right-hand end of the number. The equation giving the relationship

between logical and arithmetic representations was then written X = 2 + x,

so that the representation of a negative number was obtained by finding its

complement with respect to two.)

The actual calculation of the binary two's complement representation

of a negative number can be sdewhat cumberscme. If the previous rule is

followed, we must calculate the binary representation of the positive

quantity 231 + x for some negative x, and the conversion can be tedious.

It turns out, however, that getting 231 + x by calculating (231 - 1 + x) + 1

is relatively simple, because the representation of 231-1 is 31 one-bits.

Since x is negative, 231-1 + x = 231-1 -lx!. Thus the magnitude of x is

subtracted from a string of 31 ones. But wherever 1x1 has a one bit, the

resulting difference bit will be 0, and vice versa. Thus the subtraction

need not be done: simply change each bit into its opposite (namely the

result of subtracting it from l), and we have 23L-1 - 1x1. (The result

is called the one's complement of 1x1.) Then add 1 in the rightmost

position to get 231 + x, set the leftmost bit to 1, and there it is. And

since Ix.1 when treated as a 32-bit number always has a leading zero digit,

we can include the treatment of the sign bit in the following two-step

prescription.

Given Y: find the two's canplement representation of -Y.

1) Take the one's complement of Y (change all 0 digita to 1 and

all 1 digits to 0).

2) Add a 1 digit in the low-order (rightmost) position, and

ignore carries out of the leftmost position.

To illustrate this process, consider the following two examples in

which the arithmetic is done with eight binary digits for the sake of

simplicity.

1. Find the two's complement representation of -2.

1) Representation of t2: oooo 00102

2) One's Ccplplement: 1111 1101

3) Add one: +l

1111 11102

2. Find the two's ccrmplement of -tn.

1) Representation of +n: CO10 lOlla

2) One's Complement: 1101 0100

3) Add one: +l

1101 01012

The above prescription also works in the opposite direction, which

can be seen from the following example.

Find the 8-bit two's complement of 1111 11102.

1) One '8 Complement: 0000 OCKU

2) Add one: +l

0000 CO102

which is the binary representation of +2. Thus the two's canplement of the

two's complement of a number is the original number.

There are two unusual cases which arise in the two's complement

representation: the complement of zero and of the largest negative number.

1. Find the 8-bit two's complement of 0000 00002.

1) One's Canplement: 1111 1111

2) Add one: +l

(cerry one) 0000 oooo

6-4

To the 8-bit accuracy chosen, the result is zero, and the carry of a 1 bit

out the left-hand end is lost. Thus the negative of zero is still zero,

which is a mathematically satisfying result; there is no such quantity as a

negative zero, which can be the case in some other representations.

2. Find the 8-bit two's complement of 1000 00002.

1) One's Complement: 0111 1111

2) Add one: +l

1000 00002

It can be seen in this case also that the complement of the

number is the same as the original number.

Thus we see that the two unusual cases which arise during complementation

are those for which all the bits except the sign bit are zero, and it is

found that the complemented result is the same as the original operand.

For a zero operand this is desirable, but for the negative case we have a

situation in which there is no corresponding positive value available for

a representable negative value. Such a situation is described by saying

that we have generated an overflow condition -- that is, the result is too

large to fit into the number of bits allotted for it. Overflow will be

treated in more detail in the following section on two's complement arith-

metic. We will note in passing that the number of quantities with negative

representation is the same'as the number of quantities with positive

representation, since the non-sign bits of the number may be chosen arbi-

trarily. It is sometimes said that the set of negative values in the two's

complement representation has one more member than the set of positive

values; what is meant is simply that the largest negative magnitude is

larger by one than the largest positive magnitude.

Decij~1 Value 320bit Two's Complement Representation

0

1

2%

5ooo

2147483647(2=-l)

-2147483648(-231)

-2147483647( 02~l+l)

-5000

-256

-2

-1 FFFF F~FIE,

0000 000016

0000 0003&j

0000 010016

0000 138816

7m FFFE'16

8000 000016

8000 000116

J?FFF EC7816

Figure 6.1 Examples of Two's Complement Representation

As was mentioned earlier, it is implicit in the representation of

positive numbers that an arbitrary number of zero bits may be added onto

the left end of a number without affecting its value. For example, the

8-bit and 16-bit representations of-the decimal value +V are 0000 10012

and 0000 0000 0000 10012, respectively. Similarly, the 8-bit and 16-bit

two's complement representations of -9 are 1111 01112 and 1111 1111 1111 01112,

respectively. Thus, for numbers which can be correctly represented in a

given number of bits, the correct representation using a larger number of

bits is found by simply duplicating the sign bit toward the left as many

places as desired. This process is called sign extension.

Length of Representation Representation of +l Representation of -1

8 bits 0116 FE16

16 bits 00()116 -16

32 bits oooo 000116 FFlF*E ml6

64 bits oooo 0000 0000 000116 FFFF FFFF FFFF FKFF16

Figure 6.2 Examples of Sign Extension

Sign extension will appear later in the discussion. of instructions which

perform shifting, and which do arithmetic with halfword operands.

6-6

7. TWO'S COMPLEMENT ARITHMETIC

Arithmetic operations on numbers in a binary representation are a

basic capability of almost all computers. Though the details of the number

representation may vary slightly from one machine to another, the methods

for performing additions, subtractions, multiplications, and divisions

remain nearly the same for all machines. Thus the discussion which follows

will bee slightly more general than would be necessary if only one

particular model of the System/360 series were being discussed.

We have already used sac examples of binary addition in the treatment

of addressing, in which the addition was straightforward. The rules for

the addition of binary digits are summarized in the following short table.

The addition of numbers in the logical representation is the most straight-

forward, since the bits are all numeric digits and do not represent signs.

Thus the only unusual condition to observe in such an addition is whether

or not a carry occurs out of the leftmost position, which would indicate

whether the resulting sum is or is not representable by the number of bits

available. In the two's complement arithmetic representation, the addition

is performed in the same way, but the result is interpreted somewhat

differently. (1) All bits of each operand are added, including sign bits,

and carries out the left end of the sum are lost. (This is the same as for

logical addition.) (2) If the result cannot be correctly represented

using the number of digits available, an overflow condition is said to have

occurred. Note that overflow is possible only when adding operands of like

sign: adding numbers with opposite sign always produces a representable

result (or, as is often said, the result is in range). When an overflow

occurs, the sign of the result is always the opposite of the sign of the

two participating operands. The actualmethodiused on most machines to

detect overflow is somewhat simpler, since the sign-change detection would

require remembering the signs of both operands for comparison against the

sign of the sum. In practice, the adding circuits need only note that the

carries into and out of the sign bit position disagree, to be able to detect q

overflow: that is, if the carries out of the two leftmost bit positions

differ, an overflow has occurred.

Subtraction is performed in the machine by adding the two's complement

of the number to be subtracted. That is, A-B is calculated using A + (-B),

where (-B) is the two's complement of B. A few examples using 8-bit

aritlmetic will illustrate the methods of addition and subtraction.

1.

2.

-3.

4.

5-

6.

7.

8.

5-3:

3-5:

25.( -17):

(-17).25:

-17.( -25):

674 -93) :

(4-67:

-1280(-93):

0000 0101-0000 0011

ooooooll-oooo 0101

0001 1001'-1110 1111

1110 1111-00011001

1110 1111-1110 0111

0100 0011-1010 0011

1010 0011-0100 0011

1000 0000-1010 0011

becmes-

(carry lost)

beccmes

(no carry)

becomes

(no carry)

becomes

(carry lost)

became6

(carry lost)

becomes

(no carry)

beccKnes

(carry lost)

becomes

(no carry)

0000 0101+llll 11010000 0010

0000 0011+llll 10111111 1110

0001 1001+oOOl 00010010 1010 .

1110 1111+lllO 01111101 0110

1110 1111+oOOl 10010000 1000

0100 0011+olOl 11011010 0000

1010 0011+lOll 11010110 0000

1000 0000+olOl 11011101 1101

= 210

= -210

= ‘+&o

= -4&o

= 810

= -g&o (overflow)

= $10 (overflow)

= -3510

7-2

9* 3-3: 0000 0011 becomes 0000 0011-0000 00112 +llll 1101

(carry lost) 0000 0000 = 0

The above examples illustrate addition and subtraction and give the

expected results. However, there is one case in which the method as given

above fails to detect correctly the presence or absence of overfluw, and

this occurs when the maximum negative number is being subtracted from

something.

10. I-( -128) : 0000 0001 becomes 0000 0001-1000 0000 +lOOO 0000

(no carry) 1000 0001 (no overflow found)

11. -I-( -128): 1111 -1111 becomes 1111 1111-1000 0000 +lOOO 0000

(carry lost) 0111 1111 (overflow indicated)

In each of these two last cases the overflow indication is incorrect.

This is because the process of taking the two's complement of the maximum

negative number has already generated an overflow condition. To see how

-the computer can still use the overflow detection scheme described above,

it is worth examining in slightly more detail the actual addition process

in the machine. (The next paragraph may be omitted by those uninterested

in such details.)

Remember that the two's complement of a number is found by inverting

each bit of the number and then adding a one in the low-order position. It

is very easy to build circuits which invert bits; similarly, the addition

of a 1 bit to the low-order position is also easy, for the following reason.

Each digit position of the adder circuits must add the corresponding bits

of the two input operands and the carry-bit from the next lower-order-bit position.

7-3

In the lowest-order position of the adder there of course can be no carry

from a lower-order bit position; if an identical adder circuit is used,

however, the carry input is still there, and can be used to insert the 1 to be

to be added to the low-order position. Thus subtraction is simply a matter

of passing the second operand B through a bit inverter which forms the one's

complement, and then activating the low-order carry input to the adder to

add the 1.

Thus we arrive at the following rule:

Subtraction is performed by adding the one's complement of

the second operand and a low-order one to the first operand.

It is easy to demonstrate that the correct algebraic result is obtained

by simply adding all the bits of the operands in the two's complement

representation as though they were logical operands. Since the logical

representation X corresponding to an integer x satisfies (assuming 32.bit

operands) X = 232 + x (modulo 232), then the sum of two operands X and Y

is \

(x + Y) = 232 + 232 + (x + y) (modulo 232) = 232 + (x + y) (modulo 232).

Thus the arithmetic and logical sums give the same binary result; the bits

are just interpreted differently for each representation.

One further observation may be made concerning the addition and

subtraction of numbers in the logical representation. From the examples

given above it can be seen tkt if the second operand is logically smaller

than or equal to the first (see examples 1, 4, 5, 7, 9, and 11) then there

will be a carry out of the leftmost bit position. It may be seen in

examples 2, 3, 6, 8, and 10 that if the first logical operand is logically

smaller than the second operand subtracted from it, there is

of the left end. In these latter cases we have in some sense generated a

"negative" logical answer, since the result is not correctly represented

to the given number of bits. A number of examples illustrating these cases

will be given later, when the instructions for logical arithmetic are

discussed.

7-4

There is a simple pictorial representation of the two's connplement

representation which is helpful in seeing what happens when two such

numbers are added or subtracted. The circle is visualized as having 2'32

points on its circumference, arranged as indicated. Arithmetic values are

on the outside of the circle, logical values on the inside.

If we begin at 0 and add 1 to a number, we will move around the

circle in a counter-clockwise direction until 231-1 is reached. When 1 is

added again, we reach -2'l and an overflow condition exists. Continuing

to add 1 then brings us back to 0. It can be seen that a*dding a positive

number to or subtracting a negative number from an existing number (say, A,

as on the circle) causes us to move in a counter-clockwise direction. If

in moving in this direction we go past the point labeled -232, an overflow

occurs. Similarly, adding a negative number to or subtracting a positive

number from an existing number (say, B, on the circle) causes us to move

in a clockwise direction; and if the motion carries us past the point

labeled- 02~', we again have an overflow condition.

7-5

m-: :* ‘* .F ‘7, r, !’ .:‘, . .

8. BINARY MULTIPLICATION AND DIVISION

Before we discuss the actual machine instructions which perform

multiplication and division using integer arguments, it will be useful to

examine a few simple illustrations of the basic method used by typical

computers to form products and quotients of binary numbers. A detailed

understanding of the methods is of course not necessary to be able to use

the corresponding instructions, but will help in remembering a number of

conventions that these instructions require;

Multiplication

E

To illustrate the method used in multiplication, let us first work an

example in decimal arithmetic. Suppose we have a "machine" with registers

which will hold j-digit decimal numbers, which we will assume are positive.

& the numbers to be multipli'ed by ~6 and 213. First of all, since we

are multiplying two 3-digit numbers, the product will be either 5 or 6

digits long. Thus if we are to be able to correctly represent it, the I

product register must be at least 6 digits long. Since we assumed the

number registers were 3 digits long, it appears that we need a double-length

register (or a pair of registers connected in some way) to hold the

product. So we will assume there is a 6-digit register somewhere, the

right and left halves of which will hold an ordinary 3-digit number. Now

let us examine the way in which we normally form such a product, as when

working with pencil and paper. By taking the product of the multiplier and

each of the multiplicand digits in succession, we generate a series of

partial products which must be properly

multiplier

multiplicand

partialproducts

product

126

x 213

378126

22L26838

aligned and then added. (Note that we are

using the terms "multiplier" and"multiplicand"

in the reverse of their normal meaning; this

is done so as to be consistent with the

terminology used3n other descriptions of

System/360.) Thismanual process can be

8-1

broken down even more, by writing the sequence of operations in a different

way.

initial register contents

add multiplier to upper end

that's 1 time

add multiplier

that's 2 times

add multiplier

that's 3 times

shift right 1 place

add multiplier

that's 1 time

shift right 1 place

add multiplier

that's 1 time

add multiplier

that's 2 times

shift right 1 place

000 213

+126

126 212

+~26

252 211

+126

378 210

037 821

-1-126

163 820

016 382

a-26

142 381

+1.26

268 380

026 838

We place the multiplicand in the right half of the double-length

register and clear the left half to zero. Then by examining the rightmost

digit of the multiplicand we know how many times to add the multiplier

to the left half of the double-length register. When the rightmost digit

has been counted down to zero, the partial product of that digit and the

multiplier has been added to the accumulating result. Then the entire

double-length register is shifted to the right one digit position, at which

time the zero digit at the right-hand endis lost and a zero digit is inserted

in the vacated position at the left. The process of adding the multiplier

and counting down on the multiplicand digit then continues until the proper

partial product has been added to the accumulated result. This process is

repeated for as many steps as there are multiplicand digits. When completed,

the result in the double-length register is the product, and all the

multiplicand digits have been shifted off the right-hand end. The main

8-2

points to observe are that (1) the multiplicand is placed in the right half

of the double-length register, (2) the left half is initially cleared to

zero, (3) the multiplier is added to the left end depending on the multipli-

cand digit at the far right, and (4) the decimal point of the result (that

is, the position of the least significant digit) is at the right-hand erd

of the double-length register, because the number of right shifts was tne

same as the number of digit positions in a single-length register.

The above example omits one rather important detail which is not

actually necessary to an understanding of the basic process. (These two

paragraphs concern technicalities, and may be skipped with little loss of

continuity.) When the multiplier is being added to the left half of the

double-length register, it is possible that an overflow can occur. If the

multiplicand had been 219 rather than 213, the first partial product

(126 x 9 = 1134) would have been too large to hold in the three digits

provided. Thus provision must actually be made for an extra digit at the

leftmost end of the register. This extra digit can be thought of as

hidden from the user of the registers, since when the right shift is

performed at the conclusion of each cycle, the contents of this "overflow

digit" position move into the leftmost digit of the double-length product

register. Since the example was carefully contrived to avoid the necessity

of worrying about this detail, the presence of a zero digit at the left end

after the right shift is seen simply to be an-indication that there was no

overflow in the formation of the partial product. The assumed presence of

this extra digit position will be useful in the discussion of division.

This small but annoying difficulty can also be handled by having the

extra "digit position" attached after the rightmost digit of the double-

length register. Then instead of adding and then shifting, we could first

shift and then add. Thus the extra digit position will hold the number

of times the multiplier is to be added. However, the additions of the

multiplier must then be realigned so as to add to the second, third, and

fourth digits of the double-length register rather than the leftmost

three. Either way, the whole business is a necessary nuisance. 0-hese

comments will of course apply to the binary multiplication example which

follows.)

8-3

.r.; _ ,l,,, ,;.”. j

The above scheme, when used for multiplying binary numbers, is

conceptually very easy to implement since a test of the rightmost bit

determines in simple yes-no form whether or not the multiplier is to be

added -- no counting of additions is required. To illustrate this, suppose

we have y-digit binary numbers and registers and wish to multiply 00110;r

by 010012 to obtain a lo-bit product in a double-length register. Then the

sequence of steps shown below indicates the method.

Initialize

Step 1: rightmost bit = 1,add multiplier

Shift right 1

Step 2: rightmost bit = 0,no add. Shiftright 1

Step 3: rightmost bit = 0,no add. Shiftright 1

Step 4: rightmost bit = 1,add multiplier

Shift right 1

Step 5: rightmost bit = 0,no add. Shiftright 1

00110

oooa 0100~

00110 01001

multiplier (in separate register)

multiplicand in right half ofdouble-length register

00011 00100_ (1 bit lost)

00001 1oOlCJ

00000 llOO&

00110 11001

00011 0110~ (1 bit lost)

00001 10110 final product = 1101102 = 5410

It is most important to observe that the product is really a double-

length number, and not simply two single-length numbers stuck end to end.

If we were to consider the contents of the left and right halves of the

double-length register as ordinary single-length two's canplement operands,

we would find the result in the right, or low-order half, to be negative!

Since the product (which was computed from two positive numbers) must be

positive, it can be seen that the need for a double-length register means

that no special significance can be attached to the low-order result, unless

it is known in advance that the product is correctly representable in a

8-4

single register. The leftmost bit of the right-hand register is therefore

not a sign bit -- it has positive weight in the double-length result.

In the example above, the two operands were purposely chosen to be

positive so as not to introduce any problems with signs. Since the operands

actually used may be positive or negative two's complement integers, there

are other steps which must be taken to find the correctly signed product.

For all practical purposes, however, xe may assume that the CPU performs the

multiplication by using the magnitudes of the operands, and then complements

the double-length result if a sign-bit analysis of the original operands

indicates that the result is negative.

Itis also common in modern computers to gain speed by considering

not the rightmost single bit of the multiplicand (as on the IBM 7090), but

to consider the rightmost two bits (IBM 7094), three bits (Burroughs ‘J500),

or even four bits (larger models of System/360). This of course brings us

back to a situation similar to that in the decimal example, where the

proper multiple of the multiplier must beaded to the left end of the

developing product. In these cases, where the arithmetic can be considered

to be of base 4, 8, or 16, the "proper multiple" is of course not found by

counting down by ones on the multiplicand digit, but by having the internal

circuits generate the proper factor in a very much smaller number of steps.

This serves to increase the speed of multiplication considerably, since

then a separate addition is not required for each 1 bit detected in the

multiplicand.

Division

Division works the same as -multiplication, only backwards. Instead of

adding onto the high-order half of the accumulating product, we subtract;

instead of counting down in the rightmost digit position, we count up;

instead of shifting right, we shift left. As before, an example using

'decimal arithmetic will illustrate the process.

Since we start with a dividend and divisor and wish to find a quotient

and remainder which satisfy the equation

dividend = quotient x divisor + remainder,

8-5

it is apparent that the dividend must be a double-length number. Again '

supposing that the basic register length is three decimal digits, another

requirement becomes apparent: since (a) the quotient, to fit in a register,

can be at most three digits long (that is, not exceeding 999) and (b) the

remainder must be less than the divisor, we must not have a dividend larger

than

999 X divisor + (divisor - 1) = lo3 X divisor - 1.

(The factor of lo3 is the base raised to the number of available digits.)

Since multiplication by lo3 in this example is equivalent to shifting left

three places, the above relation means that if the division is to produce

a valid'quotient, the high-order half of the dividend must be less than

the divisor. (If for instance the divisor were 456, then any dividend not

smaller than 436000 = lo3 x 456 would require a b-digit quotient; if the

dividend is not greater than 455999 = 10' X 456 - 1, the the quotient can

be held in the three digits allotted. Note that the three high-order

digits, 4'3'3, are now less than the divisor.)

Suppose we want to divide 162843 by 762. In ordinary long division,

we would do the following sequence of steps. At each step we determine

213762m3-G

how many multiples of the divisor can be subtracted

from the leftmost part of the dividend, and enter that

10447622823

number as the quotient digit. When the subtraction

process has been completed, the remainder, from which

2286 no further subtractions can be made, is 537, and the537 quotient is 213. Just as a check, we find that

762 x 213 + 537 = 162843. On a machine, the process is almost identical.

Using the above scheme of &cimal registers, the division works as follows:

8-6

162 843

7621 628 430

-762

0 866 431

-762

0 104 432

i 044 320

-762

0.282 321

2 823 210

-762

2 061 211

-762

1299 2l2

-762

537 213

High-order part of dividend smaller than divisor,

division may proceed.

Shift dividend left once; save leftmost digit in an

"overflow digitfl position. Since dividend 2 divisor,

subtract, and count up at right end.

dividend > divisor; subtract again

dividend < divisor; no subtraction

shift dividend left again

dividend 2 divisor; subtract and count up

dividend < divisor; no subtraction

shift left for last time-

dividend 2 divisor; subtract

subtract and count up by 1

dividend 2 divisor; subtract

subtract and count

dividend 2 divisor; subtract

dividend now < divisor; stop

As the successive digits of the quotient were developed, they appeared

at the right hand end of the double-length register, and were shifted left

as the division progressed. Thus at the completion of the division, the

quotient is to be found in the right half of the register pair, and the

remainder, from which no further subtractions could be made, is in the left

half.

As was the case for multiplication, binary division is simplified by

the fact that at most one subtraction need be made for each quotient digit

generated. To illustrate, consider this example using a five-bit divisor

and a ten-bit dividend. Let the dividend be 0000111011~ = 5910, and let the

divisor be 001102. Note that the two halves of the double-length dividend

are not two five-bit numbers stuck end to end: the leftmost bit of the

right half of the dividend is not a sign bit (with negative weight) but an

arithmetic digit (with positive weight). The quotient and remainder,

however, are ordinary (i.e., signed two's complement) five-bit numbers, so

that when the division is complete the proper rehults are found in each

Xeb;iSter . This leads to the, following scheme.

1. Shift the dividend left once. If the high-order (left) part

of the dividend is not smaller than the divisor, an illegal

division is being attempted.

2. Shift left one bit position. If the high-order part of the

dividend is greater than or equal to the divisor, subtract

the divisor from the dividend and insert a 1 bit in the

rightmost digit position. Otherwise do nothing.

,3* Return to step 2 until a total of 5 shifts has been done

including the shift of step l.- (For 320bit operands this

cycle repeats 31times.)

00011 10110 shift left once

(00110) dividend < divisor, OK to continue

1 00111 01100 shift left once (second time)

00001 01101

00010 11010

00101 10100

subtract divisor, insert 1

shift 'left once (third time)dividend < divisor; no subtraction

shift left once (fourth time) 'dividend < divisor; no subtraction

01011 01000 shift left once (fifth and last time)

00101 01001 subtract divisor, insert 1.

Thus the remainder 001012 = 510 in the left half, and the quotient 010012 * 9~@

in the right half are as expected.

The example given assumed a positive dividend and divisor; if either

is negative some further steps are necessary. The division can be thought

of as proceeding with the magnitudes of divisor and dividend, and afterward%

the quotient is made negative if the signs of the divisor and dividend

differed, and the remainder is made negative if the dividend was negative.

As in the case of multiplication, there are techniques used for speeding

up the division process which are used on some models of System/36O. Thex~

details are of concern only to the machine designer, so that the prograrm3ler

can think of division as proceeding through the simple steps shown above.

8-8

9. ASSEMBLER LANGUAGE

As was indicated in the introduction, the service program which will be

of most use in setting up instruction sequences for execution by the machine

is the Assembler. The collection of conventions and rules established for

use of the Assembler is known simply as Assembler Language, even though

there is no resemblance to what we usually mean by the term "language"O

Before describing some of the basic conventions used in communicating

with the Assembler, it may help to consider first the overall process of

running a machine-language program on the computer. This process may be

broken down into five major parts, as follows: (1) job initiation, (2) assembly,

(3) linkage editing, (4)execution, (5) job termination.

1. Job initiation will usually involve the checking of the job information

provided by the programmer, such as charge number, time and page estimates,

and so forth, as required by the particular ccmputer installation. If these

details are acceptable, then preparations are made for the execution of a

series of job steps, which in this case will include assembly, linkage

editing, and execution.

2. The assembly step is represented schematically in Fig. 9.1. The

Assembler is a processing program (a previously prepared set of machine

instructions) which is placed in the memory of System/360 and is allowed

to begin execution.

“A. L-L(bAu- I 'qx/ions, etc.

Figure 9.1 Simplified Schematic of Assembler Processing

9-l

The Assembler reads the statements (to be described shortly) of the programmer's

Assembler Language program, processes them -- possibly with the help of some

pre-stored data in the library of macro-instructions (also to be described

later) -- and eventually produces as its output an object module, which will

usually be written onto some storage device such as a magnetic drum or disk.

(The object module may also be punched on cards, so that a programmer could

then have his program in both its original form and in its assembled form.)

Usually the programmer will want a program listing, which is printed output

giving the source program and pertinent details of the Assembler's processing,

along with indications of any errors detected by the Assembler.

3. The linkage editing step is shown schematically in Fig. 9.2. The

Linkage Editor, like the Assembler, is a processing program which is placed

in memory and allowed to begin execution.

1 System/3601

Object Modules

Figure 9.2 Simplified Schematic of Linkage-Editor Processing

The Linkage Editor reads the object module (or modules; cases in which

several may appear will be described later) and combines it with other object

modules that may be necessary for proper program execution. The output

produced is the completed program and is called the load module, which is

written onto a storage device for later use. A printed listing of information

pertinent to the link-edit step may also be produced.

9-2

4. The execution ptep requires that the load mpdule produced by the

Linkage Editor be placed in (or "loaded" into) memory, in such a way that

it will execute correctly (amming, of course, that the programmer has

made no blunders!). An essential feature of this process is relocation,

details of which will be treated in several later sections.

m

Load IModule

System/360

Figure 9.3 Simplified Schematic of Program Loading and Execution

When the program has been loaded and relocated, the Resident Supervisor.--transfers control to the program (that is, sets the Instruction Address to

the address of whatever tistruction was specified as the one with which

-execution is to begin). *he program then performs whatever processing

was specified by the programmer, and when it is finished returns control

to the Supervisor (that is, sets the lA to an agreed-upon value 80 that

the Supervisor may continue processing the next job).

5= When the Supervisor program has regaint-:d control it performs any

necessary "cleaning-up" operations such as noting the amount of time used

by the job, -the number of pages printed, and so on. If more jobs are to be

done, the Supervisor reverts to step 1 (Job Initiation) and the entire

cycle repeats.

The brief description of job processing given above will help in under-

standing s-cme of the constructs necessary to the writing of a correct

Assembler Language program, since certain of them apply during each of the

assembly, link-edit, and execution steps and must be used with the different

steps in mind.

9-3

A program is prepared for the Assembler in the form of statements

punched on cards. Statements are of four general types: cement statements,

machine instruction statements, assembler instruction statements, and

macro-instruction statements. Comment statements are used by the programmer

to insert explanatory material in the program so that it will be easier to

read and understand the program listing. Machine instruction statements

contain instructions which the computer may execute during the execution

step of the job. Assembler instruction statements contain information of

use to the assembler du&ng the assembly step; these can be as simple as a

statement specifying that four blank lines are to be left in the program

listing, or can be more complicated such as a statement which informs the

Assembler that it may assume certain registers may be used as base registers.

(This latter case will be treated in detail in Section 12.) Finally,

macro-instructions provide a convenient means for specifying sequences

of statements (all four types are allowed) inwhich various parts of the

specified sequence can be changed to suit the needs or desires of the- programmer. We will see later that the ability to process macro-instructions.

- is a very powerful and useful feature of the Assembler Language.

The Assembler provides a number of other capabilities which considerably

simplify the programmer's task. For example, we saw in Section 3 that a'

typical machine instruction might consist of 8 hexadecimal digits. Rather

than having to remember that the operation code 43x6 causes a byte to be

transferred from memory to the right-hand end of a general register, a

mnemonic operation code is provided which gives an easily-remembered

abbreviated description of what the operation code does. In the above case,the mnemonic is-IX, which stands for."&nsert Character", character in this

case being synonymous with byte. Another useful feature is that the

Assembler allows us to specify information in a variety of forms: as decimal,

hexadecimal, and binary numbers, as strings of characters, as arithmetic

expressions, and so on. Thus we will find that if we want to designate

register 12 for some use, we can use the decimal number 12 instead of having

to use the hexadecimal digit F, which is what may eventually appear in the

instruction itself. A third and most important feature of the Assembler

is the provision for symbols which may be used by the programmer to name

places in memory. Thus, if a program needs to make reference to a fullword

area in memory which contains a particular piece of data, the Assembler

will permit the programmer to name the fullword and then to make references

to the data by using the name. A discussion of symbols and certain aspects

of their use will be given in the next section. In the remainder of this

section we will give some examples of statements, and define or illustrate

terms which will be used in describing statements.

In general, statements occupy columns 1 through 72 of a card, with column

72 having a special meaning: if column 72 is not blank, it means that the

next card is to be considered as a continuation of the card with the

non-blank character in column 72, in such a way that column 16 of the second

card is considered to follow immediately after column 71 of the first.

(These numbers are actually under the control of the programmer, who may

specify with an assembler instruction statement that other card columns are

to be used for the start and end of a statement. The numbers given are

simply the usual ones which the Assembler will assume are to be used if it

is not told otherwise.) (It is a common error for beginning programmers to

punch characters in column 72 unintentionally, so that the next statement

is processed in an unexpected way.) Columns 73 through 80 are ignored by

the Assembler when it processes the statement, and may be used for identifi-

cation or sequencing information.

A comment statement is identified by the presence of an asterisk ('*)

in column 1. Any information desired may appear in columns 2 through 71.

An example of a comment statement appears below, as it would be punched

on a card.

9-5

_. -c----_-----. _ic. .N A M E

i,I

NAME 1 O P E R A T I O N 1

>.. __

C O M M E N T S

i IOPERATION 1 1 C O M M E N T S

!ii??<?SYSTEM/360 4I 2'ST@la#R'd' ASSEMBLER CARD

9 9 9 9 956 57 56 59 6i

0 0 0 0 061 62 63 64 6’

1 1 1 1 1

22222

333J3

44444

55555

66666

11111

88888

9999961 62 63 64 6:

00000066 67 66 69 JO ‘II

1 1 1 1 1 1

444444

555555

666666

111771

888888

9 9 9 9 9 968 C7 68 83 70 II

5’5 5 5 5 5 5 5 5’

666666666 I

IIFigure 9.4 A Comment Statement

The machine instruction statement, assembler instruction statement,

and macro-instruction statements each have four parts called fields. They

are respectively the name, operation, operand, and comment fields; of these,

an entry in the operation field must always be present, and for certain .

types of statements entries in scme of the other fields may or must be

omitted. If there is a name field entry in the statement, it must begin

with a non-blank character in column 1; it is terminated by the first blank

column after column 1. If no name field entry is desired, column lmust

be left blank. After the name field, and separated from it by one or more

blank columns, comes the operation field entry; it ends with the first

blank-column after the start of the -operation field. After the operation

field entry and separated from it by one or more blank columns comes the

operand field entry which, like the name and operation field entries,

terminates (except for one unusual case to be described later) with the

first blank column detected after the start of the operand field. The

rest of the card is treated as cments (that is, it is ignored) by the

Assembler, and does not influence the processing of the statement (unless,

of course, the comment field extends into column 72 indicating a continuation

9-6

on the next card). Note that with the exception of the name field, no

requirement is made regarding the columns in which the other three fields

must start; they simply end with a blank column. This allows what are

called free-field statements, in which the programmer may arrange the

information on the cards of his program as he desires, with the only

restriction being that the fields appear in the proper order.

The figure below illustrates a machine instruction statement in which

entries in all four fields appear, and which if executed in a program would

cause the contents of general register 7 to be replaced by the contents'

of general register 3. (The particular form of the operand field entry

wiil be discussed later.)

D ASSEMijL

I

,su. 6 4 5 9--- -__-_-- --_._ -.-- _._ _-__ ~. .-_-F-b -___---- -----__-- ^- -- _.-

Figure 9.3 A Machine Instruction Statement

An assembler instruction statement (in which the name and comment

field entries are omitted) which would cause the Assembler to leave four

blank lines in the program listing is given in the following figure.

9-7

5 5 5 5 5 5 5 5

6666f666

7 7 7 7 7 7 7 7

1:8:8::8

5 5 5 5 5 1I

6 6 6 6 6 6I

*77)777

8aa88a

9 9 9 9 9 9Y 10 II 12 I3 I46509

4 i I OPERAND A N D C O M M E N T SII I I . I I I I

IATION 1 IO P E R A N D C O M M E N T S

OPERAND COMMENTS

00000000000808800~000000000000000000000000000000000000000

15 16 17 1. 19 20 21 22 23 24 23 26 27 24 29 18 31 32 33 34 35 36 31 a 39 46 41 42 43 U 45 46 41 46 49 50 51 52 33 34 33 36 37 38 59 66 61 62 63 64 63 66 67 66 69 n II

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3333333333333333333333333333333333333333*333333333~3333333

4)4444444444 Igh’f S Y S T E M 1 3 6 0 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

5 5 5 5 5 5 5 5 5 5 5 5 STANDARD ASSEMBLER CARD 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 54

6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6

7777777777777777777777777777777777777777777777777777777j7

88888888888811:8:6888a8~8888888888888888888888~8~88888888~

9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 915 16 17 18 19 20 2l 22 23 24 25.26 21 2l28 30 31 32 33 34 33 36 31 38 39 40 41 42 43 U 43 46 41 46 49 30 51 52 53 54 55 56 51 59 39 60 Cl 62 63 64 65 66 6166 lit 76 11

Figure 9.6 An Assembler Instruction Statement

-Finally, an example of a macrd-instruction statement in which only the

operation field entry appears is given below.

twIBi4Am 6fwfI(I

001808008

-312 n 14 )I n 77 18 14

1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3

~

4 4 4 4 4 4 4 4 4

55555$555

6 6 6 6 6 6 6 6 6

7 7 7 7 7 7 7 7 7 1 1

888lllllll8

1 i9 9 9 9 9 9 9 9 972 n 74 79 n n 78 IE

.F--- _-_--I I ,;?ggFy -.

/I NAME OPERZG 1I

g ’ szEL&-- ’ --I .\AND COMMENTS

1 I I I I I Iii

NAME 1 OPERATION 1 1 OPERAND COMMENTS

NAME OPERATION OPERAND COMMENTS t4unfsm6 mm

ooooooooo’ooooocoooococ-~-~oGooooooooooooooooooooooooooooooooooooooooooooooooooooo

1 2 J 4 f 6 1 6 9 IO 11 12 I3 I4 15 1G 11 16 10 20121 22 23 24 25 26 21 26 29 30 31 32 33 34 35 3t 37 36 39 40 41 42 43 U 45 46 47 48 49 5G 51 52 53 54 55 56 57 38 59 60 61 62 63 64 65 66 67 66 69 70 71 72 13 14 13 16 71 16 74 94

1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 ~ 1 1 1 ~ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2

3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 1 3 3 3 3 ~ 3 3 3 3 3 3 ~ 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 ~ 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3

4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 8 4 4 IB%‘+if S Y S T E M / 3 6 0 1 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4

555555555555555555555p55551 STANDAkD A S S E M B L E R C A R D 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5

: 666666.66666666666666666666666666666666666666666666666S66666666666666666666666666/ I

j77777777777-7777777777771717717117117777711717171717777777777777117777777777777i7 11

1’ 818188881088888888888888888888888888888a88~88~8888888888888888~88~8~888888~8008~~ e!III’ 9 9 9 9 9 9 9 9 ’ 9 9 9 9 9 9 9 9 9 9 9 9 8 9 9 9 1 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 9 i:. 1 2 3 4 5 6 7 I 9 10 11 12 13 I4 I5 16 17 l6 19 20121 22 23 24 25I I26 27 26 29 30 31 32 33 34 3&36 31 38 39 40 41 42 43 44 45 46 47 49 49 50 51 52 53 54 55 56 31 59 59 60 61 62 63 64 93 66 67 68 69 10 ll 12 13 14 13 16 71 16 19 6%

\, _ _ _ _ _ _ L!coo’--__, I--1__--. - - - - - - - - - - - - - -_----- I --..-- - - - --_ .-

Figure 9.7 A Macro-Instructfon Statement

9-a

10. SELF'-DEFININGTEBMSANDSWOLS

In using the Assembler Language, two constructs of importance are

self-defining terms and symbols. Each has a value; in self-defining terms

the value is inherent in the term, whereas values are assigned to symbols

by the Assembler (under control of the programmer, of course).

There are four types of self-defining terms: decimal, hexadecimal,

binary, and character; the value of each is always taken to be positive.

A decimal self-defining term is simply an unsigned string of decimal

digits. 12345, 98, and 007 are examples of decimal self-defining terms.

The size of a decimal self-defining term is limited by the fact that 24 bits

are allotted by the Assembler to hold its value; hence a decimal self-

defining term must (a) contain 8 or fewer digits and (b) be less than or equal to.$4 41 = 16777215.

A hexadecimal self-defining term is written as the letter X, an

apostrophe, a string of up to 6 hexadecimal digits, and a second apostrophe.

x23456’, X'FACED', and X'OOlB7' are examples of hexadecimal self-defining terms.

As above, the value of a hexadecimal self-defining term must be at most

224-1 = X'FFFFFF'.

A binary self-defining term is written as the letter B, an apostrophe,

a string of up to 24 binary digits, and a second apostrophe. B'llOOlO',

B'OOOl', and B'1111111100001100' are examples of binary self-defining terms,

Because 24 bits are allotted for the value of self-defining terms, at most

24 digits may be specified between the apostrophes. Note also that the

.value of the term is assumed positive even though the leftmost position

contains a one bit..

A character self-defining term is written as the letter C, an apostrophe,

a string of up to three characters (except for two cases to be described

momentarily), and a second apostrophe. Thus, PA', C'...', and C'A B' are

10-l

valid character self-defining terms. The third example, in which a blank

appears, Is the exception to the rule mentioned in Section 9 that the operand

field is terminated by the first blank column after it starts: if the

blank Is part of a character atring as in a character self-defining term,

it doean? count. The two unusual cases which arise in character strings

concern the apostrophe and the ampersand. It is clear that if apostrophes

are to be used to delimit the character string, some mean&must be found

to get an apostrophe #to the character string.( T h e a m p e r s a n d h a s a

ope4.al use in paacro-instructions which will be treated later.) The

teohrriique used in the System/360 Assembler Language is to represent an

apostrophe (or -persand) in a character string by a pair of apostrophes

(or amperrands) -- a character self-defining term containing a single

apostrophe (or ampernand) would therefore be written C"" (or C%&').

Thlr can lead to cryptic constructs such as Cf'*""' and C'8&b8&8&, but

they are valid character self-defining terms.. The problem now arises as

to hov a value Is arsociated with character self-defining tetis; it is- clear that this will depend on the internal representation assumed for

- characters. In SysteB;/%C the conventional representation is called the

Extended Binary Coded Decimal Interchange Code, or EBCDXC, or even EBCD,

for short. Each character is represented internally by a single byte --

two hexadecimal digits -- as indicated in Table III. Note that the characters

$, #, and@ are considered to be letters in the Assembler Language. TM6

will have bearing on the definition of symbols, which will be discussed

shortly.

10-2

!wg!!‘4 :;

.‘,

E

Character Representation Character Representation Character Representation

blank 40 C c3 T E3

0 4B D c4 U E4i

( 4D E c5 V Es+ 4E F c6 W E6

& 50 G c7 X E7

$ 5B H c8 Y J@

* 5c I c9 z E91 5D J Dl 0 (digit) FO

-. 60 K lx 1 Fl

I 61 L D3 2 F2_

9 6~ M D4 3 F3

# 7B N m 4 F4@ 7c fi (letter) D6 5 wI 7D P D7 6 F6

= 73 Q D8 7 F7--A Cl 'R w 8 F8

B c2 S E2 9 F9*.

Table III. EBCDIC Character Representation

Thus the value associated with the character self-defining term C' '

is the same as that of the hexadecimal self-defining term X140', the binary

self-defining term B'lOOOOOO', and the decimal self-defining term 64.

Which type of term is chosen by the programmer is largely a matter of

context; certain tjpes will be more natural than others in some places.

In practice, we will find that decimal self-defining terms are used so

extensively that it is easy to forget that any other type of self-defining,

term of the same value could be used as well.

Inthe previous section, Fig. 9.5 is an example of an instruction inwhich the operand field entry contains the decimal self-defining terms 7 and 3.

10-3

Symbols are a somewhat more intricate matter, even though their use

will be seen later to be as. simple and natural as the use of self-defining

terms. A symbol is a string of from one to eight letters or digits, the

first of which must be a letter. (Remember that $,@, and # are "letters"

to the Assembler.) No special characters are allowed (namely "(", ")",'1 '1 I' '1+, -9

“*‘I I’ I’I 9

I’=” I1 1t I’ ‘I ‘1 , I?J 9 l t It , "&", and " " (blank)). The

following are all valid symbols.

A AGENT007 AlB2C3D4

#235 fim App)=

JAMES J=FI6 PRURIENT

$746~5 WfhKA - ZYZYGYV9

The following are not valid symbols, for the reasons given.

$7462.95 (decimal point not allowed)

B@J!JD/OO7 (no division sign allowed)

SET G@ (no blanks allowed)

235# (does not start with a letter)

CHARACTER (too many characters)

/ TlXN*FlXE (contains the special character *)

C'WfhKA' (no apostrophes allowed)

Symbols have the following six attributes: value, relocatability,

length, type, scaling, and integer. Of these, the first three will be our

main concern, and the last three will be discussed later.

A-symbol acquires a value by virtue of its appearance as the name

field entry in a statement of an appropriate type: The relocatability

attribute depends on several factors, one of which will be mentioned shortly;

-we usually say simply that a symbol is relocatable or absolute (not

relocatable). The length attribute of a symbol depends on the type of

statement in whose name field the symbol appears. We will give a number

of examples of the use of symbols in statements which are typical of actual

programs. The reader should bear in mind that these are simply examples and

that the instructions described here will be covered in detail later.

10-4

Symbols are mainly used as names of places in memory. In Fig. 9.5

the symbol @AD is the name of the location at which the instruction (whose

mnemonic is LR) begins. In the machine instruction statement

GlDC#NST L

the symbol GETC$NST is

a fullword fr<rm memory

instruction statement

TEN DC

0,‘+(2,7)

the name of another machine instruction which loads

into general register 0. In the assembler

F'lO'

TEN is a name for a fullword area in memory into which the assembler will

place'the integer constant 10. In the macro-instruction statement

EXIT (14,MJ

the symbol EXIT is the name of the beginning of the macro-instruction. It

is clear that no symbol can be given a value in a comment statement.

Two further questions will be discussed in this section: how do

symbols get their values,-. and of what real use are they anyway? A

partial answer to the second question is that their use greatly simplifies

the programming task, and we will be in a position to appreciate this

soon. To answer the first question, it is useful to examine briefly the

pertinent part of the assembly process.

When a program is ready to be assembled, one of the first steps the

Assembler must perform is the assignment of a relative origin (or starting

location). In the discussion of job processing it was mentioned that at'

the beginning of the execution step the user's program (in load module

form) had to be loaded into memory. Now it will almost invariably be the

case that the programmer has no a priori knowledge of where the Supervisor

program will begin loading his program, and in fact the place where it

begins may change each time the program is run. Thus, during the assembly

'step, the best that the programmer (and therefore the Assembler) can do is

assign a relative origin for the program which will act as an assumed

location for the beginning of the program. (The program must of course be

written so that it will work correctly even if the assumed relative origin

differs frcl,m the actual origin assigned by the Supervisor.)

10-5

Using this assumed origin as the initial value of the Location Counter

(which we will abbreviate LC), the Assembler begins scanning the statements

of the source program. As each statement is read, the assembler determines

(a) whether a symbol appears in the name field, and (b) the length of the

area in memory which will be occupied by the instruction. If there is a

symbol, the value assigned to it will (except for one unusual case) be the

value of the LC at that time. The LC is then incremented by the length

just computed. For example, suppose the value of the LC was 7~636 when the

statement given in the first example above was scanned. Then the value of

the symbol GETC#NST would be 7~6~6, and because the instruction whose

mnemonic is L is an RX-type instruction of length 4 bytes, the TX: is

incremented by four and will be ml6 when the scan of the following

statement is begun. In this way the Assembler scans all the statements of

the program and assigns values to all symbols appearing as name field

entries. It should be noted that there are other methods for assigning

.values to symbols, but the method described is what will most often be

used, and that there are also assembler instruction statements which allow

the programmer to change the value of the Location Counter. This usual

method of symbol definition provides the simplest definition of a

relocatable symbol: suppose the relative origin is changed by some fixed

amount; if the value of the symbol changes by the same amount, then that

symbol is relocatable. We will see later that it is also possible to

define symbols whose values either do not change or which change in

different ways. (The reader should also note that there is a definite

difference between the LC, which is maintained by the Assembler program in

the course of processing the statements of the source program, and the

Instruction Address in the ISW, which gives the location in memory of the

next instruction to be executed during the execution step of the program.

They are not at all the same.)

After this brief discussion of how symbols get their values, we turn

to the question of their utility. Suppose we want to write an instruction

which will load the integer constant ten into RO (remember that this is an

abbreviation for general register 0). Suppose also that we also know that

10-6

some other general register will contain an address which will provide

addressability for the fullword area of memory containing the constant.

Then we could calculate what the exact displacement would have to be and

write the instruction with the base and displacement given explicitly.

If, for example, these were 6 and 4EC16 respectively, we could write

(the details of writing the operand field will be discussed in the next

section)

L o,x*~Ec'(o,~)

If, however, the fullword area containing the constant were given the name

TEN (as in the example earlier), we could write instead

L o,m

and let the Assembler figure out what base and displacement to use. To do

this the Assembler needs only to be informed of the address it should

assume will be in register 6 (the method will be discussed in Section l2),

and the calculation of the displacement will be done for us. It may seem

that this is a relatively small return for so much effort; it can be seen,

however, that if the program 'is modified slightly so that the constant no

longer lies in exactly the same position relative to the assumed given base

address, then all imtructions which refer to the constant must have their

displacements recalculated. (It is of course implicit in this discussion

that (a) no program works just the way we want it to on the first try, and

(b) even if it did we'd think of some changes to make before we got done

with it. If this were not so we could dispense with assemblers and be

content with producing programs consisting of strings of hexadecimal

digits -- but even those who programmed the earliest machines that way are

agreed that assembly languages are-an improvement.) Thus the main function

of the Assembler will be to provide a convenientmeans for writing and

modifying a given program and getting it to execute correctly, by performing

many of the details of the programming process for us.

10-7

11. INSTRUCTIONS (II), MNEMONICS AND OPERANDS

In this section we will consider some of the problems of writing actual

machine instructions, using a number of instruction formats and giving Borne

simple example6 of actual code sequences. The use and detail6 of the

functioning of the individual instructions-will be the subject of many

later diSCUSSiOnS, so no effort should be made to memorize the mnemonics,

operation codes, or deScriptiOn6 of any of the instructions at this point.

Mnemonics provide a short abbreviation for a descriptive word or phrase

which designates the action of each operation code. They may range fran

something as simple as "A" meaning "Add", to "DXLE" meaning "Branch on Index

-‘Low or Fqual". To simplify the presentation, we will discuss each claes of

instructions separately, and sometimes give examples of how they are written.

A number of abbreviations such as rl, ~2, I, etc. will be explained as we

go along.

Instructions of RR format are given in Table IV; several things should

be,noted about the instructions listed there. First, not all of the

available digit combinations between 0016 and 3FL6 (in the column6 labeled

"Opcode") are used as actual operation-codes. Second, all of the instruction6

in the second column refer to the floating-point registers, the uses of

which will be described in detail later. (The floating-point instructions

operate on data in a format which is interpreted differently frau the

integer representations discussed in Section 6.) Third, two of the instructions

(namely SSK and ISK) are not normally available to the programmer and their

descriptions will therefore be deferred (they are called privileged operations).

11-l

Mnemonic .Jfwtxuction

SPMBALRBCTRBCRSEXISKWC

LCRNRC&RplRXRmCRARSRMRDRAIRSIB

Set Program MaskBranch and LinkBranch on CountBranch on ConditionSet Storage KeyInsert Storage KeySupervisor Call

Load PositiveLoad NegativeLoad and TestLoad ComplementLogical ANDCompare Logical -Logical @RExclusive $RLoadCompareAddSubtractMultiplyDivideAdd LogicalSubtract Logical

O-p50uemonic Instruction

20 LZ'DR22, LNDR22 IX'DR23 LCDR24 HDR28 LDR29 CDR2A ADR2B SDR2c MDR2D DDR2E AWR2F SWR30 LPER31 LNER32 LTER33 LCER34 HER38 LER39 CER3A AER3B SER3c MER3u IXR3E Au?3F SUR

Load PositiveLoad NegativeLoad and TestLoad CcmplementHalveLoadCompareAdd NormalizedSubtract NormalizedMultiplyDivideAdd UnnormalizedSubtract UnnormalizedLoad PositiveLoad NegativeLoad and TestLoad ComplementHalveLoadCompareAdd NormalizedSubtract NormalfzeBMultiplyDivideAdd UnnormalizeaSubtract Unnortnafizec?

Y

TABLE I-V.

RR Instructions

&X all but two of the RR instructions, the two operands of the operand

iWl.d enCry in a machine instruction statement must be written in the fomn

where the operands rl and r2 will be described shortly. The exceptions,

whi& have only a single operand in the operand field entry, are SPM (in

which case the operand is written in the form rl ) and SVC (in which

case it is written in the form I ).

To explain the meaning of the notation %l,r,$', it is perhaps useful

to refer to the example of a machine instruction statement in Fig. go?, in

11-e

which the operation and operand fields were "'LR L 3'" * (It was notci in

the description of the figure that ~.ZLLr r-~&ion of this instruction would cause

the contents of di’7 to be replaced 'by ax cp cm tenl%E- ol.2 R3 * ) &: shis C24Bd,

"rl" is "7" and "r2" is y' ,, .4) . 1 ,.IIn -if% r-: :I ~ i; i::: ,xy,.,:t ju$.i_cp 1:'~ Ly!$ yz ]gu.s$ sj.qy~,lLy

be absolute (i.eey non-relGca%ablej -~*.~-~*~.inne: (7sf value less than 16; a-^J.L~"L~~

more formal definition of the tie~ti~= ",: J .c+G~M~~' will by givei1 shortly9

Thus, we could ,just as well have wri::-ken LR X'7',B'll' in this

example. For RR instructions, the va'.r,.~es of the expressions in the operand

field are placed by the Assembler into two adJacent hexadecimal digits,

called operand register specification digits, in the second byte of the

instruction (which was labeled "Register Specification" in the first diagram

of Fig. 4.2), as in the following f'ig;ttre. _

Figure 11.1 R!3 Instruction Showing Register Specification Digits

The subscripts on the quantities "rl" and "r$ are simply a way to distinguish

which operand is being referred to; in general we will find that using the

terms "first operand", '*second operand", etc. in a consistent manner will

help in remembering what actions are being performed by each instruction. '

We would therefore say for most of the RR instructions that the operand r~

specifies the register con-tainil:g the "first operand". It will become

apparent that the word "operand" is ustid here in two different senses: as

part of the operand field entry of some instruction statement, an operand is

an expression which will eventually be-translated by the Assembler into

some part of an instruction; we also call an operand one of the quantities

in a register or in memory which at execution time participates in the given

operation. The difference is not terri.bly important but can be confusing,

and which is meant will normally be clear from context. Thus the operands

(first meaning) in the operand field entry of the instruction LB L3

are 7 and 3, whereas at execution time the operands (second meaning) of the

IiR instruction will be found in general registers 7 and 3. Using Table IV

to find that the operation code corresponding to the mnemonic ZB is l&s,

the two-byte instructionwhich would be assembled from the statement as

given would be fi.i.l in hexadecimal.

For the case of the SIM instruction the digit labeled r;! in Fig. 11.1

is ignored when the instruction is decoded; and for the SVC instruction,

the entire second byte of the instruction is occupied by an &bit number

which is specified by the absolute expression "I", as indicated above,

Thus sm 14 and svc 2'35 are acceptable forms of each instruction,

in which decimal self-defining terms are used for the operand field entries.

Before discussing RX format instructions, we will discuss in more

detailthe complexities of what is meant by an "expression". Since most of

the material of the next several pages will be illustrated in fairly simple

examples to be given later, it is not important that some of these conventions

of Assembler Language remain unclear for now.

An expression is an arithmetic combination of terms (and we will also

give a definition of the term "term") which can be evaluated by the Assembler

to produce a meaningful value for the operand. Mathematical operators allowed

"indude f, -> Jc, and /, indicating addition, subtraction, multiplication,

and division respectively; the rules used in performing these operations are

described below4 The quantities used as the basic elements of an expression

are terms, which can be one of the five following items:

a self-defining term (absolute);

a symbol (absolute or relocatable);

a Location Counter Reference (relocatable);

a literal (relocatable);

a Symbol Length Attribute Reference (absolute).

&ch of the latter three will be described later. An expression using a

symbol and a self-defining term is GETCfiNSTiX'4A' and an expression

using only self-defining terms is X'12'+C'.' -B'1010001'+7 which the

reader -can verify to have the value 1910.To illustrate the definition of an absolute symbol (up to now we

have illustrated only the use of relocatable symbols), we will make briefmention of the E&U assembler instruction: the assembl.er instruction statement

"8ymbol EQU expression" gives to the symbol in the name field the attributes

u-4

(including value and relocatability) of the expressionin the operand field.

Thus the statement

AI&25 E&U 425

serves to define an absolute symbok crith -Q~~I.IA.~ k510, (This is the unusual

case mentioned in Section LO COCCYX tk ~G.ue of the symbol is not the value

of the Lx: when the symbol was encountered.)

Parentheses in an expression may be used, as in ordinary mathematical

use (and as in algebraic procedural languages such as FORTRAN, ALGOL, and

PL/l) to indicate groupings. As one might suspect, an expression may not

contain two operators in succession; a less familiar restr$ction is that an

expression may not begin with an operator, SC that -5+ABS&5 is invalid,

whereas 0-5+ABs425 is correct. (The maximum number of terms allowed and the

maximum level of nesting of parentheses in an expression both depend on the

size and sophistication of the Assembler; we will simply mention an upper

limit of 16 and 5 respectively, corresponding to the os/360 Assembler.)

__ Expressions

With these notational matters more or less in hand, we can now state

the rules for evaluation of expressions.

1. Each term is evaluated to fullword accuracy, namely 32 bits. The

relocatability attribute of each term is noted.

2. Parenthesized subexpressions are evaluated first, and the resulting

value used in computing the value of the rest of the expression.

Thus in the expression (XE100'+2*(ABS425-420))+1 (where AR&25 is

assumed to have been defined as above), the value of (ABS425-420)

would be evaluated first.

3. As is the case in procedurallanguages, multiplications and divisions

are done before additions and subtractions. Thus the value of the

expression just given would be evaluated as (X'lOO'+(2*(5)))+l and

not ((X'lOO't2)*(5))+1. Note that relocatable terms or subexpressions

may not occur in multiply or divide operations.

lb5

4.

5*

6,

L

8.

9*

--

Qerations are performed in left-to-right order. Thus 5*2/k means

(5*2)/4, not 5*(2/4h

Multiplications yield a 320bit result whichis the low-order half of

the double-length product; thus significant bits can be lost if the

product is too large.

Division always yields an integer result; remainders are discarded.

Thus 5*2/b has the value 2, and 5*(2/k) has the value 0. Division by

zero is permitted, with the result simply being set to zero.

Negative quantities are carried in standard two's complement representation.

When the expression has been ccmpletely evaluated, it is truncated to

the value contained in its rightmost 24 bits, which is then considered

(as was noted for self-defining terms) to have a positive value, even

though the bits dropped off may have all been ones.

The relocatability attribute of the result .is found as follows: if

there is an even number of relocatable terms appearing in the expression

in such a way that they are paired (that is, they appear with opposite

signs) so that a change in the relative origin assigned to the program

has no effect on the value of the expression, then the expression is

absolute. If there is one remaining unpaired term not directly

preceded by a minus sign, then the expression is relocatable and has

the relocatability attribute of the unpaired term. (Numerous examples

will be given later, so don't worry if this seems obscure at present.)

After this somewhat lengthy digression, we return to the problems of

writing actual machine instructions by noting that the machine instruction

example at the beginning of the chapter could have been written

L&D LR c'45'-(7*~'2A36')+ABS425*B*Ul'-235,18/(Q-Q)i-3

though the gain in clarity is not obvious. A somewhat more reasonable usage

might be as illustrated in the following sequence of statements.

R7 EQU 7

R3 EQU 3

@-AD L R R7, R3

11-6

Note that there is a difference between (1) the notational convenience “R7”’

(meaning general register 7) introduced in Section 3, (2) the definition of

an absolute symbol R7 to have the va:iue '7, and (3) the of the symbol as

an operand in the operand field entr> .J? m mnchine instruction where the use

of register 7 is indicatedn The above example is entirely equivalent to

the two below.

Z$RCH EQU

ZILCH EQU

L#AD LR

Just to show

3 x7 EQU 3

7 R3 EQU 7

ZILCH,Z@RCH L#AD LR R3,R7

that programming with RR instructions is in fact quite

simple, suppose that at some point in a program we wish to add the contents

of R2 to R14, subtract the contents of Rg frcm the sum, and leave the result

in RO; the following three statements (whose properties will be discussed

later) would suffice:

m 0,2 M@E C@TENTS @F R2 Tpj R@

AR 0,14 ADD Cj&TENTS $I? Rl4-.

SR 0,9 SUBTRACT C@KKENTS @F RS‘

RX Instructions

RX instructions are given in Table V. As was the case in Table IV,

not all of the available digit combinations are used as actual operation

codes; and all of the instructions in the right-hand column again refer to

operations on the floating-point registers and will be discussed later.

None of the RX instructions is privileged, and the format of the operand

field entry is the same for each. It should be kept in mind that RX

instructions always refer to memory in scme way. Referring to Fig* 11.2,

we see that four quantities are to be specified -- the operand register

specification digit rl, the index register specification digit x2, the base

register specification digit b2, and the displacement d2. (We are again

entering on a fairly technical discussion, the details of which need not be

assimilated at this point, since many later examples will be given in

illustration of the various possibilities.)

11-7

tOpcode r1 x2 b2 d2

0 78. 16"

11 12 15 19 20 31

Figure 11.2 RX Instruction Showing Register Specification Digits

Opcodeihex) Mnemonic Instruction

40 STH Store41 LA Load Address42 STC Store Character43 IC Insert Character44’ Ex Execute45 BAL Branch and Link46 BCT Branch on Count47 BC Branch on Condition48 LH Load49 CH4A AH

CompareAdd

4B SK Subtract4-c MH4E

MultiplyCVD Convert to Decimal

4F CVB Convert to Binary50 ST Store54 N Logical AND55 CL56 Ib

Compare LogicalLogical fdR

57 x58 L

Exclusive (dRLoad

59 C Compare5A A Add5B S Subtract5C M MultiplySD D Divide5E _ AL Add Logical5F SL - Subtract Logical -

Opcode(hex) Mnemonic Instruction ._

z696~6~6c6~6~6~

STD StoreLD LoadCD CompareAD AddSD SubtractMD MultiplyDD DivideAW Add UnnoraalizedSW Subtract Unnomnalize

70 STE78 m79 CE7A AE78 SE7c ME7D DE73 AU7F su

StoreLoadCompareAddSubtract \MultiplyDivideAdd UnnormalizedSubtract Unnormalize

TABIJ3 V.

RX Instructions

There is quite a variety of ways in which the operand field entry of an

RX-type machine instruction statement may be written, but they all eventually

must yield values for the four needed quantities. Rather than give all the.

11-8

forms for the operand field entry immediately, we note first that it is of

the general form

rl,<address specification>

where <address specification> will be discussed shortly. The operand register

specification digit rl is formed according to the same rules given above 8

for the rl and r2 digits of RR instructions: it must be an absolute expression

of value less than 16.

Suppose first that we wish to specify explicitly the values assigned

to x2, bp, and d2: this is done by writing the second operand (namely

<address specificati0r-P) as

dcdxdd -

For example, the instructions in examples 3, 4, and 5 of Section 5 (page 5-3)

could be written (giving both the assembled form and the operation and

operand field entries of the machine instruction.statement) as in Fig. lL3.

1431OAI 714681 I C-. 0,x1468’ ( 10,~)

~43lool7(468) IC 0,1=8(0,7)

143107lo14a~ IC 0,1=8( 7,0>

Figure 11.3 RX Instruction with Explicit Operands

In the last of these three examples, we could have written the second operand

as.U28(7) and the Assembler will give the omitted item (the base r@ster

specification digit be) the value zero.

As was mentioned in the discussion-of addressing in Section 5, the use

of the index register specification digit x2 when the base register specification

digit b2 was intended can lead to programs which function more slowly,

though correctly. By specifying only the base digit when no indexing is

intended, the program is both more efficient and more easily understood --

the second of the above examples, where we could have written 1~8(,7) also,

is therefore preferable to the third.

11-g

!k utility of the Assembler becanee mire .apmrent when we considerall the forma in which the eecond operand of an RX instruction may be written;these tare @en in Mg. 11.4 below.

- --l&~lici$ Address

da(xa,ba)d2b2)did rho)

l&Wed Address

82(x2)

82

Figure 11.4 Addresrs Specification in RX4Qpe Inrtructionr

‘IQ the three caaea tthere an explicit address is desired, each of the

quarrtitiecl da, lip, and bg (where epecified) must be an absolute exprerrion;IQ and be, like rl, must have value less than 16, and da must have valuelees than or equal to m;lo = m16. Rote that the second and third formsof explicit address implicitly specify bg = 0 and xa * 0, respective&y, aa

lndicatid previouely l

-- Ih the two case8 where an implied address is desired, the quantity 80may be either an absolute or a relocatable expreeeion of value lssr than 244.!Phie means that we may write instructiona such aa L 0,ANWER and leaveit to the Assembler to ccrmpute the proper base and dieplacement; hw thisis dt%e will be diecuased in the next section. For the munent auppore thak

the Aaeembler has eufficient information BO that the instruction TC OJmmie translated into pmq as in Fig. 11.3. 9?hen if the index regifsterto be used is RlO, the insitruction IC O,ByTE(lO) would be translatedinto mwT .

This is the- same instruction used in example 3 in section 5; the

example given there wae erimply meant to illustrate an address aalcutition

at execution time rather than (as above) the method used by the Arrmbler

to specify the base and index digits. We will find that the moet crmmrm'means -OS address specification in simple prwramr is through the use ofimplied addresses, where the Assembler computes the proper displacement for ~8.

To give a simple example of a sequence of statemerits which increment

by one the fullword integer stored in memory in an addressable area

11-10

named by thr, symbol N, we couLd use the fo&~Wing:

L O,N L#ADFR@MN~RoA O,@E ADD INTEGER C#NSTANT 1

ST 0,N ST@E RESULT BACK AT N

where it is assumed that an addressable fullword area named j&E which

contains the integer constant 41 has been defined in the program. We will

see later that there are several ways to define such constants.

R$ and 81 Instructions

' The R&type and SI-type instruction6 listed in Table VI are somewhatvaried both in application and in the ways in which the operand fields are

specified. Note that there are nine privileged instructions: $SM, LPSW,WRD, RDD, SI@, TIfi, HI@, TCH, and “Diagnose", for which there is no mnemonic0

Opcodehex) Mnemonic Instruction

80 SSM82

Set System MaskLoad PSW

8384

DiagnoseWrite Direct

82 RDD Read Direct86 Branch on Index High

87 Branch on Index Lowor Equal

88 SRI; Shift Right SL89 8LL Shift Left SLa Shift Right S8~ SLh' Shift Left S8c SRDL8~ -

Shift Right DLSLDL‘ Shift Left DL -

8~ SlIDA Shift Right D8~ SLna Shift Left D

Cpcode

90 STM91 TM92 Mv3t93 TS94 NI95 CLI96 PlI97 XI98 LM

9c srld9D Tra9E HU9F TCQ

Store Multipl@Test Under Ma&MweTestand SetLogical ANDCompare LogicalLogical @RExclusive #RLoad Multiple

start x/j4gkist x/qHalt X/lTest channd

TABLE VI.

RS and SI Instructions(For Shift Instructions, S = Single, L = Logical, D = Double)

Bince the operand fields of RS and SI instructions cannot be deeclribed in aa

uniform a way as was possible for RX instructions, the detaila will be left

11-11

to the discussion of the individual instructiona. A simple example of an SI

instruction is MVI .FLAG,O which would cause the bylz named FlX.G

(which is assumed to be addressable) to be set to zero.

.SS Instruction6

The instructions of SS type are given in Table VII. There are no

privileged SS instructions. As was the case for the RS and SI instructions,

diecussion of the operand field formats will be deferred. The last 6i.x

instructions in the right-hand column ax-6 decimal instructions, which operate

Wof$(hex) Mnemonic Instruction

IIDlII2D3D4

m

D6

D7 *

DC

DD-DE

I)tF

MVC

NCCIC95cXCTR

ED

Move NumericMoveMove ZoneLogical ANDCcezpare LogicalLogical @RExclusive @RTranslateTranslate and TestEditEdit and Mark

Opcode

*I

F8 ZAP Zero and AddF9 CP CompareFA AP Addm SP SubtractFC MP MultiplyFD Dl? Divide

TABLE VII,

ss In6truction6

on data which is stored in a different format (called packed decimal) from

tbat’demcribed earlier for fixed-point integers in two's complementrepresentation; decimal instructions will be treated later. An example of

an 56 instruction which would cause five bytes'to be moved from a memory area

named m to an area whose first byte is named FIEXD is

MUC FIELD(5),AREA l

To conclude this short presentation of the instruction repertoire ofSystem/360, a mmnary is given in the figure below of scme of the ove~ll '

characteristics of the instructions as they depend on t.he firat four bits

of the operation code. As was illustrated in Section 4, the first two bits

I lb12

A closer examination of a complete table of operation codes reveals a great

deal of symmetry in the specification of the codes used for similar functions.

For example, the four instructions which perform the Logical AND operation

(namely, NR, N, NI, and NC) all have operation codes in which the second hex

digit is 4 and the first hex digits differ by multiples of 11 (namely, 14, 54,

94, and &). Since we will make reference to instructions shaost entirely by

use of mnemonics, these details are on&y of passing interest for our purposes.

The reader who is interested in a broader discussion of these topics --

collectively known as system architecture -- should consult the IBM Systems

determine the type. and length of the instruction. The second pair of bits

determines (depending on the instruction type) the operand length or the

general functions performed by the instructions.

FirstSecond Bit Pair

Bit Pair 00 01 10 11 . -

00 Branching and Fullword Fixed- Floating- Floatfng-m Status Switching Point and Logical Point Long Point Short

01 Halfword Fixed- Fullword Fixed- Floating- Floating-(rar) Point and Branching Point and Logical Point Long Point Short

.

10 Branching, Status Fixed-Point,O@SI)

Switching, and Logical, andShifting Input/Output

11 Logical lkcimal(ss)

c

Figure 11.5 General Instruction Classification

Journal, Vol. 3, Nos. 2 and 3, and the IBM Journal of Research and Develoment,

vol. 8, No. 2.

12. ESTABLISHING AND MAINTAINING ADDRESSABILITY

In this section we will give an exposition of scme simple methods for

providing addressability for a program, and how the Assembler makes use of

some programmer-provided information to calculate displacements. Rather

than give a set of rules and show how they work, we will start with what we

want and work backwards to some techniques which can be used to get it.

One particular instruction is central to the discussion, namely BAIR.

For the time being we will be interested -only in the situation where we

write BALR r1,O (so that the second operand register specification

digit r2 is zero). The effect of this instruction when executed is to

replace the contents of general register rl by the rightmost 32 bits of the

PSW: the ILC, CC, and Program Mask occupy the leftmost byte of the register,

-- and the rightmost 24 bits contain the value of the IA (which will be the

address of the instruction following the BALR, because the IA is incremented

by the instruction length (2 for BALR) during the Fetch portion of the

instruction cycle). This is one solution to the problem posed at the end

of Section 5, where addressability was first discussed; the BALER instruction

gives us a way to find out where in memory a program is located.

Suppose that the following short sequence of statements is part of a

program which is in memory and ready to be executed, and assume for the

moment the Supervisor has relocated the program so that the first instruction

(the BALR) happens to be at memory location 50001s.

Location Name Operation Operand

5000 BAm5002 BEGIN L ,",::5006

L#AD C@?TENTS @F N INT# R2A 23NE ADD C@TENTS #F #NE

500A ST 2,N ST@3 C@TENTS (dF R2 INT# N--- twenty-two additional bytes of instructions, data, etc. ---

5024 N DC F'8'5028 (d

FUW@RD INTEGER 8NE DC F'S FULI-@3D INTEGER1

Figure 12.1 A Simple Program Segment

12-l

Some explanation oftbe items in the e~amplkmaybe belpfU. gbs inetmtlons

L, A, and S!I! respectively (1) put the contents of a fullwold h m

into a general register (i.e., Load the register), (2) Add thy c~ntenCe a9

a fillword area in memory to the contents of a registerxnd (3) rq&aoa

the contents of a fullword area in memory wi!h the contents of GI p~&rsml ,

register (i.e., STore the register). The DC statement% tiich are treated

in the next section, are meant simply to provide two fM&#ord ereas of

memory with names 'N" and "@!IE" which contain the fUlworQ integer values

desired; we have arbitrarily set the contents of the f'ullword at N to t&z

integer 8 even though in an actual program any value might be possible.All of these instructions will be covered in detail later.

When the program has begun and after-the BALB has been executed, R6will contain xxO@O(&& where xx stands for two hex digits whose value8

are of no concern at the mcznent. To determine the proper displacement for

the L indzmtion at 500&6, we can use the knanri contents of R6 (einc6the xx digits are ignored in address ccrmputations) to compute a displacement

of 5a416 - 500216 = CQ2+; then the assembled machine instruction (using

the operation code 58 for the mnemonic L) should bewhen the instruction.is executed, the computation of the effective add@e$e

yields or22 + 005OC2 = 003024, which is what we want. ff we contlnued hthis fashion for the rest of the instructions, we would find that the

following "assembled" quantities in the indicated locations wap2La give t&?

desired results.

bxatw Assembled Contents Original Statement

5000 0560 BALR.

6,O5002 58206022 BEGIN L5006 5~206026

A5(33A 5-

%ldNE w

ST 2,Nr-r~rCll~~rrrrrr-r-r~---m-~--~~-~~--

5@4 N DC F'8'5=@ XKUXWOl #NE DC F'l'

'1pig\u‘e 12.2 Skple Program Segment with Assembled Contents

32-2

So far, so good: we have constructed a sequence of statements which

will give a desired result if it is placed in memory at the right place.

It is natural to ask at this point what would happen if the program had

been put elsewhere by the Supervisor. So, assume that the same program

segment begins at 843816, as in the figure below.

Location Statement

843884~~

BALR 6,0BEGIN L 2,rJ

84m A84~2

2,@!zST 2,N

--- the same 22 bytes of odds and ends ---*85oc N DC F'8'8510 ldNE DC F'l' -

Figure 12.3 Same Program Segment, Different Memory Location

Now, the contents of R6 after the BALR is executed would be xxOO84EA~e. To

access the contents of the fullword at N, using R6 as a base register, the

-- necessary displacement is 850~ - 84~~ = 02216 (as before!) and the dis-.placement necessary in the A instruction is 8510 - 84~~ = 02616~ Thus

the assembled program would appear as in the figure below.

Location Assembled Contents

8438 056084~ 5820602284~~ 5~20602684~2 50206022

Wm.-------------1850~ 000000088510 00000001

Figure 12.4 Same Program Segment with Assembled Contents

The identical assembled program would be used in each case to perform the

desired calculation. It therefore appears that so long as the same fixed

relationship is maintained between the various parts of -the program segment

(namely that there be 22 bytes between the ST instruction and the fullword

named N, and that N and @YE name areas that fall on fullword boundaries, the

. segment could be placed anywhere in memory and still execute correctly.

12-3

This is because the displacements of the khree RX-type instructions were

calculated on the assumption that at the time the program is executed.there would be an address in R6 (namely the address of the IL XnsCruction

named REXXN) which could be used for a base address. hdeed, we could

have assumed that the program began at momory location CWQ (evea though

an actual program would not be placed there) because the contents of R6

after the RALR would then be xx000002 and the displacements would be

calculated exactly as before. In the first example, the actual origin of

the program segment was 5OOOl6; we could by chance have assigned that value

as a relative origin in the program and had the values *of the Assembler's

Location Counter correspond identically to the actual locations later

assigned by the Supervisor to each instructions In that case, we would

need to inform the Assembler that the quantity to be used as a base is

500&, and that it would be found in R6 at execution time. Similarly, in

the second example, the relative origin would be 8438316, and the contentsof R6 that the Assembler should assume in order to calculate the correct

displacements would be 84EA16. If the value, of the actual origin is,assigned to the relative origin by the programmer, and if the Assembler

knows that the contents of R6 at execution time willalso be the value of

the symbol REGIN , then the correct displacements kill be found.' However,

in each of the above examples, the computation of the displacements actually

depended not on a knowledge of the actual locations of the instructions

at execution time, but only on their locations relative to one another and

on the value assumed to be available for addressing purposes. Thus, the

technique used is to assign a relative origin for the program, and then to

give some value relative tothat relative origin which may be used for

ccanputing displacements; although this seems, complicated, we will find it

quite simple in practice.

The assembler instruction which provides this information is the

USING instruction. It is written

USING sjrl

where s is a relocatable or absolute expresrsion (usually just a symbol.

will be used) whose magnitude is less thati 224, and rl is an absolute

12-4

expression of value less than 16 which specifies the register to be used as

a base. (As usual, there is more to using USING than has been stated here,

but we will use this simplified explanation for the time being.) Thus, the

statement USING BEGIN,6 would inform the Assembler that register 6 may

be assumed (for purposes of computing displacements) to be a base register

which will contain the value of the symbol BEGIN . We could rewrite the

sample program segment to include the USING statement as in the figure below.

BALK 6,oUSING BEGZN,6

BEGIN L 2,NA ?,@JJEST 2,N

-----------l-------l_cN DC ~‘8’aNE DC F'l'

Figure 12.3 Program Segment with IJSING Instruction

-- If the relative origin assigned by the programmer is zero, the value of theIsymbol BEGIN is 2, and the values of the symbols N and @NE are 2416 and

2816 respectively. To complete the addressing syllable of the ST instruction,

the Assembler need only note tha-t the difference between the value of the

symbol N and the value that the USING instruction specifies will be present

in ~6, is 24 - 2 = 2216; this is the required displacement. It should be

noted at this point that the value provided by the USING statement must

allow the Assembler to compute a legal displacement. If the calculation

yields a negative value or one greater than 4093, the location referred to

by the-symbol in question is still not addressable, and further steps would

have to be taken.

Two important features of the program segment in Figure 12.3 should

be noted. First, the USING instruction does absolutely nothing about

actually loading a value into a register; it merely tells the Assembler

what to assume will be there when the program is executed. Second, if the

BALI3 instruction had been omitted, there is no guarantee when the program

is executed that the correct effective addresses will be computed. The

example below will help to illustrate this.

x2 -5

Suppose an error had been made in punching the 'card with the L

instruction, such that it appeared

BEGIN L 6,N I&AD C@YTENTS @F N TNT# R2

(the first operand was incorrectly punched as 6 instead ot' 2). The

assembled program would then appear as ?n ~gure I.ZL~~ assuming a relative

origin of 0 had been assigned to the BALR instruction.

Location Assembled Contents Statement

0 0560 BAJX 6,oUSING BEKXV,6

2 58606022 BEGIN L 06 5.~206026 A 2, ME "A 50206022 ST %N-----L----III--c--cI-----------------"--------24 00000008 N DC F'8'28 00000001 PlrsE DC F'S

Figure 1.2.6 Sample Program Segment with Erroneous Statement

It is apparent that thfs program will assemble correctly, as did the one

in Figure 12.5, since all quntities- are properly specified. However, atexecutiontime, things go rapidly awry. Suppose again that the actual

I' lWation assigned by the Supervisor to the ,MrjR is 5OOOl6, so that when the

L instruction is executed, R6 contains x~O~OO216. Now, the L instruction

transmits a fullword from thk memory location at the effective address given

by the second operand into the register specified by the first operand,

'which in this case is R6. When the effective address of N is being calculated,

R6 will contain the correct base addreaa; but when the execution of the L

instruction is cC#nplete, the contents of R6 will have become 00000008~~~ and

not xx005002 When the next instruction is executed, the effective address

calculated is 26~~ + 8~6 = 00002E16 and not 5028~~, which is where thedesired operand is to be found. In this case, the generated effective

address is not divisible by 4, so that it refers to the incorrect byte of

the required fullword operand; hence a specification exception occurs, and

remedial action can be initiated immediately. This does not by any means

imply that at any time we have the misfortune to destroy the contents of a

base register that the CPU will be able to detect the error. Indeed, if

the contents of the fullword at N had been the integer 2 instead of 8, then

the effective address would have been computed to be 2 + 26 = 2816, whichis a perfectly acceptable address for a fullword. The subsequent instructions

would thus have gone their way, adding the contents of the fullword at

memory location 2816 to ~2, and storing the result at location ~J+LE,;, which

is obviously not what is intended. It is partly a matter of chance as to'

how much further damage such a program error can cause when the program is

executed; indeed, when the CPU finally (if it ever) detects an error, all

evidence pointing to the offending instruction may have been lost (R6 may

have been changed several times!), making error tracing difficult. Thus

the programmer must take care to insure the integrity of the contents of

registers being used for base registers, -since the Assembler makes no checks

for instructions performing operations on registers.designated in USING

instructions as base registers. This warning should not be taken lightly;

the errors caused by mishandling base registers are among the most

destructive of program continuity and the most difficult to find.

There is one further method in common use for establishing addressability,

which is simply to require that when "controvt reaches a certain point in

the program (where a specified instruction is about to be executed), an

agreed-upon address be in an agreed-upon register. Thus if the program

segment used in the above examples were part of a larger program, we could

then require that at any time that control reaches the statement named

BEGIN, the actual address of that instruction must be in R6. Then the BALE3

could be omitted, and the USIEG instruction would specify that R6 may still

be assumed to contain the correct value. The problem of how one part of a

program knows where the others are, so that it can pre-load the correct

address into the agreed-upon register, will be discussed later; the solutions

to this problem are basic to the use of subroutines, which is an important

programming topic.

In many of the following sections we will have occasion to examine

short segments of codini; :5M.ch illustrate the use of various instructions.

Rather than indicate explicitly the assignment of a base register and its

contents, we will assume that each segment is part of a larger program in

which addressability has been taken care of. We will also assume that all

symbols used have been defined and are addressable, and that the base register

is different from any registers used or changed in the example

12-7

13. CONSTANTS, STORAGE AREAS, AND LITERAIS

In several places in the preceding sections we have made occasional

use of the DC assembler instruction to indicate that a constant was to be

constructed and placed in the program by the Assembler (DC is a mnemonic for

"Define Constant"). In this section we will elaborate on the definition of

constants and describe a technique which simplifies their use.

As indicated insome of the examples given previously, the DC instruction

may have name, operation, operand, and comment field entries, of which the

operation and operand field entries are mandatory. Since the comment field

entry is optional, its use will be ignored in the following discussion.

-- Rather than give all the rules for defining constants immediately, it is

the principles- perhaps simpler to examine a few simple cases which illustrate

involved.

The statement DC F'8' defines (as stated in a number

examples) a fullword integer constant of value 8x0 placed on aboundary. That is, four items have been specified:

(1) the value of the constant (in this case -f&o)

of earlier

fullword '

(2) the type of internal representation to be used for the given

value (in this case two's complement integer);

(3) the length of the-constant (in this case four bytes); and(4) the alignment in memory of the constant (in this case on a

fullword boundary).

Because the Assembler does no placing of data in memory, it is probably

difficult to see at present how a given sequence of four bytes can be placed,

after processing by the Assembler, Linkage Editor, and Resident Supervisor,

on proper boundaries. We will see that there are a few simple conventions

which make this easy to accomplish. Some other types of conversion we will

13-a

discuss here, and the letters which specify/the types/are Character (C),

Binary (B), Hexadecimal (X), Halfword fiteger (II), and Address Constant (A).

The first three of these were encountered in the treatment of self-defining

terms, and their use 5n the DC instruction is quite &mKI.ar.

For the larger System/36O Assemblers, the operand field entry may '

consist of a number of operands which. are separated by commas; however, for

most of the cases which will be of interest, a single operand will suffice.

There are four parts to an operand: (1) a duplication factor, (2) a letter

specifying the type of representation, (3) modifiers, and (4) the value of '

the constant or constants. Of these only the second (type) and fourth '

(value) are requfred,I

as in the example above where, F'8." was specified.

The duplication factor is a reJlatively simple concept which will be treated

shortly. There are three types of modifier, namely length, scale, and

exponent, of which only length wili be treated here. Because there is an

important relatlonshSp between boundary alignment and the' use of a lengthmodifier, we will discw~ the techniques tied to obtain the proper alignment

of constants and data.-- When the relative orclgin is specified by the programmer at the start

of his program, the Assambler c&&s-whether the value given is exactly

divisible by eight; -%I? not, it is 'rounded up" to the, next larger multiple

of eight, which Is then used as the relative origln of his program. Thus

the Assembler insures that the program begins with the most restrictive

possible boundary alignment4 Then if a constant is defined which must fal3

on some particular kind of word boundary, the Assembler need insure only that

,its Location Counter be divisible by the proper power of two (that Is, by

2, 4, or 8) at the 1ocatlon of the leftmost byte of the constant. TheLinkage Editor and Residen%&pervisor 'must then respect this assumed*alignment for the begi.nnlllq3 of the program; this ensures that data and

Instructions will fall on tha proper boundaries when&aa program is finally

loaded into memory for execution. We will of course assume that this is

exactly what happens in the rest of our discussion; sane of the lmplicatione

of this method of handling programs will be treated in later discussions :

which give more details of the processes of linkage editing and loading.

13-2

We must now investigate what it is that the Assembler actually does to

ensure that its Location Counter is indeed divisible by the desired quantity.

Suppose in some program that after a sequence of instructions has 'been

processed the value of the LC is 12&e, so that if another machine instruction

were assembled at this point it would begin on a halfword boundary betweex

two fullword boundaries (recall that instruction addresses need only be z

divisible by 2). Suppose also that the next statement is not a machine

instruction statement but is Ix F'8' instead. To assemble the four

bytes representing the constant (namely 00000008& beginning at 12&e would

be incorrect, since an instruction which referred to the constant might

require that its memory address be on a fullword boundary. To avoid such

an erroneous situation, the Assembler will automatically skip enough bytes

to obtain the desired boundary alignment. Thus in this simple example the

LC would be increased to 13014 before the fullword constant is assembled

into the program, and the LC would have a value of 13416 after the constant

is processed rather than the value of 13216 which would be the case if no

automatic alignment had been performed. An automatic alignment is not--

performed in the following circumstances:

1) it isn't needed (that is, the LC happens by chance to fall on

the desired boundary); or

2) the type of constant specified doesn't call for it (which is

the case for types C, B, and X); or

3) a length modifier is present.

A length modifier allows the programmer to specify the exact length of

a constant, and is written immediately following the letter which specifies

the data type, in the form .

Ln

where n is either an unsigned decimal self-defining term, or a positive

absolute expression enclosed in parentheses. For example, the statements

DC FL3'8' and DC FL(2*4-5)'8'

would both cause the constant 000008 16 to be assembled beginning at the

value of the LC when the EC statement was encountered; no boundary alignment

13-3

4 *

is performed. Because alignment is automatic w when the length is implied

(that is, no length modifier is given), the two statements

DC F'8' and DC ~~4'8'

while defining the same constant may give different results since the former

ie autaatically aligned and the latter :i.s not. (As usual, there is

occasionally a little more to the use of a length modifier than is stated

here, but what has been cmitted, namely, bit-length specifications, will be

of no importance or interest until later.)

One further effect of automatic boundary alignment occurs when a

symbol appears as the name field entry in a DC assembler

Suppose as before that the value of the IX: is, L2E16 when

statements is encountered.

I IMPLIBD DC F'8'

I EXPLICIT DC FL4'8.'

instruction statement.

each of the following

Figure 13.1 Implied and Explicit Length Specifications--

Because no boundary alignment is performed in the latter case it is clear

that the value of the symbol EXPLICIT will be 12E16. In the former case,

however, two bytes must be skipped by the Assembler to achieve the required

boundary alignment Implied by type F. Since we will want to be able to

refer to the constant by using the symbol JMPI;IED, it is also clear that it

should have the value given to the location of the leftmost byte of the

conetant, namely 13016. Thus if a symbol is to be defined, it is given its

value after bytes are skipped to achieve boundary alignment. In fact, ageneral rule may be stated: the Assembler will never automatically assign

the value of a symbol to the location of skipped bytes. (The programmer can

find ways to do so if he is so inclined.) This includes the case where a

byte must be skipped to ensure that an instruction begins on a halfword

boundary. When bytes are skipped to achieve alignment of a following

constant.or instruction, the Assembler will insert zeros into the bytes

skipped.

13-4

We are also in a position now to describe the length attribute of a

symbol, which was first mentioned in Section 10. If a symbol appears in

the name field entry of a DC instruction, then the length attribute of the

symbol is the length in bytes of the first constant assembled. (Cases where

more than one constant may be assembled will be treated shortly.) Thus in

the examples in Figure 13.1, both symbols have length attributes of 4; and

in the machine instruction statement given in Figure 9.3 the length attribute

of the symbol L@AD would be 2, since LE? is an RR-type instruction of length

two bytes.

A duplication factor (sometimes called a multiplicity, replication, or

repetition factor) specifies the number of times the constant is to be

duplicated, and is written immediately preceding the letter which specifies

the constant type. It may be either an unsigned decimal self-defining term,

or a positive absolute expression enclosed in parentheses. For exam'pie,

the statements DC 3~~8' and D C (3/2+1)~!8* are equivalent

to writing the statement DC F'8' three times in succession. And

-- because more than one operand may (for the larger Assemblers) be written

in the operand field entry of a DC instruction, we could also achieve the

same result by writing DC F’8’,1?‘8’,F’8’ . There is still one more

way of defining multiple constants (again, for the larger of the System/360

Assemblers) which we will mention after discussing some of the other types

of constants which will be of use in future examples.

The type H constant is quite similar to type F, in that two's

complement integer conversion is specified. The only difference is in the

default values assumed for length and alignment, which assign a half'word

integer to two bytes aligned- on a halfword boundary. Thus the s?:atement

DC H'-10' would cause the constant FFF61e to be assembl i and

placed on the next available halfkord boundary. If an explicit length is

given, there is no difference between constants of types H and F, so that

~~3'8' and ~~3'8' are for all practical purposes identical

operands.

The following discussion deals with numerous technical matters in a

fairly loose way -- rather than give explicit rules at once we will continue

to use examples to illustrate the problems involved. The rules will be

summarized in a short table at the end of the‘section.

13-5

‘The three useful constant types C&*X, and B differ from F and H in that

no default values are assumed for either length or alignment. For example,

the five bytes required to store the constant generated by the statement

DC C’l.2345’ will be placed by the Assembler at the next ;~vailable

address given by the current value of the U. If a particular boundary

alignment is desired, extra steps must be taken which will be described later

in this section. The method of writing such constants is, as might be guessed,

the same'as for writing character, hexadecimal, and binary self-defining

terms, except that the limitations on length and value are different. In

the case of self-defining terms, the value of the tenm was restricted to

being less than 224, whereas much longer constants can bei defined with the

DC instruction. Thus one can define constants in statements such as in

Figure 13.2 below.

TITUE DC C'THI~ IS A @NG c3IA3IAcTER c@STArWDIGITS DC x’862AFcBg~310’

-- Figure 13.2 Examples of Character and Hexadecimal Constants

In the discussion of data converted according to types F and Hit was

reasonable that the resulting binary numbers should be placed with the

least significant digit at the right-hand end of the desired storage areai

and that the sign bit should be extended to the left. In all the examples

given, the constants were small enough to fit safely in the allotted sgace.

The problem may arise as to what should be done if (1) the constant is too

small to occupy fully the number of bite allocated for it by the length

specification (whether an explicit length modifier or the default length is

used), or if (2) the constant is too large to fit in the allotted space.

Scme examples of such cases are given in Figure 13.3, along with the

constants actually stored by the Aasembler. The rules used to determine

the final values of the constants are given below.

13-6

Constant Assembledtoo Large Value

~‘65537’ 000116

FLl'-300' D416

CL3'SMITH' E2D40916

XL2’56789’ 6789~BL1'100100100' 001001002

Constanttoo Small

H'2'

FLY-6'

CL3'S'

X’56789’B'lOl'

AssembledValue _

ooo216

FAX

E2404016

0567891,000001012

Figure 13.3 Examples of Truncated and Padded Constants

Forall of the constants on the left, some part of the true value must be

truncated to make it fit into the allotted space, since a length is specified

in each case. For all the constant types we are discussing except C, excess

information is dropped at the left end of the constant, and the rightmost

portion is what is eventually assembled; for character constants the excess

is trimmed off the right end, as may be verified in the example above. Note

that the special rules concerning the apostrophe and ampersand in character

self-defining terms also apply to character constants.

For the constants on the right side of Figure 13.3, the opposite

situation occurs: in each case the space allotted (either explicitly or

implicitly) is more than is required to hold the significant bits of the ,

given. constants. For the examples of types H and F, the assembled value is

simply the rightmost part of an indefinite-length representation in which

the sign bit has been extended to the left; this is as has been customary

up to now. In the character example, the single letter "S" has been padded

with two blanks (with EBCDIC representation 4016) on the right side to fill

out the constant to the required three bytes. The last two examples in the

right column require further explanation. As was mentioned earlier in this

section, no default lengths are assumed for data of types C, X, and B; the

general rule is that in the absence of any limitations, the Assembler will

use just enough bytes for the constant to ensure that no information is lost,

and no more. Thus the lengths of the constants in Figure 13.2 are 33 and 7bytes respectively (these also are the length attributes of the symbols

TITLE and DIGlIPS); no information has been lost, and no padding was required.

13-7

In the Last two examples in Figure 13.3 SC& padding with ~rd& We& required

et the left end of the .constants to fill out the partially-specified byte.

Before discussing llterals and the definition of storage areas, WC chill

introduce another type of constant which is'of great use anii broad applicability

In Assembler Language programming: this is the type A, or address, constant

(scmetimes abbreviated “adcon”). An address’ constant is written differently

fran the other types we have considered, since the constant is delimited by

parentheses rather than apostrophes, as in A(N). The utility of address

constants is a consequence of the fact that the constaI!t may be any expression,

absolute or relocatable. The latter case of course requires Mary other

considerations having to do with processing by the Linkage Editor and

Resident Supervisor, so for the time king we wi.Ll restrict our attention

to cases where the constant in an address constant is an absolute expression.

The A-type constant is similar to F-type constants in that a length of

four bytes and a fullword boundary alignment are implied; thus A(M) and F'lO'

are equivalent operands, as are AL4(10) anti FL4110' . A maJor

difference lies in the ability to specify constants such as A(X’l2E’)

and A(C’ ') (which are the same as F'3O2' and ~'64' respectively), in

'which the use of such expressions may greatly simplify the programming task.

In particular one may define constants using operands such as A(AEiS425)

where the symbol ABS425 may have been defined in an EQU statement (as in

Section 11) to have some particular value. Though the utility of such

constructs is not apparent now, we will see through later examples that

clarity and simplicity can be gained through their use.

One further facility is provided by the larger System/360 Assemblers

for conversions of types A, F, and H: the value specified may actually be

a sequence of values separated by canvas (and no blanks), as in DC F'8,8,8'

which, as was indicated earlier, is equivalent to DC 3F'8' and

m F’8’,F’8’,F18’ . Which one is used is largely a matter of taste and

convenience; for example, it is simple to specify a group of constants by

the use of a statement such as TABLE DC F’l 5? 3 4 5 6 7 8 y 10'> 2 3 t t > J I Jwhere each generated constant is a fullword integer aligned on a fullword

boundary. In all such cases where multiple constants are specified, the

symbol in the name field entry (in this example, I!ABLE) is given a value

13-8

and length attribute associated with the first constant generated. It is

not possible to specify multiple values in constants of types B, C, and X.

The short table in Figure 13.4 summarizes some of the rules given above

for writing operands in DC instructions. The complete set of rules is

summarized in the Appendix.

2a!E-H

F

A

B

C

x

ImpliedLength

Implied Value is DelimiterAlignment Specified by Used

1

Truncation,Padding on-

MaximumLength

8 halfword decimal digits ' '

8 fullword decimal digits ' '

4 fullword any expression ( 1

256 . none binary digits 1 I

256 none characters - ' '

256 none hex digits ? t

(* the implied length is the minimum number of bytes required tocontain all the given information)

left

left

left

left

right

left

--Figure 13.4 Summary of Rules for Certain DC Operands

Multiple_Values?

Yes

Yes

Yes

no

no

now

It often occurs that a storage area is needed in a program which need

not be initialized to some value by the use of a DC instruction. This

facility is provided by the D3 ("Define Storage') assembler instruction,

which is almost identical in use to the DC instruction. The rules for

writing the operand field entry are the same, with the exception that the

specification of a value is optionai. Thus the statements DS F and

Es F’8’ will both cause the Assembler to reserve a four-byte area on a

fullword boundary, but no constant will be assembled, even though one is

specified in the latter case. Statements-such as DS C'MESSAGE' will

reserve an area whose length is computed by the Assembler from the length

of the given constant (7 bytes), but there will be no constant assembled

into the reserved area. Large blocks of storage may be reserved by statements

such as -

STbRAGE DS 1OOF

which reserves one hundred aligned fullwords and assigns to the symbol

13-9

@RAGE the location of the firpIt. #oLe aals,o that the two statements

AREA1 m 8oc and AREA2 DG CL80

both define storage areas of length 80 bytes, but the length attributes of

the symbols AREA1 and AREA2 are 1 an;d 80 respectively, which may be of

interest in a program. Note in the former of these cases that in the absence

of either a constant or an explicit length, an implied length of one byte

is assumed for the C-type specification; the same is true for types B and X,

so that DS B and Ds x would both cause a single byte to be

reserved.

One special case arises in the use of the DS instruction when a duplication

factor of zero is specified. In such a case any necessary boundary alignment

implied by the type is performed, and then, if a name field symbol is present,

the adjusted value of the IC is assigned to its value and its length

attribute is determined from the operand; s space is reserved. Thus a IX3

instruction with duplication factor zero can be used to force a boundary

alignment which would not be available otherwise. For example, the two sets

-- of statements

W#RD DS OF and Ds OFDC C'W#RD' W#RD DC c 'WjhD'

both serve to define a four-byte character constant on a fullword bandary

addressed by the symbol WfiRD, which would not in general have been the case

if DC C'W@D' or DC Cti'W#RD' had been specified. Note that

DC A(C'W@RD') is incorrect: because the operand in parentheses muet

be an expression, and because C'W#RD' contains more than the allowed

maximum of three characters which is required by the rules for forming self-

defining terms, the expression which-forms the value for the address con&ant

is invalid.

If a duplication factor of zero is used in a DC instruction, it behaves

just as would the corresponding IS instruction. When bytes are skipped to

perform alignments implied by DS statements, the Assembler does not put zeros

in the skipped bytes.

This brings us finally to the subject of literalsr It often occurs in

programs that some constant must be defined which is used only as a constant.

13-10

In the sample program segment in Figure 12.1, the two quantities in the

fullwords named N and j&E are both defined by DC instructions, but it is

implicit in the use of the symbol "j&E" that the contents of that fullword

should retain the integer value +l throughout execution of the program. It

is of course possible to use constructions such as EIGHT DC F'5'

in a program, but this cannot be of much help in making the program easier

to read or understand, particularly if some part of the program stores data

of varying values in that area. The Assembler provides a simple and

convenient means for simultaneously defining constants and referring to them,

through the use of literals.

' A literal is a special kind of symbol, where the value of the contents

of the storage area referred to by the literal is contained in the literal

Ptreelf. A literal is written as an equal sign (=) followed by an operand

which conforms to the rules for operand field entries in DC instructions.

The following are examples of literals.

+"l' =c * L~INGLI~~ERAL* =BL2'111lOL'-- =H'l' =CL7! BLANK' =x'76543ul'

=A(l) =F’1,2,3,4’ =ALj(>,X'D7'/C'.')

Literals may be used in most places where symbols are permitted, with the.follaring exceptions:

(1) a literal is a term which may not be combined with other terms

(thus IC O,=F'1'+3 is illegal);

(2) an instruction may not store or modify a literal (thus ST 7,=F'l'

is illegal);

(3) a literal may not be specified in an address constant (about which

more later) (so that A(=F'l') is illegal);

(4) multiple operands may not be specified, but multiple values may;

(5) the duplication factor may not be zero;

-(6) the alignment of the data described in the literal is that implied

by the constant type (so that L 2,=X'2B' will probably cause a

specification exception).

13-11

'JPa illustrate the use of a liteM. in ,a program sement, we aM.8rewrite the example in Figure 12.1 in ltthe form given in Figure 13.5 below,

BALR 6,oUSING TsIwj)m,6

Il3EGIN L 2,NA 2 4?'1'ST 2:Ip

"-"----m---I-N DC F’8’

Figure 13.5 Sample Program Ueing a Libwal

In this uase the programmer has been relieved of the duty of defining a

constant and creating a symbol by which to refer to it, as was the case

pr@Yiously* For this gain in ease of referring to constants there is a

corresponding loss in the precision with which one may specify exactly where

the constant is to be located, since this must ~CRV be determined by the

AreembXer (a small amount of control is left to the programmer). Ae literale

-- are encountered by the Assembler in the course of scanning the source program,

-a separate internal table -- called a literal pool -- is formed whichoontains all the literals encountered, with duplicateseliminated. ,This

alluws the programmer to make liberal use of literaIls with sOme small assurancethat he will not generate an excessive number of constants. These are placed

in the program at an appropriate location, and the Assembler then computes

the required displacements which allow the constants to be addressed. We

will use literala in many places throughout this presentation, and it should

be borne in mind at all times that a literal is a special symbol, and not a

piece of data, a_ storage area, or a value, which are common misconceptiohs

in the u8e of literals.

We brave now covered enough basic material to be able to examine many of

the irmtructions of System/360 in the context of actual programs. In thenext *everaX sections we will discuss the use of the general registers fora variety of purposes, and give some examples of program segments which

illustrate typical uses of the instruction set.

1342

14. GENERAL RRGISTER SHIFTING AND DATA TRANSMISSION

In this section we will discuss the instructions which cause data to

be transmitted among the general purpose registers, between the registers

and memory, and within the individual registers themselves. Some of the

instructions will be treated in detail,- since they are the first of the RS

type to be examined.

A notational convenience will be introduced here: because we will

often have need to use the phrase "general purpose register rl" where rl

indicates the value supplied for an operand in the operand field entry of a

machine instruction statement, we will use the abbreviation "Rrl" instead.--Thus if rl has the value.5, the register being referred to is Ry.

We will first examine the instructions which transmit data between the

GpRs and memory. The most important of these are the L (Load) and ST (Store)

instructions, which were encountered in several earlier examples. Both are

of type RX; both require the effective address to be divisible by 4, so that

the use of a fullword operand is indicated. The instruction

L rl,d&&b)

causes the fullword second operand to replace the contents of Rrl. The

original contents of Rrl are lost, and the contents of the fullword area in

memory remain unchanged. As a reminder, the term "operand" was used here

to mean the data referred to at execution time by the effective address,

which was computed from components of the instruction determined during

assembly fran the second operand in the operand field entry of the instruction

statement. As mentioned before, which meaning of the word "operand" is

intended will usually be clear from context.

14-l

For example, to set the contentrs of R9 to zero we could write

L 9,=F'O'

and to set it to the maximum negative number,

L 9, =F'-2147483648

would suffice.

The inverse operation ST is written explicitly as

ST rl,ddxCtd

and causes the contents of Rrl to replace the contents of the fullword $;rea

of memory at the effective address of the second operand. : The contents bf

the register are unchanged, and the original contents of the fullword area

of memory are lost. For example, to duplicate at B the contents of the

fullword at A, we could write

L %AST 0,B

and to exchange the contents of the fullwords at A and B, we could write

L LB L 04 L %A L %AL %AST 0,B Or

L LB LST O,B Or

LB but , ST 0,BST 1,A not

ST 1,A5; 0,B

ST l,A ST 0,B ST 0,A

where we have aseumed that Rl is not being used aa a base register. The

use of L and ST in situations where indexing is desired will be treated

later. Both of these instructions are subject to interruptions due to

specification and addressing errors, which were mentioned in Section 5; onefurther interruption may be caused by memory-protection, en optional feature

available on System/360 which allows aOme degree of supervieJion over the

areas of memory acceaeible to a given program. ' We will examine memory

protection in more detail when interruptions are discurrsed.

It ia occsaionalw necessary or desirable to be able to transmit

information between memory and several registere. Thirs can be done with a

eequence of L or ST instructions, a8 in

L 1,AL 2,A+k or

ST l,B

L 3,A4ST 2,B+4ST 3,J34

If the number of registers is large, however, this can be cumbersome and

slow, and it is more convenient in many cases to use the LM (Load Multiple)

and STY! (Store Multiple) instru&ions. Each of these is an RS-type

instruction for which three operands must be specified in the operand field

entry, as follows:

L&l (or STM) rl,rwbbd

where the components of the assembled instruction are pictured in Figure 14.1.

9

operationcode n r3 b2 d2

c 20 7 8 11 12 15 16 19 20 31

Figure 14.1 Components of an RS Instruction

As usual, rl and r3 must be positive absolute expressions of value 15 or

less, and the base and displacement may be given explicitly or left for the--Assembler to compute f&n the value of a symbol or other relocatable

expression. The meanings of the register specification digits in the STM

instruction are as follows: beginning with Rrl, transmit the registers in

order of increasing number to the successive.fullwords in memory which start

at the effective address of the second operand, until Rr3 has been transmitted.

If r3 is equal to rl, only one register is transmitted. If r3 is less than

rl then Rrl through R15 will be transmitted, followed by RO through Rr3;

thus RO may be considered to follow after R15, so that the general registers

"wrap around" from the highest to lowest numbered. The LM instruction

follows the same rules except that the registers are loaded in sequence from

successive fullwords in memory.

For example, IN 2,6,=5~'0' would cause the contents of R2, R3,R4, R5, and R6 to be set to zero. Similarly, STM OJ5,SAVE would

cause the contents of all sixteen registers to be stored beginning at SAVE,

which could be defined in a statement such as SAVE DS 16F which

ensures that the proper boundary alignment will be specified for the second

operand address. If we assume that Rl contains the address of a list of

14-3

four full~ord constants, we could load them$nto R7 through RlO by executingthe statement LM 7,1~,~(1) and if we assume that R13 contains the

address of a register save area, then STM 14,J2,12(13) would store

R14, Rl?, RO,...Rl2 in successive fullwords, beginning with the fourth

f'ullword of the area. These last two example8 iXLuf3trate certain conventicmlr,

c-only used in cammunicating with subroutines, which will be treated in

detail later. As a final example, suppose we wish Lo exchange the contents

of RO through R7, as a block, with the contents of R8 through Rl5. We could

then write

STM 0,15,SAvEIM 8P7*5AvE or

82~ ~J,SAVEI M 0,15jSAvE

-"I G IL)LSAVE Ds 16F -SAVE DS 16F

One small but important detail in this example should be noted: one of the

general registers must have been specified as a base register BO that SAVE

could be addressed. The STM and LM instructions will work correctly, since

the calculation of the effective address is performed before the execute ghaee

- of the I&I instruction cycle begins. When execution is completed, however, the

-base register has been changed, so either the Assembler must be informed that

the base register is changed, or the correct value must be put back into

the original base register.

The transmission of halfword data between memory and registers is

sconewhat more complicated, because a hslfword requires only half of a genwal ’register. The relevant instructions, LH (Load Halfword) and STH (Store

Halfword) are similar to L and ST; both are RX instructions, and the operand

field entry is written the same way. STH is the simpler of the two: the

rightmost 16 bits (the right half) of_Rrl replaces the halfword at theeffective Pddress of the second operand, and Rrl remains unchanged, If thecontents of the register represent an integer too large to be correctly

represented as a 16-bit two's ccaPplement integer, some significance is 1oeLj

no indication is made that the halfword in memory may not have the desised

value. (An example illustrating this will be given shortly,) .Conversely,

when data is being transmitted fraaa memory to a register by the LH Instruction,

it is reasonable to assume that the programmer wants to perform some arithmetic

I .operations on the value transmitted, so that the data should occupy the entire

register with the least significant bit at the right-hand end. To give a

correct representation in the 32-bit register, the sign bit of the l6-bit

halfword operand must therefore be extended to the left to occupy the left

half of the general register. One may visualize this process as taking

place in two steps,. The halfword operand is brought from memory and placed

in the Memory Data Register (MDR), which is an internal register used for

communicating between the CPU and memory. The leftmost bit of the halfword

is duplicated to the left by 16 positions, providing a 32-bit representation

of the original 16-bit two's complement operand. The resulting 32 bits

are then transmitted to the designated general register. Though none of

the models of System/360 use the MDR inprecisely this fashion, we will find

that the descriptions of many instructions can be simplified considerably

by supposing it to take an active part in the handling of data passing

between memory and the CPU. Note that there is also an instruction with

mnemonic MDR; we will indicate which is meant if there is a possibility of

confusing the two. Thus the statements LH O,=H'l' and LH O,=H'-1'

would cause the contents of RO to be set to 00000001~6 and FFFFFFFFle

respectively. As long as the value of the half'word operand X involved

satisfies -215sX< 2i5 it can be correctly represented in 16 bits and will

therefore be correctly transmitted by LH and STH instructions. If this is

not the case, situations such as those illustrated in the next two examples

can arise.

Suppose the sequence of instructions given in Figure 14.2 is executed.

The contents of the registers is given in the comments field of the instructions;

the notation C(R0) means "contents of RO", and X'n' means the same thing as

n16, as in the definition of hexadecimal constants.

L 09 C(RO)=X'00010001'STH 0,A C(A)=X'OOOl'LH 1,A C(R1)=X'00000001'-mm

A D S HB DC F'65537'

Figure 14.2 Loss of Significant Digits when Using STH

14-5

The contents of RO and Rl are different because the quantity in RO being

stored by the second instruction is too large. A more awkward result is

illustrated in Figure 14,3d

L O,=F’65535’ C(RC)=X'OOOOFFFF'STH 0,A C(A)=X'FFFF'LH LA C(Rl)*X'MFFF'-I-

AIBH

Figure 14.3 Loss of Significant Digits when Using STH

Zn this case the result in Rl has a different aign and considerably different

magnitude from the original operand. From these two examples it 9s clear

that the programmer who chooses to use halfword data must exercise care to

Be sure he understands what can happen when storing or loading such quantitiee,

!l?wo further instructions used for transmitting data between the general

registers and memory are IC (Insert Character)and STC (Store Character).

(IC was used in the addressing examples in Section 5.) The operand field- sn%ry is written in exactly the same form as for L and ST, and no particular

boundary alignment is required for the address of the second operand, aincta

the data being moved in this case is contained in a single byte.

The instruction STC rl,d,dx2,bd causes the rightmost byte of

~ Rrl to replace the byte at the effective second operand address. The inverse

operation is called "Insert Character' rather than "Load Character", because

the specified byte fran memory is placed in the rightmost 8 bits of theregister without disturbing the remaining 24; no sign extension is performed.

Ae an example, the instructions below can be used to reverse the order of

the two-characters in the character constant at X and place the result at Yd

rc 0,xSTC O,Y+lIC 0,x+1STC 0,Y"WI

x DC C'AB'Y Ds CL2 BEc$?hEs C'BA'.

14-6

OccasWnaUy whet; memory space Is at a premium it is convenient to me e

single byte to contain a small integer constsnt; its value may be placed in

a register uulng the following instruction sequence.

L l,=F'O' CLLEAR REGISTERxc l,LITLC#N INSERT C@NSTANT

LrnI@Iv D C FLl'53'

None of t& instructions discussed up to now has had any effect on the

Condition Code (CC). We now turn our attention to five RR-type instructions

which transmit date among the general registers, four of which can change the

value of the CC. The instructions are LR (Load Register), lXR (Load and Test

Register), LCR (Load Complement Register), LNR (Load Negative Register), end

LPR (Load Positive Register). The IR instruction was used in the machine

inetruction statement in Figure 9.5; it is the one instruction of these flve

which does not set the CC. The operand field entry, as noted in Section 11,

is written rl,r2 and the action of each instruction is summarized in

Figure 14.4 below, Note that r2 need not differfran rl.

Instruction

LR

LTR

LCR

L

I Action.

c(w) 4~2)

C(Rrd +-C&-2)

C(Rn) e- -C(Rrd

C(b) + ICb2>l

a-1) +- -IC<Rrdl

CC Values

not set

0,1,2

o,v%3w,3OJ

Figure 14.4 Action of Certain General Register Instructions

The meanings of the CC settings are given below.

cc Meaning

0 Result is Zero

1 Result is Negative

2 Result is Positive

3 Result has Overflowed

Figure 14.5 Condition CodeSettings

14-7

As can be seen from Figure 14.4, the actions of LR and LTR are identical

exceg2; that LTR also sets the CC* XL Is notuncommon to test the contents

of a register by writing an instruction such as Lmi $4 which has no

effect other then to set the CC, which may then be tested by a X or BCR

inatructfon, which will be dlscuased later, 'For the other three instructions,

the arithmetic operations are those implied by a 32-bit t~o's complement ,

representation ; thus overfluw can occur during execution of LCR or Ll?R only

if C(Rr2) is the maximum negative number, -2'l, and no overflow can occur

during execution of U/R beuriuse all representable positive values have a

corresponding t~o's complement representation of their neptive values.

The f'o~kW.ng short instruction sequence illustrates possible uses of the

%nstruct5ons.

LM 2J0=F'1,0 c R2 =l, C(R3)=0, CC N@ t3EL’LR ?,3 C 1 1R7 "0, CC N#T SETU3CR 2,2 ow% CC=2

z 4')e7C(Rl)=O, cc=0

Im 014C(R4 z-1,C(R0 Wl,

JwlQsz 5,2 i

cc4c c = 2

C(R5 -1, CC=1

- Figure 14.6 Example of Use of Certain RR Instructions

TWO common errors for beginning programmers are to crgnfuse the LR and L

IrMznrctiona, and to try to use an "STR" instruction to '%&ore" one register

into another. By oubstituting L for U3, one can occasi6neJJy generate

aading errora which are undetected by the Assembler: 3'or example, L 58is a valid instruction referring to location 8 in memory, which is probably

not the programmer's intentSon. As an aid to remembering the difference

between related in&zuctions of differing types, note that almost aJZ of the

RR Mtructions end in the titter "R", and the RX, SI, or RS instructions

end in other letters,

The shiftQig inetruct~ons to be described next a%? more interest$Qj,

bin66 they allow the prog&~~~er to manipulate data in tio~e varied ways thati

the hUMuc!tiona described up to now, All of the eight shift instructk&s

are Rktype; they U.ffer $~GIII Levi ant! S1ItfM in the important respect that the

r3 register spacificetion digit (see Figure 14.b) is i&nor@ when the

1438

Fy!. . . .

,I ‘,.

instructions are executed, and thus the operand field entry for shift

instructions is written

rl,d2(bd

with the r3 operand cmitted. For all of the shifting instructions, the

number of bit positions to be shifted is determined from the low-order six

bits of the effective address; this allows for the specification of shift

amounts between 0 and 63 inclusive. The simplest shifting instructions are

SRL (Shift Right Logical) and SLL (Shift Left Logical); we will examine

these first.

The basic operation in shifting is the unit shift, in which each bit

moves to the right or left by one binary digit position; the vacated bit

position on the left or right end is handled differently for logical and

arithmetic shift instructions. For the logical shifts, the vacated bit

position is alway set to zero, and any bits shifted off the opposite end

are lost and ignored; for arithmetic shifts this is true only at the right

end. Thus, if the contents of R8 are 8765432116 and the instruction

- SLL ,'8,1 is executed, the result in R8 will be OECA~~~&+ Note that we .could have written su' 8,1(o) also, because the explicit use of 0 a6

a base register specification.dig3.t causes no base register to be used inthe calculation of an effective address. Again supposing R8 to contain87@GZl~j and R3 to contain 82F3A2~~j~~, execution of the instructionW 8,16(3) would cause the contents of R8 to be shifted right-516+1016 = ml6 (modulo 4016) bit positions, leaving 043B2Al9~6 a6

tbei result.

For a simple example of the use of the single-register logical shift

instructions, 6uppose we have a large table of data, where each entry is

eix byte6 long and is aligned on a halfword boundary. Suppose also that the

first three bytes contain character information of some sort, and the

remaining three bytes are to contain a 24-bit two's complement integer value

associated with the characters. We want to load and store the integer value

into and from R5, where it will be used for some purpose in the program.Now it is clear that L and ST cannot be used, since it is not possible to

obtain the proper alignment of the operand in memory; similarly, LH and STH

handle only two of the three bytes. A simple solution is to pack the integer

value so that its rightmost eight bits occupy the first byte, and the

14-y

I

leftmost 16 bit6 occupy the second and third bytes. Suppose R5 containsI

FFE!A&OB&6, and RI2 contains the address of the first byte & the particular

6-byte data entry undek conoidcration. Then the sequence of inbtru,ztions

below a@n b&used to peck the nwnbdr into memory. (The letters XXYXZZ are

meant to represent the hex digits of the three characters in the da-ta entry.)

STC 5,3@&9 C(IIATA ENTRY) = XXYYZZO3----SR.L 5,8 CR+4OFFFA&STH 5,4(0,=) C t hATA ENTRY) = XXYYZZORFA62

To shaw that the desired value can be correctly retrieved, we execute the

inver6a instruction sequence.

LH 5,4(%WSLL 5,8IC 5,3ubw

This example also illmtrates a situation where the need for efficient

us ef ownory apace outwwtghs the extra time required to aace$u olnd store

the needed value. If the data entry wem expanded to eight bytea, with tha

~hrraterr oeaupying the first three bytes and the aaoociated value Sn the

la8t four, then simple L ‘and $?I instru&ions could be used, with a considerable

itlomrse In #peed (an approximatafactor of 3) for thia segment of code._ _. - --8uclrh eoneiderations may be quite important for program@ which prodess large

emcamt~ of data -- the example typifies what is called the trade-off’ between

egslae and speed, We will see a number of examples where the e%pmditure of

aemory spacre may re6ult in increased processing speeds.

We could also have arranged the data so that the three-byte integervalue occupied the first three bytes of the data entry, and the characters

oacrugled the last three byte6. The integer value would then be stored in

mewry-with its bits in the -proper arithmetic aaquence; tl;bg instructiona

need4d to load the value into R5 would be as follows, assuming that the data

entry aontained FA6@XXYY!2Zo

LH 5,W,u) ++FFFFA&SL 53 =KFFA62~IC !mo, 12) mmA&CB

Zt is appewmt that the particular arrangement of the data in memow maydepend in the propammer’e inclinationa, as well al on coneideratiohr ofeaee. of r#pOqprppplin(r or spegd of execution.

14-10

The double-length logical shift instructionsSLDL (Shift Left Double

.Logicaa) and SRDL (Shift Right Double Logical) work in exactly the same

way as SLL and SRL except that a pair of registers is shifted. The register

specified by the first operand (Rrl) must be an even-numbered register;

otherwise a specification exception will occur. The next higher numbered

register is the low-order half of the double-length register pair, with bits

shifted out the right end of Rri entering the left end of Rrl+l, and vice

versa. (This is one of the reasons for showing the general registers in

pairs in Figure 3.7.)

To illustrate a trivial application of these two Instructions, suppose

we wish to reverse the order of the half'words at A and At2, where A is on

a fullword boundary. Then each of the following code sequences will perform

the desired task.

LH CA LH %A L 24 LH 24SRDL 2~6 SRDL 2,16 STH 2,A LHLH

3,A+22,Ai2 LH2~6

2,A-Q sm 2~6 STH2~6

2,A&SLDL SRDL STH 2,A+2 STH 3,AST CA ST 3,A

--(The third and fourth examples illustrate that when the data happen to be

aligned in a particular way, there may be simpler ways to arrive at the

same result.) To take a less trivial example, suppose that in a certain

application we need to access some integer data which has been packed SO

that four positive integers fit into a fullword, as shown in Figure 14.7.

t1st integer 2nd integer 3rd integer 4th integer9 bits l ong 4 bits long 13 bits long 6 bits long

0 89 Il.2 13 25 26 31

Figure 14.7 Four Integers Packed in a Fullword

A sequence of instructions which unpacks the integers and places them in

the .fullwords labeled FIRST, SECfiND, THIRD, and F@JRTH, follows; assume that

R9 contains the address of the data word. The comment statements give the

binary contents of RO and Rl: the bits of the integers are labeled A, B,

C, andD; X represents a bit whose value is unknown, and 0 is a 0 bit.

The " . " is simply to indicate the boundary between RO and Rl.

14-11

,

‘\

e

L 0,t.u 019) G E T D A T A FULLWQRDAAAAAAAAABBBBCCCCC,CCCCCCCCDDDDDOD.XXXXXXXXXXXXXXXXXXXXXXXXXXXXX%XX

S R D L O-,6 S H I F T O F F 6 BltSOOOQOOAAAAAAAAABBBBCCCcCCCCCCCC,DOOOOOXXXXXXXXXXXXXXXXXXXXXX%%XX

SRL lt26 M O V E 7’0 RICH7 E N D O f Rl000000A4AAAAAAABRB6CCC~CCCCCCCCC.O~O~~~O~~O~O~~~~~OO~~OOOOODDD~D~

ST 1,FQURTti S T O R E F O U R T H I N T E G E RS R D L O,t3 SHfFT O F F 13 BITS

0000000000000000000AAAAAAAAARRHB,CCCCCCCCCCCCC0000~00~00000000000SRL h19 M O V E TO R I G H T E N D UF Rl

000000000~008000000AAAAAAAAABBBB.0000000000000000000CCCCCCCCCCC~CST tgTHIRD S T O R E T H I R D I N T E G E RSRDL O r 4 SHfFT O F F 4 BITS

0QU00~0OO~OOOO~OQ~OOO~OAAnann,sBss000~~O~~O~OOO~OOOOOCCCCCCCCCST 09FlRSf S T O R E LSt XNr@GER FRbM R1SR1 I.28 P O S I T I O N SfC’QhHJ f NTEbER

00060000600400000000000AAAAAAAAA~0000~~~~0~00~~~0Q000~~~00~0088BBST ItSECOND STORE SECOND ‘IiWZCER

I Armthe? m& raquintze to do the came task iot

L1-1RStDlSTLRSt-D!.ST ,.LRSLDLS TSRLST

Z,*F’O’1*0(0,9)*012019O,FtRS% -Oa2b40, SECONDQd0,130,THfRDI.261 rFOURTti

GET A 0 CCINS~A-N’~ FOR CLEARING ROG E T D A T A F U L L U O R DC L E A R ROSHIFT 9 8IrS IMTf3 ROSTORE F iRSr t NTEGEfiCLEAR ROS H I F T 4 B I T S !WtO R O

C L E A R RQSHlFT 1 3 B I T S TNT0 ROS T O R E T H I R D I NTEGERREPOSIYION FOlJRtH I N T E G E RS T O R E F I N A L WALUE

Jn thie example t& au’ 1,26 replaces the WI and WDb usad $0 tha

firat three steprr, bscauara It results in leas coda aad rlightly faster%%ecution. The ovcsrall raving is quite small, but tba almice ~*mres es a nsxaepp1a of a small econabyr which,. if applied in mm~l kay places in e Zolrgeprdgx&n, could result in elgnif’lcant savings,

T h e arithmtic shift instructions am almost ithntical to Ohs loglaalshift instructions, with the differences being In ths r&ti~ of $b CC and*he treatment of the siggn bit. The instructions a;ti Sti ($?a&% ILeft

14-12

Arithmetic), SRA (Shift Right Arithmetic), SLDA (Shift Left Double Arithmetic),

and SRDA (Shift Right Double Arithmetic). On right shifts, the sign bit is

duplicated in the vacated sign position after each unit shift; thus the

arithmetic integrity of the shifted operand is maintained. To illustrate

the difference between logical and arithmetic shifts, suppose a right shift

of two places is performed on a register containing FFFFFFF&e:

L O,.=F'-8' L O,=F'&SRL 0,2 SRA 0,2

After the logical shift, C(RO)=3FFFFFF2 16, and after the arithmetic shift,

C(RO)=-~e. For positive operands, the SRL and SRA instructions will

leave identical results in the register shifted; SRA will set the CC but

SF& will not. The instruction SRDA is similar to SRA except that an even-odd

register pair is shifted.

For arithmetic left shifts, the situation can be a little more complicated.

When an operand is shifted left there is the possibility that one or more

significant bits will be lost. This situation is detected by (1) retaining

the original sign bit, and (2) indicating an overflow if any bit shifted--out of the bit position Jubt to the right of the sign is different from the

sign bit. The following code sequence would produce the results indicated.

L O,=F'-8' C(RO)=FFFF'FF'F8, CC UNCHANGEDSRL 0,2SLA 0,4

C(RO)=3PFR?F2, CC UNCHANGEDC(RO)=TFFFFF20, CC SET TO 3JhIEBFL@

Condition Code settings produced by the arithmetic shift instructions are

given in Figure 14.8.

t 1 .

Instruction CC = 0 CC = 1 CC = 2 cc = 3

SLA Result=0 Result<0 Resulta Overflow

SRA Result=0 Result<0 Resul-00 Znpossible

SLDA Result=0 Result<0 Result>0 Overflow

SRIM Result=0 Result<0 Result>0 Jinpossible

Figure 14.8 CC Settings after Arithmetic Shifts

14-13

A CC value of 3 iar ndt pousibb after the SBA and Burls Instructions. Ngtethat becau~s the meult tested for CC eettidgs for SLM and f3RRA is a

double-length operand, these inertruetions provide a simple means for testingwhether both registers contain zero: both SD 0,o and BLDA 0,o

will rert the CC to zero if RO and Rl contain zero.

An important charucteristiu of the arithmetic shift operations Is thatthey provide a simple means for multiplying by positive and negetive powersof two. Since the bite of an operand shifted left by a unit shift appearwith a weight (in the sum forming the value of the operand) which has increased

py two, we can r3ee th8t 80 long a8 no overflow occur6, an errithsnettic lsftshift of n places corresponds to multiplication by 2". Similarly, for a unit

right shift each bit haa a weight which has decreased by two, so that anarithmetic right shift of n places corresponds to division by 2? Because

such a "divlaicm" can appear to produce fractional results, we must examinewhat happen8 when bit8 are lost; consider the two following code eequcrncee.

L 3,=c5’ cow = OOOOOOOgai 3,1 C(R3) = OoooOOC2

L 3pp1’9’ (03) ama+SW 3,l C(R3) =rnD=-3

As we might have expected, the lost bit in the first case simply reaultss in

the fractional part of s/2 being loart, so that the result is simply 2. Inthe eecond case the result is -3, not -2; this is because the truncation ofthe fraction part of a nulraber in the two's caPplement representation has theeffect of always forcing the result to the next lower integer value.

As a simple example, suppose we wish to truncate the integer in R9 to

the next algebraically lower multiple of 16, unless it is already a multipleof 16. - Roth of-the following code sequences achieve the desired result.

53w 9,4 SRL 9,4Emi 9>4 SLL 9,4

The logical shifts can be used because whatever bit is shifted out of the

sign position by the SRL instruction is put back by SLL. If a CC settingis desired to indicate the status of the result, then the first code sequenes

must be used; if not, the second is preferable because 'it will operatealightly faster, became the CPU need not bother with duplicating the. @ign

bit nor checking for overflow.

14-14

To conclude our discussion of shifting, we will re-examine the problem

of unpacking the data contained in the fullword pictured in Figure 14.7,

on the supposition that the four integers are in signed two's complement

representation rather than the unsigned logical representation assumed

before. The following code segment stores the four signed integers as

required.

t O,O( 019)S R D A 0 . 6S R A 1,26S T 1,FaURTHS R D A 0113S R A I,19S T 1tTHlRDS R D A 014ST 0,F IRSTSRA I,28ST 1,SECOND

G E T D A T A h’CRDS H I F T 6 B I T S INTO RlE X T E N D T O R I G H TS T O R E FUtl-WORD R E S U L TS H I F T O F F 1 3 F?ClRE BITSS H I F T W I T H S I G N E X T E N S I O NS T O R E S I G N E D R E S U L TSHIFT- O F F L A S T 4 BITSS T O R E C O R R E C T FIRST I N T E G E RE X T E N D S E C O N D I N T E G E RS T O R E F I N A L R E S U L T

Because the number of positions to be shifted by any shift instruction-- is determined from an effective address, the number of shifts can be

specified at execution time. For example, SLL g,o(4) will shift Rg

by an amount determined by the ;Ightmost six bits of the contents of R4.

As was the case for the use of relocatable symbols which named areas of

memory, the Assembler will compute displacements and assign bases for

absolute expressions. If we write the sequence of statements given below,

the instructions would be assembled as indicated in the right-hand column.

USING 6,2A EQU 10

SLL g,l2 . 8ggozoo6SLL 9,l-m) 8ggoooocSLL g,A 8ggozoo4 <

Thus we can vary the number of shifts at execution by placing appropriate

values in R2. We will find that there are relatively few occasions where

an absolute expression will be used as the first expression in a USING

instruction.

14-13

15 * CONDItTfONAL BRANCHING

In this eection we will discuss two branch instructions whose use is

fundamental in almost all. prowarns. The ability to choose alternative

courses of action in a program dependtng on colllputed resukts is one of the

most diatinative feature6 of 6 computer, and we will make use of these

instructions in most of the remaining program examples. We will examine the

oonditional branch inslemctions before continuing our treatment of generalreegieter operations, since we will then be able to give more extensive and

realistic aample programs to illustrate the points involved.Because the Condition Code is contained in a two-bit field of the PSW,

‘-the possible values which may be assumed by those two bits are 0, 1, 2, and

3. To test for one of these values, either BC or BCR is used; both are

cal31ed “Branch On Condition" instructions, with BC being of type RX and BCRbeing of type RR.

If the con&ion for branching is met (and how this is determined

will be discussed shortly) no action is taken and execution simply proceeds

to the next sequential instruction following the BC or BCR.If the branching condition 5 met, the branch address must be determined.

For the JX instruction, the branch address is the same as the effective

address computed as usual from the base, index, and displacement fields of

the instruction; for the BCR instruction, the branch address is given by

the rightmost 24 bits of the general register specified by the r2 digit of

the instruction unless r2 is zero, in which case no branch ever occurs. To

ocqplete the execution of the branch instruction, the IA portion of the PSWis replaced by the branch address. The next instruction to be fetched will

therefore come from the location specified by the branch address. Sranch

instructions are also called wjumpw and "transfer" instructions, in the sensethat a jump is made, or control is transferred, to the branch address.

=R 9,4 in which t2w maok Pieldts are 0U.k and XWlg fictively. kt

executicm tioas, a mtbb io made kPtween the 1 bYts of the mr%rk and the value

t 1 Hwk 3it Value 1 CC Valw HL%ched 1

I

a8 8 0

9 4 1

10 2 2

ll 1 3

teetre 4;or CC=3- test4l for cc=2

Figure 134, Mask 3its and Corresponding CC Values

If thrs CC Ixes a vaMe wh%ch mat&es a 1 bit in the ~+sb field, the bdiqgodnditticm &met; if the CC hm a value which matches SI 0 bit in the ljlr,

t+b branching condition ;,I; &set, and no branch o66urs; Thus in tW

exampiLe given abdve, the IiE instmactlon would branch unless the CC I@ m&mOj md the BCR would bmnch if the CC had value 0 or 3. Further exe*-

a2-e &van beluw.

1) Branch to X if C(RlZ)=O.

l3YR l2,12Or

SRA x2,0

BC 8 , x BC 8 , x

2) Branch to X if C(RO)#O.

LTR 0,oor

SLA 0,o

BC 6,X BC 7,x

(Note that the CC cannot have value 3 after LTR.) In both of the above examples

the use of LTR is shorter and faster.

3) Multiply C(R5) by 4 and branch to X if the result does not overflow6

Su 52Bc 14,x

4) Branch to the address contained in R14.

BCR 15,1-4 (preferred)

or

BC 15,0(0,14) (slower)

or

BC 15,004) * (slowest)

Sinue the CC must have a value which matches a bit in the mask, the branch

alttaye ot!W~jr~j this is called an unconditionalbranch.

5) P l a c e -C(R2) in R8 and branch to X if the result is negative&LCR 8,2

BC 5,X

It is not sufficient to use a mask of 4 since the result will also be

negative if overflow occurs.

6) A positive nonzero fullword integer at N is to be shifted rightaa many places as necessary to insure that its rightmost bit is noneeroI

a> Snift left into R4 until R5 has been vacated:

L 5,JJ GET INTEGERL 4,=F'O' CLEAR R4

SHUET SLDL 4,l SHIFT LE3!7!LTR 535 TEST R5BC 7,SHIFT BRANCH IF NJ6T ZER$ST 4,N ST@ REWJLT

15-3

bj $hlf% right, testing "loat" bits:

L 0sHu% g?Di 4,L

QD33NTEGER .l!!%TDT RIGHT

I%tfR 5,5 !ll?BT SIGH #F Q5Bc 10, SHZFZI 3#l%AMxDNPST-sm 4,l BJT BACKST 4J IlFCESULT

Wote t&t this Latter example would wo-& kr negative integers aUo $f

arittaaetic shift In&suctions were used.

!&i~j last pair of examples illustratetl a ,I.oop -- a seguenca o$ fhMn@uutltonwhich 1s repeated as many times as is necw~ry to obtain a desired ~~iJ;l~~!k&Loop are such a ccmmn aepect of programmUg that speciah branch irrtitid$@~eare provided in Syetez&60 which greatly facilitate the coding ds 10ojprwithout either examining or testiag the Cc; these will be treated in mm

detail later.

We n~teU &I example 4 above that a lloa& with all 1 bits provid@a, ~lrr

uneondftiom1 branch (remember that we could have written BCR %'3" ,L4and BCR P'llll', 14 also), since the bmnch condition must al*@ bq

amt.I There are occasion&when it is useful to be able to execute an i~ty~uticar

ai'eh a zero mask field. khua .3C 0,X and BCR 0, any aa w6Ll

as BCR any,6 have no effkct; they are sometimes called "no-OJgccmt1on'

tistructions, and the Assembler aotually prov+ko mnerrronics for their1

specification. !I3313 inPitruction6 NIdp 8 and Nf&'R r are tm*tb4

by the Assembler as being the same as BC 0,s and BCR O,rrespectively.

An important use of %o-operation' inst;ructkma is in obtaining a

(desired boundary aiignmnt for a particular instruction. For example, wemay wish that an imtruction such as BALR 143 be followed by analigned fullword cm&ant such as ara address con&ant; emu&es of just t&Se

sort of usage will be illustrated in the treatment of subroutines. SinceRALR is an RR instruction, we must singly insure that its address lies

between two fullword boundaries. In a small prograrm it is easy for the

programmer to determine the location of the BAI;R simply by counting, and if

it falls on a fullword boundary he can insert a R'#E% 0 4mtruction jmt'

before it. Huwever, if the program is large, or if any changes mu& be made

15-4

I

in the code preceding the BALR, it beccmes difficult to know whether the

N#PR should be used or not.

To relieve the prograurnc:; of this worry, the Assembler provides an

instruction CN@? (Condition:31 No-Operation) which ensures the desired alignment.

The operand field entry of rt Sl\l$P instruction is written 0 where

b and w are absolute expressions; b may have values 0, 2, 4 and 6, and w riayhave values 4 and 8. No name field entry is permitted. The second operand,

w, specifies the boundary type :\*elative to which alignment is to be performed,

and b specifies the desired byte relative to that boundary, as described in

Figure 13.2. The Assembler inser's from 0 to 3 N@?R*s to force the LC to

the desired boundary.

Instruction

CN#P 0,4

CN#P 2,4

CN$P 0,8CN#P 2,8CN@P $8CN@P 6,E!

Alignment Performed

Beginning of a fullword

Middle of a fullword

Beginning of a doubleword

Second half'word of a doubleword

Middle of a doubleword

Fourth half'word of a doubleword

Figure 15.2 CN#P Alignments

To achieve the alignment desired in the current example, we would write

CN#P 2,4 ALIGN T$ MIDDLE #F W&D

lb,15 TW#-BYTE INSTRUCTIfiN

DC A(ANYTHING) N@ INTERVENING BYTES

Note that we could not write

Ds OH

BAIiR 14,13

DC A(ANYTHING)

because the alignment to a half'word boundary forced by the DS is automatically

performed by the Assembler for instructions, so that the BALR could still

15-5

fall 051 a,fullword boundary; the Assembler would then fill the two 'bytes

between the RALR and the address constant with zeros (remqber that A-type

constants have an implied fullword alignment). Similarly, we could not

write

BALR lb,15Ds OF

Ix A(ANYTHING)

since the BALR could again fall on a fullword boundary, leaving two bytes

between it and the constant which would be skipped by the Assembler; the

contents of the skipped bytes at execution time may be arbitraw, since

the Supervisor does not clear the area into which a program is about to be

loaded,

Before continuing with our discussion of arithmetic instructions, one

important feature of the use of branch instructions should be noted. Due

to a peculiarity in the design of System/360, invalid branch addresses

(namely odd ones) are not detected at the time that it is found that the

branching condition is me?, but only when the address is presented, as the-

IA portion of the PSW, at the next instruction fetch cycle. The arror Is

duJ,y detected and a specification interruption results, but the 3% now

contains the invlalid address rather than the address of the instruction

which attempted the illegal branch. This means that there is no direct w&y

to tell where such an error was caused, and therefore that such errors in CB

program are correspondingly more difficult to detect. The programmer must

exercise caution in specifying branch addresses in order to avoid this

particular error.

15-6

0. 1 2

8 1 216, I7 1832 33 3448 49 30

64 65 6680 81 8296 91 98112 113 114

128 129 130144 145 144160 161 162176 177 178

192 193 19420% 209 210224 225 226240 24f 242

256 257 250272 273 274280 289 290304 305 306

320 321 322336 337 338352 353 354368 3&9 33e

384 38'5 306400 401 402416 417 410432 433 . 434

448 449 450 451464 465 466 467480 48f 482 483

3 4 5

2: 2:36 37

152 53

6 t I 8

‘f193551

293854

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23 2439 4055 54

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115 116 AA7 it8 119 120

131 132 133 134 135 136147 148 149 150 151 152163 164 165 166 167 168179 180 A01 A82 1433 184

195 196 197 198 199 * 200211 212 213 214 215 216227 228 229 230 231 232243 244 245 246 247 240

259 260 261 262 263 264275 276 277 276 279 280291 292 293 294 295 296307 308 309 3io 31 L 312

323 324 325 326 327 320339 340 341 342 343 344355 356 357 358 359 360371 372 373 374 375 376

387 3 8 8 389 390 391 392403 404 405 406 407 4084L9 420 421 422 423 424435 436 437 438 439 440

452 453 454 455 456460 469 470 471 472484 465 496 487 488500 SOA 502 503 504

9 A

2; 10

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265 266281 282

8

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C 0 E F

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3% 397422 4L3428 429444 445

460476492

461 462 463477 478 079493 494 495so9 510 5-11

6 7 a 9 A 5 c c E F

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527543

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582 583 584 585; 586 587 S88 589 590 591598 599 600 6 0 1 602 603 6 0 4 605 606 607614 615 616 617 618 619 620 621 622 623630 631 632 633 6 3 4 635 636 637 638 639

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9119279439 5 9

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iot4 LO15 1 0 1 6 1017 t o ia 1019 1020 LO2i i022 1023

c 1 2 3

tm2w32*23+

512 513 314528 St9 530544 545 546540 561 L 562

515531547563

24* 576 577 518 579251 592 593 594 5932w 608 609 610 6112t+ 624 42s 626 627

2(1+ 64C 641 642 64929+ 656 657 458 6592A* 612 673 674 61520* 688 689 690 691

2c* 7c4 705 706 70720* 72c 721 722 723zE* 736 t37 730 739ZF* 752 153 t54 735

!D 30* 760 769 170 771r: 3a* 784 385 196 787

321 8OC 801 802 803338 016 817 818 819

34* 832 833 834 83535+ 848 849 850 851336s 864 865 8 6 6 8673t* 88C 881 882 883

38* 896 a97 89839* 912 913 9143A* 928 929 9303w 944 945, 946

3c* 9&C 961 9 6 230* 576 s77 9 7 s3E* 9 9 2 9 9 3 9 9 43f* 1008 lCO9 1OlC

899915931947

963979995

1011

4 5

516 Sl7532 533548 549S&4 565

S80 581596 597612 6136 2 8 6 2 9

644 645660 641676 a77692 693

708 709724 725740 741756 757

772 773788 789804 805a20 821

836 01Jf852 853868 d&98 8 4 8 8 5

900 9 0 191’6 9 1 79 3 2 9 3 39 4 8 9 4 9

964 9 6 59 8 0 9619 9 6 9 9 7

1 0 1 2 1 3 1 3

0 1 2 3 4 5 6 9 A 5 c 0 E

40* aU24 1023 1020 1027 1028 1029 1030 1031 1032 1033 1034 103541* logI 1041 1042 1043 1044 1045 1046 1047 1048 1049 1050 10514251 1056 1057 iosa 1059 1060 106A 1062 1063 1064 1065 1046

1072_ 1067

43* 1073 '1074 1075 1076 LO77 1078 1079 1080 108t 1082 1083

1036 1037 1038 10391052 1053 1054 10551068 1069 1070 LO711084 1085 1086 1007

44* 1088 1089 1090 1091 1092 1093 1094 1095 1096 1097 1098 1099 1100 1101 1102 110345* 1104 1105 1106 1107 1108 1109 1110 1111 1112 1113 1114 1115 1116 1117 1118 111946* 1120 1121 1122 1123 1124 1125 1126 1127 1128 1129 1130 1131 1132 1133 1134 113547* 1136 1137 1138 1139 1140 114A 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151

48s 1152 1153 1154 1155 1156 4157 1158 1159 lib0 1161 1162 116349* 1168 1169 1170 1171 1172 1173 1174 1175 1176 1177 1178 1 I.79GA* 1184 ii85 1186 1187 1188 1189 1190 1191 1192 1193 1194 119540* 1200 1201 1202 1203 1204 1205 1206 1207 1208 1209 1210 1211

1164118011961212

1165 1166 11671181 1182 11831197 1198 11991213 1214 1215

4c* 1216 1217 1218 1219 1220 I.221 1222 122s 1224 1225 1226 1227 1228 1229 1230 123140* 1232 1233 1234 1235 ,1236 1237 1238 1239 1240 1241 1242 1243 1244 1245 1246 12474E* 1248 1249 1250 1251 1252 1253 A254 1255 1256 1257 1258 1259 1260 1261 1262 12634F* 1264 1265 1266 1267 1268 1269 1270 1271 1272 1273 1274 1275 1276 1277 1278 1279

1280 1281 1282 1283 1284 1285 1286 1287 1288 1289 1290 1291 L292 1293 1294 12951 2 9 6 1297 1 2 9 8 1299 1300 13OA 1302 1303 1304 1305 1306 I.307 1308 1309 13lQ 13111312 1313 1314 1315 1316 1327 1318 1319 1320 1321 1322 1323 1324 1325 1326 13271328 1329 1330 1331 1332 1333 1334 1335 1336 1337 133j3 1339 1340 1341 1342 11343

- -1359137513911407

1344 1345 1346 1347 1348 1349 1350 1351 1352 1353 1354 1355 1356 1357 13581360 2361 1362 1363 1364 f365 1366 1367 1368 1369 1370 1371 1372 1373 13741376 1377 1378 1379 1380 1381 1362 1383 1384 1385 1386 1337 1388 1389 13901392 1393 1394 1395 1396 1397 1398 1399 1400 1401 1402 1403 1404 1405 i406

58* 1408 ii09 1410 1411 1412 I.413 1414 1415 1416 1417 1418 1419 1420 1421 1422 142359* 1424 I;425 1426 1427 1428 /429 LB30 1431 1432 1433 1434 1435 1436 1437 1438 14395A* 1440 1441 1442 1443 1444 1445 14.46 1447 1448 1449 1450 -1451 1452 1453 1454 145550* 1456 1457. 1458 r459 f460 14bl l462 1463 1464 1465 1466 1467 1468 1469 1470 1471

1472 1473 1474 1475 1476 1477 1478 1479 1480 1481 14821488 1489 1 4 9 0 1491 1492 1493 1494. 1495 1496 1497 14981504 1505 1506 i507 1508 1509 i510 1511 Z5,22 1513 15141520 1521 1522 1523 1524 1525 15'26 1527 1528 ‘1529 I530

1483149915151331

1484 1485 1486 14871501 15u2 15031517 1518 15191533 1534 1535

1500I.5161532

E F0 1 2 3 4 5 6 7 8 9 A 5 C 0

60* 153661* 135262* 156863* 1584

1537 15381553 15541369 L570i5a5 1586

1543' 1544 1545 15461559 1560 I.561 15621575 1576 1577 15781591 1592 1593 1594

1539is5515711587

1540 15*i 15421556 1557 15581572 1573 15741 5 8 8 1589 1590

1547 1548 lS49 1550 is511563 1564 lS6S 1566 15671579 1580 1581 1582 15831595 1596 1597 1598 1599

64* l&0(1 160165* Lb10 1617b6* 1632 16336t* 1446 1649

1602 16031618 16191634 1635165C 1651

1604 1605 1606 1607 1608 1609 1610 1611 1612 16 13 1614 161s1620 la21 1622 1623 1624 1625 1626 1627 1628 1629 1630 16311636 1637 1638 1639 1640 1641 1642 1643 1644 1645 1646 16471652 1653 1654 1655 1656 1657 1658 1659 1660 1661 1662 1663

68* 1664 1665 1666 1667 1668 1669 1670 1671 1672 1673 1674&9* 1680 1681 1682 1683 1684 1685 1686 1687 1638 1689 1 6 9 0&A* 1696 1697 1698 1699 1700 1701 1702 1703 1704 1705 170668* 1712 1713 1714 1715 1716 1717 1718 1719 1720 1721 1722

1675 1676 1677 i&78 16791691 i692 1693 1694 16951707 1708 1709 1710 17111723 1724 1725 1726 1727

6C* 1728 1729 1730 1731&Cl* 1744 1745 1746 1747bE* 1760 1761 1762 1764bF* 1776 1777 1778 1779

1732 1733 1734 1735 1 7 3 6 1 7 3 7 1 7 3 81748 1749 1750 1751 1752 1753 17541764 1763 1766 1767 1768 1769 17701780 17t)A 1782 1783 1784 1785 1786

1739 1740 1741 1742 17431755 1756 17s7 1750 17591771 1772 1773 1774 17751787 1788 1789 1790 1791

:L‘ to* 1792 1793 1794 1795.L- 714 1800 1809 1810 1811

72* i824 1825 1026 1827'13* 1840 1841 1842 1843

1796 1797 1798 1799 1800 1801 18021812 1613 1814 1815 1816 1817 1818ia28 I&L9 1830 1831 1032. 1833 18341844 id45 1846 1047 1848 1849 1850

1803 1804 1805 1806 18071819 1820 I.821 1822 18231835 1036 1837 1838 18391851 1852 1853 1854 1855

tr* 1856 1057 1058 1859 1860754 1872 1873 1874 18-75 187676* 1888 1089 2890 1891 1892t7* 1904 1505 1906 1907 1908

1867 1868 1869 1870 18711883 1884 1885 1886 1887La99 1900 1901 1902 1903191s 1916 1917 1918 1919

A862 1863 1864 1865 18661876 1079 1880 1381 18821894 1895 ia9d 1897 18981910 1911 1912 1913 1914

-r8* 1920 1421 1922 192379* 1936 1537 1938 1939IA* 1952 1953 1954 1955704 1968 1969. 1970 1971

1924 1925 1926 1927 1928 1929 19301940 194i 1 9 4 2 1943 1944 1945 19461956 1957 1958 1959 1960 1961 19621972 1973 1 9 7 4 1975 1976 1977 1978

1931 1932 1933 1934 19351947 1948 194s 1950 19511963 1964 1965 1966 1 9 6 71979 1980 1981 1982 1983

7c* 1984 1985 1986 198770* 2000 2001 2 0 0 2 20037E* 2016 2017 2018 2019tF* 2 0 3 2 2033 2034 2035

1988 1989 1990 1991 1992 1993 19942004 LOO5 2006 2 0 0 7 2 0 0 8 2 0 0 9 2 0 1 02020 2021 LOL2 2 0 2 3 2 0 2 4 2 0 2 5 2 0 2 62036 2037 203s 2 0 3 9 2 0 4 0 2 0 4 1 2 0 4 2

199s 19962011 20122027 20282043 2044

1997 1998 199920 13 2014 ilbl5'2 0 2 9 2030 2031204s 2046 2047

FG 1 2 3 4 5 6 7 8 9 A 0 c 0 E

808 2048 2049 205081* 2064 2C65 206682s 2080 2C81 208283* 2096 2C97 2098

2051 2052 2053 2054 2055 20562067 2068 2069 2OfCI 2071 20722083 2084 2085 20tj6 2083 20882099 2100 2101 2102 2103 2104

2051 205% 2059 2060 2061 2062 20632073 2074 2075 2076 2077 2078 20792089 2090 209L 2092 2093 2094 20952105 2106 2107 2108 2LC9 2110 2111

I

2115213121472 163

84+ 2112 2113 2L14as* 2128 2129 213086* 2144 2145 214687+ 2160 2161 2162

2116 2117 2118 2119 2120 2121 2122 2 It23 2124 2125 2126 21272132 2133 2134 2135 2136 2137 2138 2139 2L40 2141 2142 21432148 2149 2A50 2151 2152 2153 2154 2155 2156 2157 2158 21592164 Lib5 2166 2167 2168 2169 2170 2171 2172 2173 2174 2175

2 179 2180 2ltli 2182 2183 2184 2185 2L86 2 187 2188 2189 2190 21912196 2197 2198 2199 2200 2201 2202 2203 2204 22C5 2206 22072212 2213 2214 2215 2216 2217 2218 2219 2220 2221 2222 22232228 2229 2230 2231. 2232 2233 2234 2235 2236 2237 2238 2239

80+ 2176 2177 217889* 2192 2193 21948A* 2208 220s 221088* 2224 2225 2226

219522112227

2240 2241 2242 2243 2244 2245 2246 224i 2248 2249 2250 2251 2252 2253 2254 22552256 2257 2258 2259 2260 2261 2262 2263 2264 2265 2266 2267 2268 2269 2270 22712272 2273 2274 2275 2276 22217 222% 2279 2280 2281 2282 2283 2284 2285 2286 22872288 2289 2290 2291 2292 2293 2294 2295 2296 2297 2298 2299 2300 2301 2302 2303

2304 2305 2306 2307 23082320 2321 2322 2323 23242336 2337 2338 2339 23402352 2353 2354 2355 2356

2310 2311 2312 2313 23 14 2315 2316 23 17 2318 23192326 2327 2328 2329 2330 2331 2332 2333 2334 23352342 2343 2344 2345 2346 2347 2348 2349 2350 2351,235a 2359 2360 2361, 2362 2363 2,364 2365 2366 2367

2368 2369 2370 23.7 1 2372 2373 2374 2375 2376 2377 2378 2379 2380 2381 2382 238323%4 2385 2386 2387 2388 2389 2390 2391 2392 2393 2394 2395 2396 2397 2398 23992400 2401 2402 2403 2404 2405 2406 2407 2408 2409 2410 2411 2412 2413 2414 24152416 2417 2418 2419 2420 2421 2422 2423 2424 2425 2426 2427 2428 2429 2430 2431

2433244924652481

2432244824642480

2434 2435 2436 2437 2438 2439 2440 244L 2442 2443 2444 2445 2446 24472450 2451 2452 2453 2454 2455 2456 2457 2458 2459 2460 2461 2462 24632466 2467 2468 2469 2470 2471 2472 2473 2474 2475 2476 2477 2478 2479

\

2482 2483 2484 L485 2466 2487 2488 2489 2490 2491 2492 2493 2494 2495

2 5 1 12496 2497 2498 2499 2500 2501 2502 2503 2504 2505 2506 2507 2508 2509 25102512 2513 2514 2515 2516 LSL7 2518 2519 2520 252L 2522 2523 2524 2525 25262528 2529 2530 2531 2532 2533 2534 2535 2536 2537 2538 2539 2340 254L 23422544 2543 2544 2543 2548 2549 2550 2551 2552 2553 2554 2555 2556- 2557 255%

25272 5432559

G 1 2 3 5 4 7 8 c 04 9 A 6 E F

AO+ 2560 2561 2542 2 5 6 3 2 5 6 4 2565 2 5 6 6 2567 2 5 6 8 2 5 6 9 2570 2571 2!572 2 5 7 3 2 5 7 4 2575Al* 2516 2 5 7 7 2 5 7 0 2 5 7 9 2580 2581 2 5 8 2 2 5 8 3 2 5 8 4 2 5 8 5 2 5 8 6 2 5 8 7 2 5 0 % 2589 2 5 9 0 2 5 9 1AZ* 2 5 9 2 2 5 9 3 2 5 9 4 2 5 9 5 2 5 9 6 2 5 9 7 2 5 9 8 2 5 9 9 2 6 0 0 2601 2 6 0 2 2 6 0 3 2 6 0 4 2605 2 6 0 6 260tA3* 2 6 0 8 26091 2610 2611 2612 2 6 1 3 2 6 1 4 2615 2 6 1 6 2617 261% 2619 2 6 2 0 2 6 2 1 2 6 2 2 2 6 2 3

A4+ 2 6 2 4 2 6 2 5 2 6 2 6 2 6 2 7 2 6 2 8 2 6 2 9 2 6 3 0 2631 2632 2 6 3 3 2 6 3 4 2 6 3 5 2 6 3 6 2 6 3 7 2 6 3 8 2 6 3 9AS* 2 6 4 4 2 6 4 1 2 6 4 2 2 6 4 3 2 6 4 4 2 6 4 5 2 6 4 6 2 6 4 7 2 6 4 % 2 6 4 9 2 6 5 0 2651 2 6 5 2 2 6 5 3 2 6 5 4 2 6 5 5A6* 2 6 5 6 2457 2 6 5 8 2 6 5 9 2 6 6 0 266A 2 6 6 2 2 6 6 3 2 6 6 4 2 6 6 5 2 6 6 6 2 6 6 7 2 6 6 8 2 6 6 9 2 6 7 0 2 6 7 1A74 2 6 7 2 2 6 7 3 2 6 7 4 2 6 7 5 2 6 7 6 2 6 7 7 2 6 7 8 2 6 7 9 2 6 8 0 2681 2682 2 6 8 3 2 6 8 4 2685 2 6 8 6 2 6 8 7

A8* 2608 2689 2690 2691 2692 2693 2 6 9 4 2 6 9 5 2 6 9 6 2 6 9 7 269% 2 6 9 9 2700 2701 2702 27031194 2 7 0 4 2705 2706 2707 2 7 0 8 2709 2 7 1 0 2711 2712 2713 27 14 2715 2716 27 I? 2718 2719AA* 2720 2721 2722 2723 2 7 2 4 2 7 2 5 2724 2727 272% 2729 2730 2731 2732 2733 2734 2735AB* 2 7 3 6 2737 2 7 3 8 2739 2 7 4 0 274/ 2742 2743 2744 2745 2746 2747 2740 2749 2750 2751

AC* 2752 2753 2754 2755 2756 2757 2758 2754 2760 2761 2 7 6 2 2 763 2 7 6 4 2765 2766 2767AD* 2168 2769 2770 2772 2772 2773 2774 2775 t2776 2777 2778 2779 2 7 8 0 2781 2782 2703AE* 2184 2785 2786 2787 2788 2789 2 7 9 0 2791 2792 2793 2794 2795 2 7 9 6 2797 2798 2799Af* 2800 2801 2802 2803 2804 2805 2 8 0 6 2907 2 8 0 8 2809 2810 2811 2812 2% 13 2814 2815

s&

80* 281651* 2 8 3 2828 2 8 4 %03* 2864

2817 2810 2819 2820 2821 2822 2823 2824 2025 2826 2827 282% 28292833 2 8 3 4 2 83’5 2836 2837 2838 2 8 3 9 2840 2841 2842 2 8 4 3 2844 28452849 2 8 5 0 2851 2852 2853 2854 2855 2856 2857 2858 2859 2860 28612865 2 8 6 6 2867 286% 2%69 2870 2871 2872 2873 2j174 2875 2876 2877

2830 28312046 20472862 2063207% 2879

--

04* 2880 2881 2882 2883 2884 2085 2806 2887 2888 2889 2890 2891 2892 2893 2094 2095B5* 2896 2e97 2898 2899 2900 2901 2902 2903 2904' 2905 2906 2907 2908 2909 2910 2911E6+ 2912 2913 2914 2915 2916 2917 2918 2919 2920 2921 2922 2923 2924 2925 2926 292701* 2928 2S29 2930 2931 2932 2933 2934 2935 2936 2937 2930 2939 2940 2941 2942 2943

2045 2946 2947 294% 2949 2950 ‘2951 2952 2953 2954 2955 2956 2957 2958 29592961 2962 2963 2964 2965 2966 2967 296% 2969 2970 2971 2972 2973 2974 29752977 2978 2979 2980 2981 29t32 2983 2984 298s 2906 ‘2907 2988 2989 2990 29912993. 2994 2995 2996 2997 2998 2999 3000 3001 3002 3003 3004 3005 3006 3007

E8* 294409* 29600A* 29768W 2992

6C* 300800* 30248E* 30408f* 3056

3009 3010 3011 3012 3013 3014 3015 3016 3017 3018 3019 3020 30213025 3026 3027 302% 3029 3030. 3031 3032 3033 3034 3035 3036 30373041 3042 3043 3044 3045 3046 3047 3048 3049 3050 3051 3052 30533037 3058 3059 3060 306i 3062 3063 3064 3065 3066 3067 3068 3069

3022 30233038 30393054 30553070 3071

A2‘0 1 3 4 5 6 7 8 9 c 0 E F

co* 3072 3073 3014 3075 3076 3077 3078 3079 3080 3081Cl* 3088 3089 3090 3091 3092 3093 3094 3095 3096 3097c2* 3104 3105 3106 3107 3108 3109 3110 3111 3112 3113c3* 3120 3121 3122 3123 3124 3125 3126 3127 3128 3129

3082 3083 3084 3085 3086 30873098 3099 3100 3101 3102 3103311'4 3115 3116 3117 3118 31193130 3131 3132 3133 3134 3135

ce* 3134CS* 3152Cb* 3168c7* 3184

3137 31383153 31s43149 31703185 3186

3139 3140 314A3155 3156 31573171 3172 31733187 3188 3169

3142 31433158 31593174 317s3190 3191

'3144 31453160 31613176 31773192 3193

3146 3147 3148 3149 3150 31513162 3163 3164 3165 3166 31673178 3179 3180 3181 3182 31833194 319s 3196 3197 3198 3199

C8* 3200 3201 3202 3203 3204 3205 3206 3207 3208 3209 32 10 3211 3212 3213 3214 3215c9* 3216 3217 3218 3219 3220 322 1 3222 3223 3224 3225 3226 3227 3228 3229 3230 3231CA* 3232 3233 3234 3235 3236 3237 3238 3239 3240 3241 3242 3243 3244 3245 3246 3247C8* 3248 3249 3250 3251 3252 3253 3254 3255 3256 3257 3258 3259 3260 3261 3262 3263

cc*CD+CE*CF*

LDJ.1 CO+

ill*02*03*

3264 3265 3266 3267 3268 32b93280 3281 3282 3283 3284 32853296 3297 3298 3299 3300 33013312 3313 3314 3315 3316 33L7

3270 327L 3272 3273 3274 3275 3276 3277 3278 32793286 3287 3288 3289 3290 3291 3292 3293 3294 32953302 3303 3304 3305 3306 3307 3308 3309 3310 33113318 3319 3320 3321 3322 3323 3324 3325 3326 3327

3328 3329 3330 3331 ( 3332 33333344 3345 3346 3347 3348 33493360 3361 3362 3363 3364 33653376 3377 3378 3379 3380 3381

3334 333s 3336 33373350 3351 3352 33533366 3367 3368. 33693382 3383 33 84 3385

3338 3339 3340 3341 3342 33433354 335s 33156 3357 3358 33593370, 3371 3372 3373 3374 33753386 3387 3388 3389 3390 3391

3404 340s 3406 34iI73420 3421 3422 34233436 3437 3438 34393452 3453 3454 .3455

tl4* 3392 3393 3394 3395 3396 3397 3398 3399D5* 3408 3409 3410 3411 3412 3413 3414 341506* 3424 3425 3426 3427 3428 3429 3430 3431D7* 3440 3441 3442 3443 3444 3445 3446 3447

3400 3401 3402 34033416 a417 3418 34193432 3433 3434 34353448 3449 3450 3451

34703464 3465 3466 3467 3468 34693480 3481 3482 3483 3484 34853496 3497 3498 . -3499 3500 35013512 3513 3514 3515 3516 3517

C8* 345609* 3472GA* 3488cw 3504

3457347334893505

3458347434903SO6

3459 34603475 3476349 L 34923507 3508

3461 3442 '34633477 3478 34793493 3494 34953509 35AO 3511

3471348735033519

348635023518

CC* 3520 3521 3522 3523 3524 3525 35L6 352.7 3528 3529 3530 3531 '3532 3533 3534 3535cm* 3536 3537 3538 3539 3540 3541 3542 .3543 3544 3545 3546 3547 3548 3549 3S310 3551DE* 3552 3553 3554 3555 3556 13557 3558 3559 3560 $561 3562 3563 3564 3563 3566 3547OF* 3568 3369 3570 357L 3572 3573 3574 3572 3376 3511 3578 3579 3480 358t 3582 3583

s

0 F0 1 2 3 4 s 6 7 0 9 A B c E

3584 3su5 3584 3587 3588 3 5 8 9 3 5 9 0 3S911 3592 3593 3594 3595 3596 3597 3598 359936qo 3601 3602 3603 3604 3605 3606 3607 3608 3609 36 10 3611 3612 3613 3614 36153616 3617 3618 3619 3620 3621 3622 3623 3624 3625 3626 3627 3628 3629 3630 36313632 3633, 3634 3635 3636 3637 3638 3639 3640 3641 3642 3643 3644 3645 3646 3647

EO*El*E2*f3*

fi+ 3648 3649 3650 36511 3652 3653fS* 3664 3665 3666 3667 3668 3 6 6 9h6* 3680 3681 3682 3683 3684 3685El* 3696 3697 3698 3699 3700 3701

3634 36SS 3656 3657 3658 3659 3660 3661 3662 36633670 3671 3672 3673 3674 3675 3676 3677 3678 36793686 3687 3688 3689 3690 3691 3692 3693 3694 36953702 3703 3704 3705 3706 3707 3708 3709 3710 3711

f8* 3712 3713 3714 3715 3716 3717 3718 3719 3720 3721 3722 3723 3724 3725 3726 3727E9* 3728 3729 3730 3731 3732 3733 3734 3735 3736 3737 3738 3739 3740 3741 3742 3743EA* 3744 3’145 3746 3747 3748 3749 3750 3751 3752 3753 3754 3755 3756 3757 3758 3759E6* 3760 3761 3762 3763 3764 3765 3766 3767 3768 3769 3770 3771 3772 3773 3774 3775

3776 3777 3778 3779 3780 3781 3782 3783 3784 3785 3786 3787 3788 3789 3790 37913792 3793 3794 3795 3796 3797 3798 3799 3800 3801 3802 3803 3804 3805 3806 38073808 3809 3810 3811 3812 3813 3814 3815 3816 3817 3818 3819 3820 3821 3822 38233824 3825 3826 3827 3828 3829 3830 3831 3832 3833 3834 3835 3836 3837 3838 3839

EC*ml*EmfF+

:r-;;o fO*

FL*F2*F3*

3840 3841 3842 3843 3844 3845 3846 3847 3848 3849 3850 3851 3852 3853 3854 38553856 3857 3858 3859 3860 3861 3862 3863 3864 3865 3866 3867 3868 3869 3870 38713872 3873 3874 3875 3876 3877 3878 3 8 7 9 3880 3881 3 8 8 2 3883 3884 3885 3886 38873888 3889 3890 3891 3892 3893 3894 3895 3896 3897 3898 3899 3900 3901 3902 3903

5918393439503966

-~--3919393539513967

3904 3905 3906 3907 3 9 0 8 3909 3 9 1 0 3911 3912 3913 3914 3915 3 9 1 6 39173920 3921 3922 3923 3924 3925 3 9 2 6 3927 3928 3929 3930 3931 3932 39333936 3437 3938 3939 3940 394l 3 9 4 2 3943 3944 3945 3946 3947 3948 39493952 3953 3954 3955 39556 3957 3958 3959 3960 3961 3962 3963 3964 3965

3968 3469 3 9 7 9 3971 3972 3973 i974 .3975 3976 3977 3978 3979 3980 3981 3982 39833984 3985 3986 3987 3988 3989 3990 3991 3992 3993 3994 3995 3996 3997 3998 39994000 eoo1. (5602 4003 4004 4005 4006 4007 4008 4009 40 10 -4011 4012 40 i3 4014 40154OM Wl? 4818 4019 4020 4021 4022 4023 4024 4025 4026 4027 402 8 4029 403a 4831

4032 4033 4034 4035 4036 4037 4038 4 0 3 9 4040 4041 4042 +043 4044 4045 4096 40474%48 4c49 4OSO 4051 4052 4053 4054 4055 4056 4057 4058 4059 4060 4661 4062 40634,064 4065 4066 4067 4068 4049 4070 4071 4072 4073 4074 4075 4076 4077 4078 4079i-08 0 4081 4082 4083 4084 4085 4086 4087 4088 4089 4090 4091 4092 4093 4094 409s

16. FMED-POINT ARITHMETIC INSTRUCTIONS

In this section we will discuss the instructions which perform fixed-

point two's complement arithmetic in the general purpose registers; the

relevant instructions are tabulated in Figure 16.1.

IMnemonic TYPe Instruction

AR RR Add RegisterA Rx Add

ALR RR Add Logical RegisterAL Rx Add Logical

AH Rx Add Half'word

SR RR Subtract RegisterCR RR Compare Register

S Rx SubtractC Rx Compare

SLR RR SubtractLogical RegisterCLR RR Compare Logical Register .

SL Ftx Subtract LogicalCL Rx Compare Logical

SH Rx Subtract HalfwordCH Rx- Compare Halfword

MR RR Multiply RegisterM Rx MultiplyMH Rx Multiply Halfword

' DR RR Divide RegisterD Rx Divide

Figure 16.1 Fixed-Point Arithmetic Instructions

16-1

.

There are severe1 lnotructionr riming frop the table which one might

expect to find: there are no logical halfwt>rd lnstructionr, there is no

"Divide Halfword", and there are no instjructionr for perfoming multiplication

and division with logical operanda. It is posrlble, however, to ccmpute

logical products and quotients using avallrble inrtxuctionr.The operations of the add and subtract inrtmctiens are straightforward ,

and are sumarfzed in Figure 16.2 below. Reaember that the logical add and

subtract produce the sue result as the arlthzetic add and subtract lnstructims

except that the CC Is set differently. For the halfword operations, we may

assuae (as in the discussion of LH in Section 14) that the second operand is

brought fraP memory to the XIX!, extended to a fullword, and then used for the!indicated operation. The notation 'FK$ means the fullword operand at the

effective memory address in the RX instructions, and %?~' means the samefor halfword operands.

Instruction

t-

ARSRA *SAHSH'

ALRSLRALSL

l-

I

Action CC Settings

c(m) +C(bM~2C(R+l) tC(Rr&C(Rr2

C(b) +c(m)+mw2)C(b) +C(b)-c(Fw2)

C(b) + C(Rrd+C@b)c(m) +c(R&-c(Hki)

0: Result is zero1: Result is< 02: Result is> 03: Overflow

C( Rrl) + C( Rrl)+c( Rrd 0: Zero result, no carryC(Rrl) t C(Rrd-C(RT2) 1: Nonzero result, no carryC&r) +-C(~l)~~~2) 2: Zero result, carryC(b) ec(Rr+C(FW2) 3: Nonzero result, carry

Figure 16.2 Fixed-?oint Add and Subtract Instructions

The CC settings in the rightPost calm apply to all the instructions in the

same part of the table. It Is useful to note several aspects of the CC

settings for the logical instructions, which depend on whether a carry occurs

out of the leftmost position of Rrl, and whether the result is zero. Byreferring to the examples in Section 7, we can see that

(1) a CC setting of zero is possible for AL and AIR only if both

the first and second operands are zero.

(2) it is not possible to have a CC setting.of zero for SL and SLR,

because after the one's complement of the second operand and a

low-order 1 bit are added to the first operand, a carry must have

occurred if the result is zero.

Suppose we wish to store at ANS the sum of C(X) and C(Y), unless the

result is negative, in which case we must also add C(Z) and subtract 2:

the instruction sequence

L 59XA 5,y C(R5) = C(X) + C(Y)DC ll,ST B R A N C H I f N O T N E G A T I V EA %Z A D D C(Z)SH 5,=H’2’ S U B T R A C T 2

ST ST 5,ANS S T O R E - A N S W E R

will calculate the required quantity. Note that ST is used both as a symbol

and as an ins-M.&ion mnemonic; no confusion is possible, since the Assembler

identifies the instruction only by its appearance as an operation field entry.

Suppose we want to compute the sum of the first n odd numbers, where

the positive integer n $8 stored as a halfword integer at N;. consider the

following instruction sequence.

L H 31N G E T NL M b9r =F'O,Z,l,l' LOAQ R&R9 W I T H 012,ld

AODUP A R 690 A D D O D D JNTEGER T O S U M I N R 6AR 897 N E X T O D D I N T E G E R I N R 8SR 319 D E C R E A S E N B Y 1BC 7 , A D D U P B R A N C H N - l T I M E SS T 6,SUM S T O R E R E S U L T

One feature of this example is that all calculations inside the loop (third

through sixth instructions) are done using RR instructions; this technique

is occasionally useful in p~rams where processing speed is important, and

enough registers are available to allow all operands to be carried there

instead of in memory. The example is of course mathematically nonsensical

because we have expended all this effort to calculate n2 where a multiply

instruction would have sufficed.

To give another simple example of the use of saue of these instructions,

suppose we wish to canpute NEWT@ from the formula

NlB?ST@CK = @JST@CK+RECEIPTS.- SAL?%3

16-3

where all quantities are fullword integers small enough to guarantee that

no overflows occur. Both sets of statements Ibelow compute the desired

result.

L 2 ,Ot!XTOCKA &RECEIPTSs 2,SALESST 2,NEWSTOCK

L 2 ,OLDSfdCKA L 2,RECEIPtSS L 2,SALES 3S T 2 ,NEWSTOCK

The ccmpare instructions are useful in testing the relative magnitude@

of two operands; the results of the comparison are indicated in the CC

setting as shown in Figure 16.3.

I Operations ICC Settings

I

CRC 0: Operand 1 = Operand 2CH 1: Operand l< Operand 2CLR 2: Operand 1 > Operand 2

C L, L

Figure 16.3 CC Settings for Compare Instructions

-

The CC cannot be set to 3 as a result of a compare instruction. It can be

seen for the CR, C, and CH instructions that the CC setting is the same as

would result from performing SR, S, and SH instructions with the same

operands, assuming that no overflow occurs. In fact, this is how the

comparison is done by the CPU -- a subtraction is performed internally and

the CC is set to reflect the sign and the magnitude of the difference, which

would have been placed back in Rrl for the subtract instructions. Further

analysis of the original operands is required in the CJ3.J if the internal

result overflows. The logical-comparisons do give the same results as

arithmetic comparisons, since numbers in the logical representation are

always considered to be positive. The following instruction sequence may

help to illustrate the differences.

16-4

LM 093, =F’L ,O,-1.02147483647’CR I. 9 3 c c = 2CLR 1 . 3 cc = 1CR 012 c c = 2CLR 012 cc = 1CR 293 c c = 2C L R 2,3 cc = 2LPR 413 C(R4) = X’7FFFFFFF’, C C = 2CR 493 c c = 2C L R 4,3 c c = 1C O,=F’l’ cc = 0:C L 2,= F’+Z’ c c = 2C H l,=H'S' cc = 1C H l,=F’5’ c c =()

The last of the statements in the above example is a programming error that

occasionally occurs; note that the Assembler gives no indication of the

conflicting data types implied by the instruction and the operand.

As an example of the use of a canpare instruction, let us recalculate

the sum of the first n odd integers using a different scheme than before.

L H.-Lit

TEST CHHCL RARA HARA 1-iBC

S T O R E S T

4,=H’l’7147,N8 , S T O R E0170.0O,=H’ I’4907,=H’l’15,TEST4,SUK

C(R4) = A C C U M U L A T E D S U MC(R7) = C O U N T O F A D D I T I O N SC O M P A R E C O U N T T O C(N)B R A N C H I F N T E R M S A D D E DCOMPUlE N E X T O D D I N T E G E RC O U N T + C O U N TA D D 1, G I V I N G N E X T O D D T E R MA D D T E R M T O S U MI N C R E M E N T tOUNT 8Y 1B R A N C H T O S E E I F F I N I S H E DS T O R E R E S U L T

This example is rather cumbersome, but yields the desired result; we will

see that there are many ways to perform-the same computation with varying

degrees of elegance. It is worth noting that programming is often as much

an art as a science, since many different programs of varying effectiveness

can be written to achieve a given objective; an important part of learning

to program is understanding where efficiency can be increased.

As another example, suppose we wish to force the value of the integer

in R6 to be a multiple of 8, in such a way that if it is not already so,

the next higher multiple of 8 will be chosen. This would be required of the

16-5

relative origin assigned to a program: the Assembler chooses the next

higher multiple of 8 if the programmer assigns a relative origin which is

not already a multiple of 8. Consider the following segment of code.

SR 797 CLEAR R7SRDL 6,3 SHIFT 3 BITS INTO R7LTR 7,7 SEE IFTHE BITS ARE ZEROBC 0 BRANCH IF YESA 6,=~*i* IF NOT, ADD 1 TO R6

A SLL 6,3 MULTIPLY BY 8

First, note that we have cleared R7 by subtracting it from itself -- this

is the fastest and simplest way to do so and will be used generally except

in situations where the condition code must not be set. In such circum-

stances, an instruction such as L 7,=F'O' might be used, though

there are other ways which are sometimes more efficient. Second, we can

use a shift instruction to divide by 8, and since a double-length shift

is used, the "remainder" bits shifted into the three high-order bit

positions of R7 are not lost, which would be the case of SRL 6,3 had

been used. The BC instruction branches only if the remainder bits are all-

zero -- that is, if the number in R6 was already a multiple of 8. The same

'calculation can be done more simply:

A 7,=F'7' F#RCE CARRY IF P@SIBLESRL 7,3 DRJ~P #FF 3 BITSSLL 6,3 MULTIPLY BY 8

where in this case the presence of any 1 bit in the three rightmost bit

positions of the original number cause a carry into the 23 bit position

(that is, bit 28 of R6); the result is the same as before except for the

final CC setting.

To illustrate the use of logical arithmetic, suppose we are required to

perform additions and subtractions on 8-byte integers: double-length integers

too large to fit in a single fullword. Such operations are infrequently

required, but an examination of the methods used provides insight into the

properties of scme of the pertinent instructions. Double-length integers

will occasionally be encountered as products and dividends. Consider first

the problem of finding the two's complement of such a number. Since we

know that the two's complement can be found by adding a low-order 1 bit to

16-6

the one's complement of the number, we might proceed as in the following

example, where the number to be complementedlis stored beginning at ARG.

By C(RO,Rl) we mean the contents of the double-length register formed by

RO and Rl.

L O,=F’-1’L R 190 C(KO,Rl) IS A L L 1 BITSS 0,4RG 1’S C O M P L E M E N T O F H I G H - O R D E R P A R TS L,ARG+4 1’S C O M P L E M E N T O F L O W - O R D E R P A R TA L l,=F'l' A D D L O W - O R D E R 1 BITDC 12,NC B R A N C H I F N O C A R R YA 01 =J=‘l’ A D D C A R R Y B I T T O R O

N C s TM O,l,ARG S T O R E ’ C O M P L E M E N T E D R E S U L T- - -

D S OD A L I G N O N DOUBLEWORD B O U N D A R YARG c c FL8’123456787654321@-

The AL instruction in the fifth statement must be used rather than A

because the high-order bit of Rl is not a sign bit, but an arithmetically

significant bit with weight 231; if a carry out'of Rl occurs, it must be

detected and propagated into the low-order bit of RO, since there is no

--provision for having this done automatically. The same calculation is

performed by the following code sequence, but in a less direct and obvious

way.

LM O,l,ARG G E T D O U B L E - L E N G T H O P E R A N DLCR 010 COt’PLEMENT HIGH-IRDER W O R DLCR 1.1 C O M P L E M E N T L O W - C R D E R W O R DBC 8rX J U M P I F C(Rll = 0S O,=F’l’ S U B T R A C T 1 F R O M R O

X S T,yi O,ltARG S T G R E R E S U L T---

D S 03 A L I G NARG - DC FL8’987654.3456789’

In this case, we use the first LCR instruction to form the two's complement

of C(R0) immediately; that is, we have already added a low-order 1 bit to

the one's complement of C(R0). The following LCR complements the low-order

32 bits and sets the CC. Now if C(R1) had been zero, its one's complement

would be all 1 bits, and adding a low-order 1 bit would cause a carry out

the left end of Rl. For any other bit pattern, no such carry would have

16-7

occurred, and we must correct C(R0) by subtracting 'off the low-order bit

added during the execution of the first LCR.1

At this point it should be evident what we must do to add two double-

length integers; we will simply write a code sequence without further

explanation.

L rvl 0~14 G E T AA L l,B+4 A D D LGW O R D E R P A R T SBC 12,NC B R A N C H TF NI_) C A R R YA O,=F’l’ Pl?OPAGATE C A R R Y @IT T O H I G H - O R D E R P A R T

NC A 0,3 A D D HIGH-QPDER P4RTSs TM OtlrC S T C R E DQUBLE-LENGTH S U M- - -

C DS 0 FFSEPVE 8 B Y T E S , A L I G N E D8 DC FL8’222333444555’A ‘DC FL8’558777666555*

Subtraction is performed in the same way, except that the condition code

setting after the first subtraction will require explanation.

LlllSLBC-S

CAR SSTM- - -

c D S8 DCA c c

OILA GET FIRST OPE9AnSDl,B+4 S U B T R A C T L C W - O R D E R P A R T O F S E C O N D G P E R A N D3,ChR B R A N C H ’ I F T H E R E ’ S A C A R R YO,=F’l’ RfzDUCE C(RO) RY 1 ( B O R R O W 1)OTf3 SUBTRBCT H I G H - G R D E R P A R T O F S E C O N D O P E R A N D0,l.C S T C R E D O U B L E - L E N G T H D I F F E R E N C E

DF L R ’ 1 2 3 4 5 6 7 8 7 6 5 4 3 2 1 ’FL8’2345b769876543Za

In performing a subtraction, the one's complement of the second operand and

a low-order 1 bit are added to the first operand. If a carry occurs out of

the high-order bit position, then the result is correctly represented; if

a carry does not occur, then the resultcannot be correctly represented,

in the sense that we have tried to generate a %egative" integer in the

logical representation. Hence we must "borrow" a 1 bit from the next highest

bit position, which accounts for the subtraction of F'l' if the branch

condition is not met. It may be helpful to review the examples in Section 7

to clarify the cases of "overflowtt in the logical representation.

Multiplication and division work essentially in the manner described in

Section 8. Except for MH, a double-length register is required for product

16-8

and dividend, and the various operands are placed in the expected registers

before and after the operation.

For the multiplication instructions MR and M, the rl digit must be even;

as was the case for the double-length shift instructions, the even-numbered

register is the high-order half of an even-odd register pair, with the next

higher odd-numbered register being the low-order half. The multiplicand is

placed in the odd-numbered register, and the multiplier is the second operand.

The product replaces the original contents of the pair of registers. Thus,

the following instructions will produce the indicated results.

KR 2 . 7 C(R2,R3) = CH?3l*ClR71IYR 04 C(RO,Rl) = C(RlPK(RllMR F; , 3 CIR8tR9) = CtR8)*CIR91M 4,X C ( R4 t R-5 1 ‘= C ( R’S 1 *C t X 1M 121 = F ‘ 9 3 2 ’ C(RlZtR13) = CfR13W932LR 5,4 M O V E M U L T I P L I C A N D TO R 5MR 4 9 4 C(R4,R5) = CtR51*C(R41

Tne last two instructions illustrate a situation'where we wish to square the

integer in R4 -- the LR is required to place the operand into the odd-

numbered register; note that we could have used MR 4,5 also, giving

C(R5)*C(R5). The presence of the multiplier in the even-numbered register

does not cause it to be lost when that register is cleared at the beginning

of the multiply sequence, since the multiplier must be moved internally to

a separate register in the CPU; we can visualize the multiplication taking

place after the multiplier has been moved to the MDR.

It is important to remember that the product generated by the M and MB

instructions is 64 bits long. If we were to perform the following sequence

of instructions (note that 65536 = 216)

L 1, =A(X'lOOOO') C(Rld = 655’36IJ, K 091 S Q U A R E TTST 1,PRCDUCT---

PROCULT C S F

we would find that the fullword stored at PR#DUCT was zero and that C(R0) = 1;

and if we executed the instruction sequence (note that 32768 = 21s)

16-g

L 1,=A(X’10000’~ C(,Rl) = 6 5 5 3 6IT ‘1,=,4(x’8XN’) NLTIPLY B Y 3 2 7 6 8ST 1 T PI?O!IlUC T .

we would find that C(PR@DUCT) = -2'l. There are thus two situations the

programmer should be aware of: first,that the size of the product may b,e

such that it overflows the low-order register, and second, that whether or

not the high-order register contains significant bits, the leftmost bit of

the low-order register is not a sign bit, but contains an arithmetically

significant digit.

The MH instruction produces a single-length result, which is the low-

order 32 bits of the product of C(Rri) and the half'word'second operand.

Because only a fullword result is retained, rl need not be even, and a

specification exception will occur only if the effective address of the

halfword operand is odd. Because fewer shifts and adds are needed during

multiplication, some small economies may be achieved by the use of MH,

particularly on the smaller models of System/360. Thus, MH 5,=H’lOO’

is a simple way to multiply the contents of R5 by 100. If X and Y are both.-

halfword operands, their product may be found by wl‘i.ting

LH 9,XMH 9J

and R8 is undisturbed. And to square the halfword integer n at N we

could write

LH 6,~MH 0

Note that because both operands are halfwords of at most 15 significant bits,

the product will fit in a single register; the only halfword whose magnitude

requires 1.6 bits (namely -2l') when squared yields 230, which requires only

31 bits. We note in passing that none of the multiply instructions affect

the condition code.

-As an example of the use of a multiply instruction, suppose we want to

calculate A = B + G * D, where all quantities are fullword integers, and it

is assumed that all results are small enough so that no overflows occur.

16-10

L 7?G C(R7) ;= C(G)J.’ 6,D CfR6,d7) = r,):Dr, 7,B C(R7) = B+G*f)S’1 7,A S T C R E R E S U L T

Note that we have used the letters A, B, G, and D to denote both the names

of fullword areas of memory and the names of the contents of these areas;

this usage is typical of procedural languages, where little distinction is

made between the name associated with an area of memory, the contents of

the area, and the value associated with the contents. We will explore such

considerations further after more data representations have been discussed.

. As a second example of the use of multiply instructions, suppose we

wish to compute the sum of the cubes of the first n integers, where n is

stored in the fullword at NBR. We will assume that n is a small enough

positive integer that the sum is representable in a single fullwordP The

quantity k will be the index in the sum n

c k3.

k=l

s RL

>iPT LRI\: R8% RA RAChCS T

cJ,5/+,=I= ‘ 1 ’114Cl , 1014544,=F’1’4,NP,R12,RPT5,sw

S U M C A R R I E D I N R5K C A R R I E D Itv R 4 ’CtRl) = KCIRO,Rl) = K * KC(RO,Rl) = t( CUBEDA C C U M U L A ’ T E SUFU?Ib!CREMENT KCGhPARE T O U P P E R LIt’lIT8RANCH I F K N O T BIGGERS T O R E S U M O F C U R E S

A slightly different version'of the same program which counts from n down

to 1 follows.

SRL

1RPT LR

,y f-!.? KA ;ISRBCST

5,5/;,=F’l’4 , hr 2 R1940 , 40245.14,62,RPT5,SW

INITXALIZE SU# T O Z E R OC(R6) = 1 , USED A S C O N S T A N TI N I T I A L I Z E K T O C(N3R) = NC(Rl) = KC(RO,Rll = KazKC(RO,RLI = K C U B E DA D D T O S U MD E C R E M E N T K B Y 1R R A N C H IF K S T I L L P O S I T I V ES T O R E R E S U L T

16-11

Division is aLways performed using a double-length I;tvidend and remainder.

As was the case for the fullword ~aultiply kn%tructions, the rl digit must

be even, and specifies the register pair containing the?. dividend; -5he CC Ps

unaffected. As indicated in Section 8, the quotient replaces the iow-order

half orf the dividend in the odd-numbered regfoter, and the remainder replaces

the high-order part of the dividend in the even-numbered register; If a ,

valid quotient cannot be computed, a fixed-point divide exception occurs.

For example, to divide the double-length number in (R8,Rg) by the number in

R13, we can write DR 8,lj and to divide the same number by 10 we

could write D 8,=~'10' . To illustrate the use of a divide instruction,

suppose we want to compute the product of C(A) and C(B), an6 force the result

to the next largest multiple of 29 if it is not already a multiple. We wiU

assume that the product is small enough-that a fixed-point divide exception

will not occur when dividing by 29, and that the final result is contained

in a single fullword.

-

I‘r; t’ Y

As a final example of division, suppose there is a positive integer at

N which we want to divide by 10, and then store a rounded quotient at Q.

This means that if the remainder is 5 or larger the quotient must be

increased by 1.

I - 7,N G E - T N A S LCIeGRDEP !‘ART O F DIVI0ET\IDs 2 6~6 CLEAR HIGf+ORW? P A R T O F OIVIOEflD11 6, =F:ll()’ T?IVIDE BY 10C 6, xF’5’ CCIVIPARE REM/II I\JUER, 713 543 c 4 , 0 K A Y BP,ANCH i[F SMALLEY? T H A N 5A ?,=f-‘1’ CTHERhI S E R O U N D U P

Oi<AY ST L9 S T C R E RC2UN[?Er) R E S U L T

Suppose now that the integer at H taight be negative3 it is apparent that the

instruction sequence above will not work correctly, for two reasons.

First, the initial value of the dividend would not have a correctly extended

sign bit for negative arguments; second, because the sign of the remainder

is always the same as the sign of the original dividend, the compare

instruction would always (when C(N) is negative) cause the following branch

instruction to transfer control to #KAY independent of the magnitude of the

remainder. To obtain a correctly represented dividend it is simplest to

use the SRIIA instruction, as shown.

L l,=F’l’ S E T tJP ROUNDING B I TL 6lN C(R6) = C(N)SRDA 6,32 C!RbrR7j = 64-811 D I V I D E N Dt3C 11,OIV J U M P I F NGN-NEGATIVE DIVIQENO

* LCR 1,l CTHERWSE S E T IIOUNDi)FF: T O - 1cxv D 67 =F'lO' D I V I D E B - Y 1 0

L P K 6,6 AhSOLUTE V A L U E O F R E M A I N D E Rc 6,=F’S’ CUMPARE T O 5BC 4 ,OKAY B R A N C H I F SYALLER T H A N 5AU 791 A D D CORRECTLY-SIGNE3 ROUNDOFF

O K A Y ST 7rQ S T O R E R O U N D E D Q U O T I E N T

-We note that a simple check may be made to insure that a fixed-point

divide interruption does not occur: if the inequality

IC(Rrl) I< l/2 1 second operandi

is satisfied, the quotient can be computed correctly.

16-13

17. LOGICAL OPERATIONS ANC INSTRUCTIONS

The basic capabilities of a ccmputing system are derived from the many

interconnections of basic circuits which'perform simple logical functions.

Sane of these same functions may also be performed on operands in memory and

in the general registers through the use of logical instructions, though

their applications are of course different. We will discuss some of the

instructions which perform logical operations and give a few simple, example6

of their use; other important u6es of logical operations will be treated

when Some of the SI instructions are examined.

Although it is not what we usually would consider a logical instruction,

the LA (Load Address) instruction is classified as such, and has many and

varied uses in System/360 programming. It is a very simple RX-type instructian:

the effective address replaces the'contents of Rrl, with the high-order byte

being set to zero. Thus, for example, a positive integer n between 0 and

4095 can be placed in a register by executing an LA r,n instruction,

where the index and base digits are implicitly zero and the displacement

contains the constant n. Instead of writing L 2 =F'l't which requires

8 bytes (4 for the instruction and 4 for the constant), or LH 2,=H'l*

which-requires 6 bytes, we can write either LA 2,l or LA 2,m,o)

which requires 4 bytes and less execution time, because no memory access is

required. Also, because LA does not affect the CC we can clear a register

without disturbing a CC setting which may be required at a later point in

the-program. For example, suppose we wish to add C(A) and C(B)' snd clear

the result to zero if it overflows, without changing the CC setting. The

two instruction sequences which follow perform the desired task.

L 04 L OtAA Ot0 A Ot08C 14*ST BC 14+SfLA OtO L O*=F'O

ST ST 0,ANSWER

17-l

ST ST 0,ANSWER

Because the m instruction canputes an effective address, it 8160

provide6 a rsimple way to increment the content6 of a register byla emalL

positive amount. For example, LA 4,1?10,4) will increase the

content8 of R4 by 17, if the original contents'of R4 are between -2.7 and

2244.8. This restriction is of course due to the fact that the high-order

byte of the register into which the result is placed will be oar%' to aero;

thus the use of LA for incrementing registers is usually limltad Lo ca6e6

where the quantity being incremented is an address or reasonably ramall

integer. For example, suppose we want to perform the shifting operation

described in example 6 of Section 15, where it was required t&t the fullwordat N be shifted right enough places so that its rightmost bj+t $6 a 1 bit;

we niLI also require that the half'word at C@UNT contain the in&r of

positions shifted.

1L

SMWT S R D L17-RLA

- 0CSLDLS TSTH

Q*N3,=F’-1’4tl5,s3.luI.3)10,SHIFT491 ’%N31COUNT

G E T I N T E G E RI N I T I A L S H I F T C O U N TSHXFT A BIT I N T O R5T E S T S I G N O F R5f6JCREMENT R 3 B Y 1B R A N C H I F R5 N O T N E G A T I V EMOVE BIT B A C K IN P L A C EWORE S H I F T E D I N T E G E RS T O R E S H I F T C O U N T

By setting the shift count to -1 initially, we guarantee that the correct

value will be in R3 when we exit from the loop; the first time the LAinstruction is executed, the result will be zero and the setting of the

leftmost byte to zero is what we want. The placement of the M instruction

between the LTR and the ensuing BC was done to show that no adverse effects

are caused; one would normally place the LTR just before the BC becau6e the

relation between the two is then clearer to anyone reading the program,

A third use of the LA instruction, and possibly the most important, is

in generating addresses for actual operands in memory. For example, we may

require the address of scme operand to be in a given register during the

execution of a segment of code. Suppose we Want to add three integers, and

branch after all additions are cmpleted to @ERR if no overflow occurs, and

to ERR1 if one or more overflows occur. Let the integers be stored in

successive fullwords beginning at Q.

17-2

L ALABCL A

OK1 ABCRBC

9,NOERR2tQZ&+414,OKl9,ERRl2rQ+8149915tERRl

S E T B R A N C H A D D R E S S F O R N O E R R O R SG E T FIRST I N T E G E RA D D S E C O N D I N T E G E RB R A N C H IF N O O V E R F L O WS E T B R A N C H A D D R E S S F O R 1 O V E R F L O WA D D THIRD I.NTEGERB R A N C H I F N O O V E R F L O WB R A N C H , S O M E A D D I T I O N O V E R F L O W E D

It should be noted that the instruction with a mask digit of 15 could also

be written BC 1JRRl without affecting the operation of the code,

since the inetructicm is reached only if the branching cadition for the

immediately preceding instruction is not met; by specifying a mask of 13 it

is clear that the branch must always be taken. There is one important

assumption underlying the use of the two LA instructions: the instructions

named @ERR and ERRl must be addressable, since the LA instruction will

simply perform the address ccmputation specified by the base and displacement

assigned by the Assembler. As mentioned earlier, we are assuming that all

symbols (and expressions 'such as Qt8) are 'addressable and that the appropriate

-- base register information has been established elsewhere in the program.

It is occasionally easy to forget that the symbols used in LA instructions

must be addressable, since no reference is being made to any memory.location -- only an address is being generated, and no checks for the

validity of that address are made.

We will give a number of examples later where the LA instruction can

be used to give-the effect of indexing for instructions for which indexing

is not actually possible, namely RS, SI, and SS instructions.

The three logical operations provided by System/360 are AND, OR, and

EXCLUSIVE OR. These are relations between pairs of bits, which produce a

result depending only on the values of the two bits participating in the

operation. The effect of the three operations is given in the figure below.

OR

Figure 17.1 Logical Functions in Syst&360

17-3

In the first case, the result bit is 1 only if the first AND the second

operand bits are 1; in the second case the result bit is 1 if either the

first s the second operand bits (or bcth) is 1; and in the last case, the

result bit is 1 if either the first OR second operand bits is 1, EXCLUSIVE

of the case where both are 1. Henceforth we will abbreviate EXCLUSIVE OR

by XOR. For the instructions listed in Figure 17.2, the operands are fullwords;

however, the result of the operation is obtained by matching the corresponding

bits of each word, with no interactions between neighboring bits. A few

examples will help to clarify this. As before, "Fw~" means the fullword

second operand specified by the effective address.

cMnemonic Type Action CC Settings

NR RR C(Rrl) +-C&l) A C(R&) 0: all result bitsN Rx C(Rrl) tC(Rri) A C(m2) are zero

plR RR 1: result bits arePi

C(Rrl) tC(Rrl) v C(Rr2)m C(Rrl) +-C(Rn.) v C(m2) not all zero

XR RR C(Rrl) tC(Rrl) @ C(Rr2)X Rx C(Rrd c-C(Rrd 03 C(m2)

b.

Figure 17.2 Logical Instructions

Suppose C(R4) = 0123456716, and C(R9) = ~~~96521~~. Then if theinstrutitions indicated are executed, the final contents of R4 will be as

shown below the instruction.

NR 4,Y (dR 4,Y XR 4,Yo1~?1$211~ EDAB656716 E~8A2046~~

To see in more detail how these results are obtained, we will examine the

fourth hexadecimal digit of each case in binary form in the figure below.

AND OR I EXCLUSIVE OR I

Figure 17.3 Examples of Logical Operations

17-4

One important use of the N and RR instructions is for "masking"

operations in which it is desired to isolate or extract portions of a word.

For example, suppose we wanted only the third of the four positive integers

packed in the data word illustrated in Figure 14.7. This could be done by

shifting as follows:

c 0,DATAWORD GET INTEGERSSRl O& D R O P O F F F O U R T H O N ESRDL 1913 M O V E T H I R D INTO R lSRI. 1,19 POSITION FOR STORINGST 1,THIRO

or as follows:

L OrOAfAWORDSLL 0913 D R O P O F F F I R S T A N D S E C O N D I N T E G E R SSRl 049 D R O P O F F F O U R T H , PQSITION F O R S T O R I N GS T O,THXRD

(Ifb the integers were allowed to have negative-values as well, the SRL

instructions would be replaced by SRA.) However, the following instruction-- sequence using a logical AND is considerably faster:

t 1,DATAWORD AAAAAAAAABBBBCCCCCCCCCCCCCDDDDDDN 1rMASK OOOOOOOOOOOOocCCCCCCccccccooooooSRL I,6 0000000000000000000cccccccccccccST 1,THXRD S T O R E D E S I R E D I N T E G E Rwe-OS OF A L I G N T O FUiLWORD SOUNDARY

MASK D C X’OQ07fFCO’

First, note that the IX3 OF is required to insure that MASK falls on

a fullword boundary -- type X constants have no implied alignment. Second,

the mask hals 1 bits only in those positions which correspond to the bits

(labeled "C') of the third integer in the data word* When the N instruction

is executed, all of the bit positions in which the msk is zero will be set

to zero, since a 0 bit ANDed to any other bit gives a zero result. In all

of the mask's bit positions which are 1 bits, the result is the same as the

original bit from the data word, because a 1 bit ANDed to any other bit

gives a result identical to that bit.

To illustrate the use of a logical j!!R instruction, suppose we want to

store a new value for the third integer into the proper part of the data mrd.

17-5

We can do this by shifting the various pieces into place:

L 0,DAXAWORD GET fNTEGERSS R D L O& M O V E s=QURXW XNTO Rl1 OoNEWSHl[RD G E T N E W V A L U E OF T H I R D INTEGERS R D L 0 9 1 3 MOVE fT IN ?dPTH FOURTH1 O,DATAWORD GET INTEGERS AGAINS R L ovr9 D R O P OF?= THIRD A N D F O U R T HS R D C 0113 M O V E F U L L WORD I N T O R1S? J,~DATAVORD S T O R E N E W DATAWORD

Alternatively, we can use the logical AND and $R to do the same:

1 OsCAFAk!ORD GFT XNTEGERSN O,,MASKA CLEAR SPACE FOR 7'HPRDL 1~NEWHHRD G E ? N E W V A L U E O F WrtRD XNTEGERSLL 116 SHIFT lNT0 PROPER POSITIONOR 001 a0R' IWO PLACEST O,DAfA!GORD STORE NE!4 DATA14URD--IDS OF

MASKA D C XaFFF8003F’

In this case, the N causes all the bit positions into which the third

integer will be placed to be set to zero. The $R instruction then forms-the logical OR of all the bits of RO and Rl. Since the only bits in Rl

which may be l's are in the 13 positions corresponding to the space provided

in the word in RO, and because the result of ORing a 0 bit to any other bit

is the value of the other bit, the effect is to insert the new value of the

third integer in its proper position in RO. This of course assumes that the

contents of NEWTHIRD is a positive Integer of at most 13 significant bits;

if not, an instruction such as N l,MASK should be inserted before

the #R to insure that no extraneous bits are ORed into RO.

The-X and XR instructions are used mainly for inverting the value of a

bit or a group of bits: it can be seen from Figure 17.1 that the result of

XORing a 0 bit to any other bit is to leave it undisturbed, and the result

of XORing a 1 bit is to invert it from 1 to 0 or vice versa. Thus, for

example., we can form the one's complement of the number in R7 by subtracting

it from a word of all 1 bits, or by executing X 7,=F’-2’ which does

the same thing. We can rewrite the example above to use an X instruction

(though in a somewhat roundabout way) as follows:

17-6

t 0,OAtAWORD G E T I N T E G E R S0 OtMASK S E T THIRD Sf’ACE T O 1 B I T SX OgMASK NOW S E T THEM T O Z E R O Sc 1,NEWTHIRD ETCSLL 196 ETCN 1 *MASK B E S U R E T H E R E A R E - N O E X T R A B I T SOR 091 .ffC *S T OdMtAWORO- - -OS OF

MASK DC X’OOO?FFCO’

As another example of the use of the XOR function, suppose we again want

to force the integer in Rg to be the next larger multiple of 8 if it Is not*already a multiple of 8; consider the following code sequences.

A ‘lr’F.7’ F O R C E C A R R Y S F A N Y 1 B I T SN 7,=F’-8* S E T L A S T 3 BITS T O Z E R O

ml6 is the fas es method, but space is required for the constants.t t

LA 017 CfRO) = 7AR 9,O F O R C E C A R R Y IF ANY 1 BITSOR 9,O F O R C E T H E T H R E E 81TS T O 1’SXR 990 N O W S E T T H E M T O Z E R O

In terms of space required, this method is superior to the ones illustrated

previously.

We will find that the logical operations have considerable use in

examining and manipulating individual bits in memory, particularly through

the use of certain SI-type instructions. As a final example, suppose we

dre required to shift the integer contents of R6 (assumed nonzero) left so

that the first significant bit is immediately to the right of the sign bit,

and store at N@M the number of positions-shifted.

SR 8~8 S E T S H I F T C O U N T T O Z E R OSHIFT SLA 691 S H I F T L E F T ONE BIT POSITltlN

8 C 1,FINIS IF O V E R F L O W , J U M PLA 8,1(0,8) I N C R E M E N T S H I F T C O U N TSC 15,SHXFt T R Y A G A I N

FXNIS SRA 6.1 R E P O S I T I O Nx &,DIGft R E S T O R E T H E 1OSt B I TS T 8 , N O R M S T O R E S H I F T C O U N Tw-1)

NUORM OS FJUGIT D C %‘40000000’

17-7

from the sign bit has &en shU.‘ted*out of bile RQcrit$.on 3. The right sh%Pt

qlove8 everyth ing back , bu$ JnFatead of qeeterjw the Worst bit, extends theeign bit into the second b%t position O$ Ni #k!bti whtcb the most aigniffc:ant

bi t was just lost , Since the s ign ia knm t6 be the oppoaeite of the 5c1s-tbit, the X operation Inverte the second bit %o give the deoirsd resulta

17-8

18. LOOPING, INDEXING, ANDSIMPLJ3ARRAYS

Much of the power of a digital ccmputer derives from its ability to

execute sequences of statements repetitively until some condition has been '

satisfied. Programming with loops is therefore basic to most programs of any

size and complexity; we will examine in this section several instructions which

simplify the coding of loops, and sane typical uses involving arrays of data.

As a simple example which will be used to illustrate sane of the basic

principles, suppose there is a string--- a one-dimensional array -- of 80 bytes

beginning at STR and ending at STR+79 which contains character data in the

EBCDIC representation. We are required to scan the string and replace all

special (non-alphanumeric) characters by blanks: specifically, any character

with representation less than C'A' (referring to Table III, itcan be verified

that this is equivalent to 193~o=X'Cl') should bereplaced by C' ', which has-

representation X'40', so that letters and digits will be unchanged.

First, consider the following code sequence, which performs the desired

processing in a straightforward but rather clumsy way.

SRLRLAL ALA

GETChAR ICCR8CS T C

O K A Y LACACf3C- -

OdJ1902,C’A’ ’3,C’ @4,STR0,0(0*4)09210 (OKAY3,0(0,‘4~ -4,1(0,4)1,1(0,1)L,=fWO4,GETCHAR

-

CIIAKACTERS IhSERTED lNTCl R O ’CHAtiAilTtA CCNr\tT I N RI* XNlTlALLY 0C(U) = x’ocoooocI.’Cik3) = x’00000040’FfKST BYTE AGORESS I N R 4GET t$YTE FROP S T R I N GCOWARk TO L E T T E R ‘A’d&AivCti Ic; L E T T E R OR D I G I TOTHttihiSfi R E P L A C E BY A B L A N KhiCt(tMENT C H A R A C T E R A D D R E S S 8Y 1IiUCr(tASii C H A R A C T E R C O U N T BY 1CurWAKE TO 8 0&HAhdh-i IF L E S S T H A N 8 0 T O D O M O R E

STR CC CL80’THIS.IS~~O~dYT~S~TO,6E~SCANNED~F~R~SPEClAL-C~A~#

We will see later that this particular problem can be solved more efficiently

in a variety of ways. For the time being, note that the character comparisons

are made in the rightmost bytes of registers 0 and 2, and that the address of

1 8 - 1

the byte to be examined is regularly incremented in R4 after being initialized

to the location of'the first character. The branch inrtruction at the end of

the loop must branch if C(R1) is less than 80, not if it is less than or eQua1

to 80, since the final test in the latter case would cause the byte at STR&O

to be examined and possibly changed.

A second version of this program which makes use of the indexing capabilities

of the IC and STC instructions follows.

- A trivial difference in this version is that the fullword containing the

EBCDIC representation of the letter A is now in memory, specified by the literal

=A(C'A') rather than in R2 as before: note that =F'193' and =A(X'Cl') would

give identical results. The addressing of the byte to be exgmined is now

computed using Rl as an index register. The first time the instruction named

GETCHAR is executed, C(Rl)=O and the effective address generated will be the

actual relocated address of STR, assuming that the necessary base register(s)

have been set up correctly. On the last execution of the IC instruction,

C(R1)=79 and the last byte of the string \wi.ll be inserted into RO for

examination. When the LA instruction named '@SAY is executed, C(R1) will be_increased to 80, the branching condition for the final BC instruction will

not be met, and control will pass to the following instruction.

To illustrate another use of indexing, consider the example of Section 17,

where three integers at Q are to be added; in this case, however, after the

sum ia complete a branch to N$I!ZF?R is to be taken if no overflows occurred, to .

ERR1 if exactly one overflew occurred, and to ERR2 if two.

SR1A8CL A

Al A8 CL A

A2 8CE 8 C

8C8C

lrl, ' SiiT UViRFLOW CGUNT T O Z E R OO,Q biT FIGT INTEGERO&l+4 AI1)L) SECMID14,Ai t3ttAILCt-l I F N O GVERFLOW1,41011) IiWICATi ONE OVERFLOWO&I+8 Atid THXKU I N T E G E R14ri2 6KAILCH IF N O O V E R F L O W 11,4(Ot.H INL)ACATi A N GVERFCObd15,8t 1) diIAMI3-i Ii’d- B R A N C H T A B L E15,NOERH O-ERiUiIK B R A N C H15vERRl A-iiKi+OR &RANCH15,ERRZ L-EI(IIOK bRANCH

When the instruction named A2 is reached, Rl contains four times the number

'of overflows. This number is used as an index in computing the effective

address of the BC instruction at A2,-which will be B, B+& or Bt8; the

appropriate branch instruction will then cause control to be transferred to

the desired location. Note that B need not be on a fullword bouildary; the

index in Rlmust simply be incremented by 4 to account for the length of the

BC instructions. Such branch tables often provide a fast and effective way-- to route control to different parts of a program.

We will now consider the Branch on Count (BCTR and BCT) instructions,

which simplify counting operations such as thosein the above example. As .

was the case for the BCR and BC instructions, the branch address is obtained

either from Rr2 for BCTR (unless r2=0,I in which case no branch can be taken)

or fra the effective address for BCT. In this case, after the branch

address is canputed, the branching condition is determined by first algebraically

reducing the contents of Rrl by one, and then branching unless C(Rr&)=O.

Note that the CC is unchanged and has no effect on the branching condition.

We-can rewrite our first'example to use a BCT by working backwards along

the string of characters from STR+79 to STR, which also allows the use of

the same quantity both as an index and a counter.

SR 090LA 1980C A 29C’A’LA 30 ’XC OrSTR-l(l)CR 2,O8 C 1 2 ,OKAYSK 3,STR-l(l)8CT ItNEXT

CLkAtt ROSEf CiA TO N U M B E R OF QASSESCoi2) = L E T T E R AcdK3J = &LA&KG E T CkiAttACTERCCitiYAKt ‘Aa TO C H A R A C T E RBi+ANCH 1F SATXSFACTGRYuTtiEK~I~k BLCT IT OUTCuvrLT bUWhi 8 Y 1, JlJII?P IF N O T 0

18-3

The use of the expression STR-1 in the second operands of the TC and STC

instructions is dictated by the fact that the possible values of C(R1) run

between 80 and 1, rather between 0 and 79 as before. This can be thought

of as reflecting a difference in the enumeration of the bytes in the string:

if we number them from 0 to 79 they would be addressed STR(l), and if the

bytes were numbered (in perhaps a more natural fashion) from 1 to 80, they

must be addressed STR-l(1). On the final pass through the loop, C(Rl)=l;

when the BCT instruction is executed, C(R1) is reduced to zero, the branching

condition is not met, and control passes to the next seguentrlal instruction.

One immediate gain in program efficiency can be seen simply by counting the

instructions inside the loop: we have reduced this number from seven to five,

which will give approximately the same ratio in processing speeds.

' The BCT and BCTR instructions arc especially useful in situations where

a certain number of passes through a loop is, needed, and no special attention

must be paid to indexing quantities, To illustrate several uses of these

instructions, consider the foIllowing variations on some examples from previous

- sections.

(1) The fullword at NBR contains a positive integer n; compute the sum of

the cubes of the first n integers,

LSR

NEXT LRHRNHAR8CTS T

4,NBRfit5l#4O#l094Ll4,NEXt5,SUM

(2) The halfword at N contains a positive integer n; store at NSQ the sum

of the first n odd integers.

SR 010 U.tAN SUM T C Z E R O- Lh 1tN bkf N hU,JM MkKGHY

CGOP LA 2,0(1,1) d CW&T+COUNT )’ I N R 2BCTR 2 . 0 2 * CWNT - 1AR 0 . 2 AriO Ju S U M8CT 1,LOOP i4kWCE COUNT A N D ORANCHST OaNSQ

18-4

Because n is contained in a tiMword integer, we may use the LA instruction

to compute (n + n) in one step, since the result is known to fit in the

rightmost 24 bits of IQ. The following BCTR instruction cannot branch, s:i_nce

r2 = 0; hence the only effect is to reduce C(R2) by one, as required.

(Remember that the k-th odd integer is 2k-1).

(3) Find the two's complement of the double-length integer stored at ARC.

LM O,lsARC &if r)uUdlE-LEhGTH N U M B E RLCH 010 CdMPLEMENT HIGH-GRDER PARTLCR 191 ~WWCEMEIL? LC’Jli-CROER P A R TEC 8.X ~KMvCH IF “ C A R R Y OUT OF Rl

e BCTR 0,O OTHERhXSE R E D U C E C4RO,, f?Y 1x STM O,l,ARfj SWUz CuKPLEP&NTED R E S U L T

This is identical to the exa@pl.e in Section 16 except that the BCTR replaces

S 0,pF'l' and thus the CC setting may be different when the S!IM is

executed. The BCTR instruction with r2=0 may be used in this fashion anywhere

in a program; it is shorter and faster than subtracting a constant 1 from

memory, but has the possib3.e d$sadvantage that the CC is not set.

- As a further example of the use of the BCT instruction, we present

below two examples of program segments which store the cubes' of the integers

from 1 to 10 in a table of ten successive fullwords, the first of which is

labeled .CUBEL

LA 4,lOHUT LR 394

MR 283KR 2t4CR 114xc 192S T 3,ClJBE-4L 1) .0C7 4,MULT

ci( R4d = N U M B E R T O B E C U B E DMiJVE 17 TO R 3StiUAKE iiAN0 Cuf$ X TSkT UP INDEX XN RlMU’flPLY 8Y 4 F O R FlJLLWURD L E N G T HSfuRE id C O R R E C T T A B L E P O S I T I O Nt)RAiJCH dACK 9 JAMES

In this case we have used the integer argument being carried in R4 to index

the desired word in the table; since the table entries are fullwords, the

index must be multiplied by four for successive items, which is why the SLL

is used. Because the first entry in the table corresponds to 1 cubed, the

expression in the operand field of the ST must be CUBE-4 so that the address

of each entry will be correctly calculated'. Another method of doing the same

calculation is as follows.

1 8 - 5

L AL ALA

MUT LRMRr.RS TL ALACR0C

lrCUBE40~42,CUBE+9*43915r34134,35,060,1)3,1{0,3)1,460,Z)19212,MULT

In this case an explicit address in the ST instruction is used, rather than

an implied address as in the first method. This is because the loop termination

condition is determined from address arithmetic rather than frcm tests on any

of the quantities being calculated in the loop; we will see that cases often

arise where it is convenient to perform such addressing calculations explicitly,

rather than rely on the Assembler to assign all bases and displacements. The

"index" of the entries in the table may be thought of as running from 0 to 36in steps of 4.

In most of the programming examples we have examined in which loops-were used to perform some iterative task, the termination condition depended

on some kind of counting tiperation. More specifically, many such applications

require that some quantity be established as an indeF,whose value is changed

regularly by an increment, compared to some compkrand, and a branch then be

made depending on some condition established by the comparison. Note that the

term "index" as used here is meant only to indicate the variable quantity which

controls or determines completion of the‘loop; it may or may not be related

to a quantity to be used as an index (that is, specified by an index register

specification digit) in an RX instruction, as in the two examples above which

compute a table of cubes. In the first illustration, the index of the loop '

(in R4) is also used (in Rl) to index the ST instruction; in the second illus-

tration, the index of the loop is the address contained in Rl, but no indexing

is performed in any of the RX instructions. The increment may be a negative

quantity, in which case it might be more appropriate to call it a decrement;

rather than try to use names to distinguish the sign of the quantity to be

added to the index, we will assume that the increment can be positive or

negative.

For the Branch on Count instructions, the quantities involved are all

impLied by the instruction: the index is in Rrl, the increment is -1, the

18-6

the three functions of incrementation, comparison, and conditional branching,

but with much greater flexibility.

Both RXH and RXJ-22 are R&type instructions requiring two register

specifications digits rl and r3, as indicaaeil in Figure 14.3,. Like the STM

and LM instructions, the use of reg;:'-::;ters other than Rri and Rrz may be

implied, but in a less simple way.+ Tk in&x is always ill Rrl, and the

increment is always in Rr3= The comparand is contained either in Rr3+1

(if r3 is even) or in Rr3 (if x-3 is odd), That Is, if WC wrZte l.?XLE 0,4,NEXT

then the index is in RO, the increment is in R4, and the comparand is in R>*

whereas if we write Bxu3 'Q,~,JXlZT the index is again :A R3, bu;; both

the increment and the comparand are in R'j. There is a aimple notational

device which illustrates the fact that the comparsnd is contained in

an odd-numbered register (if r3 is even, the comparand is in Rr3+1, and if

r3 is odd, the comparand is in Rr3): FE willwrite Rr+l to indicate that the

register containing the comparand may be determined by ORing a 1 digit into

the r3 digit. Thus R8Vl refers to R9, and RgVl is t91e same as R;g. The

operation of BXH and RXLE, w'hich is diagramqed in E'igure l&l, is as follows:

the sum of the index and increment is cagputed internally and then compared

algebraically to the ccmparand. Nhet'ner or not the branching condition is

met is noted -- for RXH this means that %he sum is algebraically greater

than the comparand, and for BXIJ3 thab the sum is algebraically less than or

equal to the comparand. It is important to observe that the branching

condition is not reflected in a setting of the CC but is determined internally;

none of BCT, BCTR, RXH, or BXI.3 change the CC. The sum then replaces

the index, and the branch is taken if t,he branching condition is met. Note

that because the bra.nch address is ccn~.1~.-&.3. during the %ecode" portion of

the instruction cycle before .incremcnta~t;ion ttikes place!, the effective

address may not be as expected if rl and b2 are the same (unless both are

zero, which is unlikely since the branch address would have to be less than

4095) l Note also that the comparison takes place before the sum replaces

the index; we will give sCPne examples of situations where this is important.

The upper portion of the figure below is a verbal description of the

execution of BXH and lXLf2; the lower portion indicates explicit register

usage by the two instructions.

“““““““““““““““L”““*““““““““““““””””””””~””””””““““~~“~~“”””””

I

I I

I * . , * I

&code; II

:Ccmpute Compare sum SUIR Branch ' I . .

compute index + +branch Tincrement

to ccmparand;+ conditiondetermine

replaces+index met ?

no ! )FetchR

I A *address : branch cond. b- I

Ii I

III

I

!

Execute I l3ranch Qddr I

*cm II

t

1 - -’I

L ““““““““““““““““““-“““““““““““““””””””””””””””*““~~““““““-”” 1.

“““““““““““~“““““““1”“““““““““““”””””””””””””””~~““~~““““”””””aI I I I

I

:- -->sw31> C(Rr3vl) ?.4 no

I BXH ?

\ 1 !Decode; ; C&l)+compute Ibranch .y c(Rr3)

,suIn 4

/h4 ' C(Rd

address I 4SUmup-.-".2 Yes

m 4

>Sum 5 C(Rr3Vl) ? - no4

!iI ,

I

' )FetchI I ,-

Figure 18.1 Operation of BXH and BxIJ3 Instructions

To illustrate the use of BXH and BXLE, consider the example given at

the beginning of this section, where we wish to replace non-alphanumeric

characters by blanks. We will rewrite the code sequence to use a BXLE:

instruction.

18-8

LM 0,3r=F’OvO~1,79’* ChARACTERS XNSERTED fi’jTU ii0,’ IiWi?X fN RI, I N C R E M E N T IN R:2,,4 AIIG CCMPARANO I N R 3 .

LM 4,5,=AK'A!,C' 8)8 L E T T E R ‘ A ’ IN R4v AND A BLANK I N f-3.GETCkAR l[C 0,STRt 1) i;EjT A C H A R A C T E R F R O M T H E STRING;

CR 014 ClljMPARE T O L E T T E R “Au I N R 4BC 1OvAlPHANbM 6tiACUCH IF ALPWAIWMERICS T C 5,STRu.l LVbEi-wISE STGRE A B L A N K

PLPkAfWM BXLE tq2vGETCHAR irvi&~MErqB AN0 B R A N C H

Note that the values of the index run fror;l 0 to 79; when control reaches the

BXW instruction, the increment in R2 (namely +l) is added to C(RO), and

because R2 is an even-numbered register, the sum is camp&red to the canparand

C(R3) a' If the sum is less than or equal to 79, the branching condition ismet and control will. be transferred to the instruction named GJSTCRAR after

the sum is placed back in Rl. When control finally passes to the instruction

following the RI&E, the contents of Rl wili'be 8010.

To give an example where the use of ST;E is perhtqq more natural, we

will rewrite the code segment'which canputes a table of the cubes of the

first 10 integers, starting at CUIEL

CA 711 1. t<:TIAL I N T E G E R f 1LR 8~7 Cbribi = 1 FOR INCREMENTING NSR 414 SEX- lNDEX T O ZEROCA 2.4 INCMEMlbNT Q F 44 F O R !NDEXL A 3936 Gu’WAI;(ANO = 36~ IN R 3

Mb11 LR h-t N IN RlKR 011 d\Wlu.R 097 I\ CUBEDS T l,CU8E(4l SruKE fN fA8LEAR 79% U\Cit,EAS~ N B Y tBXLE 4,2tMUlT UUXEASE fNOEX B Y 4 A N D C O O P

This segment of code has been written in such a way as to use fewer instructions

inside the loop, at the expense of some extra instructions outside the loop.

The following two code segments perform the same calculation, but are set

up sltghtly differently.

18-g

LA 791LA 494LR 294L A 5140

MULT LR 117HR 011fiR 017S T ld&BE-4(2~L A 7,1(0,7)BXLE 2,4,MUCT

lNlTIAC V A L U E O F N * 1

In this example, the index runs from lC to I+0 in steps of 4, rather than from

0 to 36 as previously. In general there -is no difference between the two

methods, except that the second method can he conceptually simpler: since

the integer N runs from 1 to 10 by steps of 1, the multiplication by 4 to

account.for the len<$h of the fullword result :tiakes it natural to have the

index run fram 4 to &O in steps of 4. We will. exami.ne SM~ cases shortly

where such considerations are important. The use of the LA instruction can

yield very slightly increased speeds, since it is faster on some models of

System/360 than an AR instruction; the programmer interested in such details

should consult the instruction timing tables f'or the particular CFTJ he is using.

A variation on the above example is given below, where the index and comparand

quantities are addresses.

LALAAAAA

MLAT LRMRMRS TCABXLE

4,CU3E+0*42943,CU8E+9*479111,71091110,lllrot0,4)7r1(0,7)4,2,MULT

To illustrate the use of the 3ZU-I instruction, two of the previous code

segments will be rewritten so that the indexing runs in the opposite direction.

L A 7,lOA 8,=F’-1’LA 4,40i. 2,=F'-4'Sd 3*3

FLLT CR 1,7MH 017MA 017ST lrCUd&-4444AA 74BXh 4,2,MULT

18-10

When the instruction following the BXH is reached, the index in R4 will be

zero. In fact, we can use -4 for both the increment and comparand as in the

following example.

LA 7&lL A 4,36L 5,=F”-4’

IVU.J LR 187r!R 097t?R 097S T l,CUBE(4~BCTR 7 9 00Xl-i 4,5,MULT

In this' case the r3 digit is odd, so Rr3V 1 is the same register as Rr3;

the BXH will increment the index in R4 by -4 and branch until the resulting

sum becomes -4 also, when control will gass to the instruction following.

Some specialized uses of m and EKLl3 may be obtained by various

combinations of register specification digits. For example, suppose the

contents of an odd-numbered register such as R9 is zero. Then the instruction .

BxI& 4,9,x will branch to X only if C(R4) is less than or equal to zero;

similarly, Em 4,9,x would branch to X only if C(R4') is greater than

zero. Since the B[XH and RXLJ3 neither set nor test the condition code, this

technique can be used in situations where a condition code reflecting the

state of the contents of R4 is not available, or the current CC setting must

be undisturbed, or if it is desirable to avoid using instructions such as

LTR followed by a BC.

Suppose we want to perform the inverse of the BCT instruction, namely

increment a register by +l and branch. If C(R7)=1 and the contents of R2

is scme integer greater than zero, then - EKH 2;7,X will branch to X

after incrementing C(R2) by 1 unless the sum overflows. Similarly, if there'

is same negative integer in R2, BlfT;;Li: 2,7,x will branch to X so long

as the resulting sum does not exceed +l. If C(R4)=1, the instruction

BXH %4,X will increment the contents of R'j by 1 and then branch to X

if the sum does not overflow; this example is instructive because the index

and comparand are in the same register. If the canparison was made after- -the sum was placed in R>, an equality would always be indicated and the RXl3

would never branch. Tricky usage of RXH and l3X.U as described above is

relatively rare, and these instructions find their major use3.n applications

such as table searching and loop control.

In the examples given up to now of loops involving indexing in an array,

the choice of a method to perform the indexing arithmetic and the selection

of initial and final index values was left open; no foml t&mique was

described. Since arrays and array processing techniques are heavily used,

we will examine some general methods for handling arrays.

One-dimensional arrays are relatively simple, since each successive

element may be obtafned by sddlng the eleprent length to the address of the .preceding element. If for example the halWord integers ko, &, --- ho are

stored starting at K, then s is found at KtZn; if the array elements were

fullwords or doublewords, the corresponding addresses would be K&n arid Kt8n

respectively. On the other hand, if k4 *.. ka are stored beginning at.K, and

the length of a single array element is L, then,kn Is found at K+L(n-4).

The required subscript arithmetic should b&evident *- if the lowest-subscripted

element km $6 stored at K, then the location of kn (where n > m) is K+L*(n-m). .(It is also evident that n n&d not be greater than m; it i's merely customary

to store arrays this way.) An example will help to illustrate this.-

Suppose an array of fullword integers xg . . . x17 is stored beginning at

X, and we are required to store their sum at T. The lower and upper subscriptbound6 of 5 and 17 are stored at LOWER and UPPER.

.

SR 010t 1 ,lOtJER

A 's LR 291S 2,LOWERSAC 2.2A 0*X12)LA l,l(O,l)

. . c l,UPPER8C 1 2 , AST 0,T

INiTIALlLE SW4I N I T I A L I Z E S U B S C R I P T N, 1OWER WUND = 5INOEX C A L C U L A T E D I N R 2(N-MI440~M)S U M = SUM + X(N)IhCREMENT N f3.Y LGMWAKE fv T O U P P E R BOUNC1F N O T C;HEATER* B R A N C H

LGklER ic’--

F’5’UPPER CC t-17’T cs FK oc 13F’1’

LO&&R S U B S C R I P T 6OlJNDUPPEH SUBSCR 1PT B O U N D

FQt4 EXAMPi&

Now, suppose that the lower and upper subscript bounds of the elements

fotiing the required sum do not wve known values,. but we still know that xs

1 8 - u

is stored at X. We can include a, portion of the indexing arithmetic in the

program at assembly time so that it need not be performed at execution time,

namely the factor L*(-m).

SR OtOL A 4 9 4L 2 ,lONERSLL i?dL SpUPPERSLL 5,21 oax-20(288XLE i?v’bAODST 09T

It can be seen if C(L@ER) = 5 and C(UPPER) = 17 that the same result willbe obtained; the first element to be added will be at X-20+(4*3) = X, as

desired. The Assembler will of course require that the expression X-20 be

addressable; this requirement is sometimes a limitation on the use of this

time-saving technique.

Two- and higher-dimensional arrays present a few further complications, .

which can be handled fairly easily; we will examine two methods for addressing-array elements. First, it is necessary to find some way to reorganize the

rectangular form of an array into a linear arrangement which conforms to the

machine's natural method of addressing successive bytes in memory. A common

method is to store successive columns of the array one after another, as

indicated below.

E/ -+ 813. ‘821.' a12 ,a22 813 823.

Figure 18.2 Storing an Array in Column Order

It is apparent that any desired arrangement is actually possible, and that

a choice-between possibilities must be based on considerations such as

convenience and the time and space required to retrieve a particular element.

For the example above, the arithmetic necessary to retrieve the element ais

is as follows, assuming that $11 is stored at A: to obtain the address of

18-13

the first element in a given column, we need the address A+L*(j-1)*2 where

L is the element length in bytes, and the factor of 2 accounts for the

presence of 2 elements in each column. Once having obtained that address

the i-th element in the indicated Column is found by adding L*(i-1) to the

partially computed address, giving A+L*(2"(5-l)+(i-1)). The quantity added '

to A is sometimes called a subscripting function or a mapping function, and

gives the correspondence between the array subscripts i and j of a particular

element and the "linear subscript" which gives the difference between the

locations of aj-j

and alpe It can be seen that if a column-ordered array

has r rows, the subscripting function is L*(r*(j-1)+&l)). For example,

suppose we have an array of fullwords of 2 rows and 7 columns stored at A,

and wish to store aij at X, where i and j are fullwords stored at I and J

respectively.

1 &Jf3CTR 6 . 0MH 6,=H’5’A 681BCTR 6 , 0SLC 6,21 3.Al61ST 3.X-we

I UC F’3’J GC F’6’A OS 35F

isir CULUMN I N D E X JFuKM J - 1MUsrlPLY B Y f+UMBER O F R O W SAUL) dL)LJ I N D E X iI)Z(;KtASii B Y 1MULTIPLY BY E L E M E N T L E N G T H , 4GiJ A(I,J)SJOKk AT x

PuSSIuLt V A C U E FCR 1WbSlt)Lt V A L U E FOR 3SL1MkkbuDY ELSE C O M P U T E S T H E V A L U E S

As was the case for one-dimensional arrays, part of the subscripting arithmetic

can be absorbed into the address of the 5nstruction which references the

array element. Thus, the address of ai3

becomes A-L*(r+l)+L*(r*j+i), and

only the final term need be computed at execution time; the code sequence

above can be rewritten as follows.

1 693 CuLUMiv iNOEXMH 6,=H’5’ *( ~\rUMBttt O F RGWS 11 691 + KClw lNOEXSLl 692 0kLi*(iiLEMEhT LENGTH)1 c&u) = A(X,J)

S T S T O K E A T X

Figure 18.3 Example of Array Subscripting Arithmetic

18-14

The address A-L*(r+l) can be seen to be the address of the element "aoo"

(which may not actually exist) and is sa?etimes called the address of the

"base element" of the array or (unfortunately) the "base address" of the

array. Since this almost always has nothing to do with a base address to

be used by the Assembler in computing displacements, it is best to avoid the

latter terminology.

In the examples above we have assumed that the subscripts could take

positive values only, and always had a lower bound of 1; this is not a

necessary condition, and if the lower subscript bounds on i and j are io and jo

respectively, the subscripting function becomes L*(r*(j-jo)+(i-io)). In such

cases it is usually more difficult to include the factor -L*(r-jo+io) in an

expresston at assembly time, &nce the result may not be addressable. We

will adopt the convention that all subscripts run upwards beginning at 1

unless the contrary is stated.

A second method of array addressing is usef'Q when processing speeds

are important, and occasionaU.y also finds application to arrays of irregularly-

spaced or irregular-length data. This involves pre-computing the addresses

of portions of the array, and storing those addresses in a separate table,

For example, suppose the addresses of the elements aAl, 812, and al3 in

Figure 18.2 are stored as fullwords at C!#LADDR, as indicated in Figure 18.4.The notation A(x) means 'kddress of x?

Location Contents- -

C@ADDR Abd

C/6LADDR i- 4 A( ale>

C@LADDR -t= 8 A( aid

Ia11 a21 a12 a22 a13 a23

Figure 18.4 Addressing with Tables of Addresses

The code to store aij

at X might then be as follows.

1 703BCTR 7,OSLC 7,2L 6,COLADDR(7~L 5,x0CTR 5 . 0SlL 5 . 2L 3,0(5&lST 3rX

18 - 1.3

The main advantage of this scheme is that it avoids the previously required

multiplication by the number of rows. The additional expense is In the space

required for the table, and the time required for forming it (either during

assembly or at execution time). As a final example, suppose *we want to

store at X the element aij

of a y-by-> array of fullwords stored in column

order at A; first we will compute a table of column addresses and store them

at ADDEITAB. We actually compute not the true addresses of the first element

in each column, but that address minus 4, because this then allows us to use

the subscript i directly without subtracting 1 during the accessing of the

desired array element. The table contents are shown in Figure 18.3 below,where the zero subscript indicates the subtraction of one element length

from the address of the beginning of the column.

LH 6,NROWS CiK68 = &UMBER G F R O W SSLL 6,2 M U L T I P L Y FOR I N D E X I N G B Y E L E M E N T L E N G T HLH 5rNCOLS huiYt)&ii dF COLUMILS IN RS FCiR LOOP C’QUNTLA 9,ADDRTAB tik%INNihG AOORESS OF T A B L ELA O,A-4

STACR ST 0,0(0,9)AR 096

- LA 9.440.9)8CT 5,STADR--II

I\icaLs lx H’5’NR13kS CC H’S’AGCRTd8 OC ,5f;

Location

ADDRTAB+4-43+l2+16

AR&AY AODRESS - t ELEMENT LENGTH)STtiRE A N AODRESS I N T A B L EWC&EASE A D D R E S S TD IjEXT C0LUMNIhCKEASE T A B L E A D D R E S S T O N E X T W O R DCWY duUTIL A L L AOORESSES C O M P U T E D

Contents Element Addressed

A(A-4) r a01A(A+-tZO) a02A(A-&kO) - a03A(A-k-1-60) a04A(A-4&O) a05

Figure 18.5 Example of Addressing Table Contents

To use this table to perform the desired calculation, we can write the

folIowing code sequence.

18-16

m! . (.

1 2tI Lm- KOhl ir\lOEX1 3tJ GET C O L U M N lNDEXSLDL 2t2 PUTWLY 80TH BY 4L 4,A00RTA8-4(3j G E T cclu?m AGORESSL 0,0(2,4) bi3 AII,J)ST 0,x .STUiKk A T X

This segment of code gives much faster access to the desired element; the

subscripting arithmetic (all but the last two instructions) on a System/360

Model 50 requires 18 microseconds, while the same arithmetic as performed inFigure 18.3 requires 33 microseconds. L-t should be noted that the faster

ex&ple uses the SLDL instruction to take advantage of the fact that the array

elements and the entries in the address table (sometimes oalled an 'access

table") are of the same ILength, which might-not be true in general.

In closing this discussion, we will mention that the address tabJ.e can

be constructed by the Assembler if the necessary quantities are known in

advance. The items in the middle CO~UM of 'Figure 18.5 can be used as

operands in DC statements ; remember that in the discussion of A-type constants ..(address constants) zin Section 13, 'it was stated that the abnstant may be

relocatable. Though we are not yet ina positipn to be abficct to discuss how

the correct addresses are eventually placed in the program; We will simply

write.a sequence of statements Which generates the same address table at. /

assembly time.

MChS EQU 5 &&ER Gf nwst EQU 4 LE:NGTH Cf ilF?RAY E L E M E N TPCCRTPE! D C AIA-Lb ,AWiRST CCLUKN - 4 . 1

GC AIA+L*(hRQkSd-Ld AWiCOkD CCUW - 41GC A{A+L*(NWks@Zl-1) A ? 3HXRD CCL&W - 41C C A(A+tWURUkS*dbL) AWWCITH CGLUNN rc 4)

- cc A(A+l*IlVRGkS*43-Ld AifiIFTH COLUKN - 41

The expressions in the address constants are written in such a way that

the programmer need only specify the value to be given to XR$WS in the first

E&U statement, and the required addresses are calculated by the Assembler.

18-17

19. SI INSTRUCTIONS

Most of the instructions discussed up to now have referred to data

w.hich was either in a register or was to be found in memory at a given

location. One exception we have encountered is the LA instructions, in which

th,e operand to be placed in F&l was constructed using part of the instruction

itself. In particular, writing statements such as lx 53 provides

Q way to place data into a register without an additional memory reference,

which *would be required if we wrote L ~,=F'E' instead. Instructions

which contain one of the operands of the operation to be performed in the

instruction itself are called immediat;e instructions, in the sense that an

operand is immediately available. Thus, we could call LA a “Load

I&mediate” Instruction in those situations where the base and index register

specification digits are z,ero, since the immediate operand comes from the .

displacement field of the instruction.

The six Instructions to be dikussed here make use,of an immediate

operand contained in the second byte of the instruction, as denoted by “I$’

in Figu;*e 19 .l.

Figure lg.1 SI Inqtruction Format

In writing SI instruction statements, the first operand will usually be a

relocatable expression; the second operand must be a positive absolute

eqression of value less than 256, so that it will fit into a single byte.The instructions are given in Figure 19.2; the notation “Cl’ is meant to

indicate the single character or byte at the effective memory address computed

. frcxn the addressing syllable.

19-l

I Instruction

Move

AND

OR

XOR

Ccmpare

Test Under Mask

Mnemonic I Action

MVI

NI

prI

XI

CL1

TM

C(Cl> +I2

Wl) +-C(Cl)h 12

C(Cl> +c(c2)v 12

C(Cl> +cb.> a3 12

c(Cl> : 12

Test Selected Bits of C(Cl)

Figure 19.2 SI Instructions

CC Set?

no

Yes

Yes

Yes

Yes

Yes

The operation of the first four of these instructions is straightforward,

and is illustrated below.

(1) MVI x,0 sets the byte at X to zero(2) Mu-(3) MvI

X,255 sets the byte at X %o all 1 bitsX,C’X’ puts an EBCDIC "X" at X

(4) NI X,0 equivalent to (1)) except CC = 0equivalent to (2), except CC = 1sets bit 6 at X to 1sets bit 6 at X to 0inverts bit 6 at X

It is occasionally clearer to use other than decimal self-defining terms;

example (7) could be written NI X,B'11111101' with the bit to be

zeroed immediately indicated. The CC settings after NJ, #I, and XI are

given in Figure 17.2.

The CL1 instruction performs a logical comparison between two 8-bitquantities, which are treated as unsigned integers for the comparison arith-

metic.' The result of the comparison is indicated by the CC setting, as given

in Figure 16.3. Thus, the statements below would result in the indicated

CC settings.

CL1 =C’A’,X’Cl’ cc=0CC1 =X’OO’ ,O cc=0CL1 XC’ “,5’1000000’ cc=0CL1 =X’l’,X’2 CC=1CL1 =C’A’,250 CC=1Cl1 = c ‘XYL’ ,c ’ X’-1 c c = 2CL1 =X’l’,X’O’ c c = 2

It is important to remember that the first operand in the caparison canes

from memory. We can rewrite the sample program fron? Section 18 which blanks

19-2

out the special characters in the string at STR by making use of the CL1

and MVI instructions; the latter simply stores the second byte of the

instruction at the first operand address.

LA 1980 )INITIALIZE LOOP C O U N TNUT LA 2rSTR-41) CUNS’IRUCt* CHARACVR A D D R E S S W:ITH I N D E X I N G

CL1 0(2I,C@A’ CUMPARE A D D R E S S E D C H A R A C T E R TU LEk,TER @A@5c 1OvANUM B R A N C H fF NUT 1ESS T H A N OA”WI O(21,C’ ” B L A N K O U T IF IWk-ALPHANUMERIC

AAW 8 C T 1 rNEXT COUNT OOhfJhl AAD LOOP

Because SI instructions cannot be indexed, the LA instruction named NEXT

must be used to construct the desired memory address for the character to

, be tested. The CL1 instruction campares the eight bits in memory to the

immediate operand CIA', and if the byte in memory contains a bit pattern .

whose value is greater than or equal to 193&o, the following BC will branch

around the MVI instruction. If the branching condition is not met, the MVI

stores the bit pattern corresponding to the EBCDIC representation of a blank

into the character string. It can be seenthat the use of these two SI

instructions allows considerably simpler coding.than in the previous examples

of the same processing. e

- The TM instruction is one of the most useful in the System/360 instruction

set for applications where individual bits must be examined. Because nomeans is provided for addressing individual bits, data in bit form must be

treated differently. The immediate operand of the TM instruction is used

as a mask to indicate which bits of the addressed byte are to be examined;

wherever a 1 bit appears in the mask, the corresponding bit position of the

memory operand is examined, and 'wherever a 0 bit appears in the mask, thecorresponding bit of the memory operand is ignored. The result of theexamirlation is indicated in the setting of the Condition Code, as shown in

Figure 19.3.

ICC I Indication -10 Bits examined are all zeros or mask is zero

1 Bits examined are mixed zero and one

3 Bits examined are all ones--

Figure lg.3 CC Settings after m Instruction

19-3

One special case of the TM instruction can arise if the mask specified by

12 is zero (indicating that no bits are to be examined); the CC ie simply

set to zero. To illustrate the use of the TM instruction, consider the

following examples,

1)

2)

3)

4)

Branch to MINUS if the fullword integer stored at NUM is negative.

(This technique can be used to avoid having to load a register.)

TM NUM,X’80’ r&ST LkfTMOST 5iT8 C 1,MXNUS i3RANCH 1F A 1 611

Branch to EWEN if the fullword integer stored at HUM is even.

TM NUM+3r 1 T E S T HI(;HTMOST 81T O F FULLWURDBC 8,EVEhl 6KAlvCH IF ZERC

Branch to MIXED if the bits in the byte at B are not all .zero or all one.

TM Is.255 TksT ALA NTSBC 4,MXXED d&ANCH 1F MIXED 0 AhD 1

Branch to SMALL if the value of the klalf'word i.rlteger at HNUM is between

-512 and 311.

TM HhUM,X’FE’ Its1 LiiFTEx.JS? 7 8fTS5c 9, SMALL ;dKANCH 1E A L L 0 CR L

When used in conjunction with the NI, $1, and XI instructions, TM-provides a simple means of settin @ and testing yes-no indicators in a program.

For example, suppose we wish to add the three fullword integers stored

beginning at Q, and afterwards branch to N$kXR il' no overflows occurred and

to ERRfiR if one or more overflows occurred.

MVI FLAGtOL OtQA o,u+e5 c 14,NEXTAOX FUG, 1

kEXTA A O,Q+8ec LtERRORTM F L A G , 15 c 8,CYOERR5c 1 rERRORe-w

StT irLUiCATU8 I - C R N O O V E R F L O W SdiT FlhUl I N T E G E RA D D SECUhD I&TEGERtJKANCH AF N O C V E R F L O WSET UVEKf-LOh F L A G @ON ( T O 11ADL) THIKD I N T E G E Rt3hACuCH A6 OVERFlCk T O E R R O RL)THkKMJlsfi EXMINE O V E R F L O W FlAG BITIF 4lT W A S LERC, I\iO O V E R F L O W SI F ON&z, OVERC-l.GW C C C U R R E D

FLPG CS X OVtiUUhd F L A G B Y T Ec GS 3F 3ruh(iEKS JO EE ACGEO

The @I instruction OR8 a 1 bit into the rightmost bit position of the byte

named FUG, thus setting it to 8 3, Note that only the rightmost 'bit of the

byte is being used; the other bits might be used to indicate other conditions .

detected elsewhere in the same program.

As another representative example of the use of these instructions,

suppose we are required to process a list of n haZtiord integers stored at

LIST, where the positive nonzero fullword integer n is stored at N. Suppose

that the processing requires that the elements of the list be added together,

except that alternate elements of the list are to be added twice; the right-

most bit of the byte named SWJITCH is set to 1 if the first element is to be

added twice.

LA 4,LXST1 39NSR 64

CCAG 1H 5t0(0,4)AR 6VS

TM SkffCH,Z6C 8,QNCEAR 6V5

GI\CE LA 4,2dOv4)X1( ShITCH,,P

8CT 3,LClAD

I N I T I A L LIST A D D R E S S IN R 4NUidbEK-OF ELEKEixTS I N R 3INITIAAJLE S U M T C ZEROG E T A HALFWORD ImIST ELEMENT IN R5A D D TO S U M OKCETEST SWXTCM MTt)RAhCH 1F 09 A D O G N L Y OKCEADO Li SECGND TIMEfNCREMENT IJST ADORESS @Y 2fNVEKT WXTCH BITi%IANCi-i PO G E T N E X T E L E M E N T IF N O T DilNE

Since the XOR of a 1 bit and any other bit inverts the value of the latter,

the XT instruction alternately sets the switch bit to 0 and 1. The TM

instruction examines only the rightmost bit. of SWITCH; the branching condition

will be met if that bit is zero.

A technique which occasionally finds use in such an application involves

changing the mask field of a branch %r&,ruction so that italternately

contains B'llll' and B'OOCO', causing an unconditional branch to alternate

with a-no-operation. The above code sequence can be rewritten to use such .

a technique as shown below.

:

1 lthLA 0~2

I,GET NUiWER OF ELEMENTS TO 8E AbQDEDS&T U P I N C R E M E N T O F 2 fh/ RO._

AR Iv1SR 14SR 212LR 3r2Of BRNCH+l#fOTM SkXTGH.1BC 8vADDNI 0RNCH+lvX'OF~

ACC AH 3,CIST(2)IWNCH BC 0,FlIP

AH 3,LISTUIFClP XI BRNCW1,X'FO'

BXLE 2vCdWIST 3rRESUlT

244 '2*i[N-Ii IN Rl = COMPARAIKI FOR $XLE COOPIr\llllALIZE INDEX IN R2 T O Z E R OS A M E FOR S U M I N R 3S E T SWITCH F O R SINGCE AC0 QN F I R S T P A S SCHECK SNITCH TCI SEE IF S E T U P .IS C O R R E C TJ U M P I F B R A N C H H A S B E E N S E T CORRECTLYOTHERUSE S E T U P TO A D D T W I C E Q N 1ST P A S SA D D A TERMMASK FfELfl H E R E I S A L T E R N A T E D iEDY XfADD AGAIN IF N E C E S S A R YfNVkRT. B R A N C H NClSK 6ITSWUNT AiUO LCGPSTWE AIVSWER bPPRUPRIAfELY

There. are several features of this example to be noted. First, the mask

field of the second BC instruction must be addressed at BRNCH+l rather than

at EDWCH, because the latter is the name of the byte containing the operation

code. Second, the instructions preceding the loop which initialize the mask

field might be necessary because this segment of code may be part of a larger

program which executes it many times, and we have no assurance that the mask

field will be preset correctly. Third, the instructions which manipulate the-mask bits are written in such a way as to leave untouched the index register

specification digit in the second byte of the instruction at BRNCH. This is

necersary because we do not want to insert extraneous bits (thereby causing

indexing to be performed), and because in general there can be information

there which must be unmodified.

The above technique of actually modifying an instruction in memory can

occaeionally yield higher processing speeds, but it is not generally considered

a good programming practice for the following reasons:

(a-) the coding tends to be more. difficult to understand, since a

reader cannot tell with any degree of certainty what is to be done

by a given instruction if it is subject to modification by other

part8 of the program;

(b) checking out the program is more difficult, since it in usually

easier to keep track of data (such as at WITCH in the previousr

example) than parts of instructions;

19-6

(c) if it is necessary to 'rewrite a portion of the program it may be

difficult to find all the instructions which modify others;

(d) if the program must 'he re-enterable (a property of codkg which is

involved in multiprogramming ap~YZcatio~>s and interruption processing,

which Wll be treated later) such a technique is forbidden.

This might appear to contradict the earlier statements that the flexib$lity

of a computer is derived from its ability to modify the instruction sequences

it executes; by this we simply meant that Lhe program can control its paths

of execution, rather than that it modifies the actual instructions as was

done here. A degree of instruction modification is provided by the Ekecute

instruction, to be discussed later.

To show that the above example need no-t rely on program modification,

we give two further code segments which perform the same calculation more

rapidly; the first uses two separate add seguenccs.

L 14BCJR 1,oSLl 191LA Or2SR 3 9 3LR 293 ’TM SkITCH,lBC 19JWltCEA H &!.IST(i!)BXH 2.0,NEXTA h 3viaIsTt2)A H 3tCISTt238XLE ZrO,ONCE--a

The second aclds all the terms in orle loop and the alternntu ones in another.

L IdBCTR 1~0AR_ 181LA 082SR 393SR 2,2

A&Cl AH 3,dISJG?lBXLE 2,09ADOlLH 290AR 090TM ShiJCHglf3c 89ADD294 2r2

ACC2 A ti SdXSJi2)BXLE 2,01AOD2

!l?hie last exatnple is slightly slower than the pc~$gtX~ one, becau& mW8 ,

branching instructions are executed; in particular, it will not work

correctly if n = 1.

The above examples have illustrated the use of logical instructions

mainly for control purposes. Another important application is the manipulation

of data in bit form -- that is, data which assume only two values. For

example, suppose that part of the record of a person carrying automobile

insurance requires the following yes-no information: (1) age less than 251

(2) male? (3) d ir ver training course completed? (4) married? (5) anyprevious claims? (6) assigned risk?: Let the 'yesV answers be represented

by 1 bits in the first six bit positions of the byte named STATUS. The

following tasks may be performed by the indicated instruction‘s.

1) The policy holder has passed his 23th birthday.

NI STATUS,B'Ol111111'

2) The policy holder has married.

TM STATUS,B'00010000'Bc 1,BIGAMY

- flI STATUS,B'00010000'

3) The policy holder has submitted a claim; if it is the first, branch

to TSK, otherwise branch to TSKTSK.

1M SJAJUS,B’lOOOBC 1,TSKJSK0C 15,JSK

4) If the policy holder is single, male, less than 23, an& has not ccxqileted

a driver training course, brhnch to HIGHCJdST.

J M STAJUS,jV30’ Tfi$J MAi-WIEO AN0 JRAINIhGBC 7,NEXTJM SJATUSvX’CO’ T E S T AGE A N D S E X8C 1,HIGHCOST IF- YOUNG M A C E , B R A N C H

hE)rJ - - -

3) If the policy holder is an assigned risk, indicate that he has previ~::

claims if he also has no driver training.

? M SJAJUS,X’4’0C 8,NEXT3 ,‘? STATUS,X*20” ’I. I-CL l,NEXJc: STATUS,X’B’

r’\L)rl -. - -1

19-8

6) If the policy holder is married or has completed driver training,

branch to L#RISK.

TM SJATUS,MARRIED+TKAININGBC 5,LORISK

)4ARRIEC EQU 16TRAfItIhG E Q U 32

As a final example of the use of SI instructions, suppose there is a

fullword integer stored at I!? which we wish to convert to a character string

of decimal digitswhich can be printed, with the sign of the number preceding

the first significant digit; if the number is zero, the characters ?-OH

should be placed at the right-hand end of the character string. 'Since a

fullword integer can be at most 10 decimal digits long, we will reserve 11

bytes for the result at NBR. The conversion is performed according to the

scheme given in Section 2.

L A 2 . 1 0ElAhK tA 3,NER-l(2)

MVI 0~31,C’ @BCT 2rBCANK

- L 1rN ,LPR 1.1LA 3,NBR+lO

ChrVTLP SR 0.00 Oe=F’lO*STC 0*0(0,3)01 043J,C’O’BCTR 3 , 0LTR 1 . 1EC 2 , C N V T L PWI O(3) ,C’+’TM N,X’80’BC 8rAlLDONEMVI

ALLCOrk - - -O(3)&‘-‘-

NBR OS-

-

Cl11k GS F

S E T U P TU ULAtW G U T R E S U L T A R E ACONSTRUCT BYTE ADDRESSSTOKE BLANKS IN FIRST 10 B Y T E SB R A N C H l3ACK 9 T I M E SGET NUMtiER TC B E C O N V E R T E DTAKt IT3 MAGhITUDES E T UP A D D R E S S O F R I G H T M O S T &DIGITCLEAR H I G H - O R D E R R E G I S T E RW’JERATE A OPGXT B Y DXVIS,IONSTUKE THk REPAINDER BYTEGIVt 01(31J CGRRECJ EBCDIC REPRESENTATEQNMOVt CHAkACJER P O I N T E R X B Y T E T O T H E LEFTStE IF DOr\tE, WQTIENT G O E S TO ZEROIf lLUJ LERCI, GENERATE MGRE DIGITSASSUiUlti S I G N X S +t S T O R E TWAT C H A R A C T E RCHE.CK ACTUAL S I G N O F A R G U M E N TBKANCH 1F I T k;AS I N D E E D P O S I T I V ECll’HtkhISE PLAllT A - SIGh IN T H E STRINGREST UF P R O G R A M

O U T P U T LHARACTER S T R I N GNUMtitK TO 0E C O N V E R T E D

19-9

20. SS Instructions

Ae the name implies, Storage-to-Storage instructions work with operands

which are entirely in memory; except for TRT end EDMK, the only reference to

or use of the general registers by SS instructions is for addressing purposes.

This allows considerable freedom in the arrangement of operands in memory,

parttcularly since the data to be manipulated by SS instructions may be of

*vepiable length + Our concern in this sectton will be with the first nine

instructions in Table VII, which are listed for convenience in Figure 20.1.

The remaining SS instructions, which are primarily used for handling data in

pecked decLma1 format, will be discussed later.

ury “’

Mnemonic Instruction Mnemonic Jnstructkonr

Mvc Move I fiC OR

Move Numerics NC ANDMove Zones XC Excjius ive OR

TR Tranelate’ CLC Compare

TRT Translate and Test

Figure 20.1 Some Storage-to-Storage Instructions

All of the above instzxctione have the format illustrated in Figure 20.2 below,

;hbperationCode Specification bl

Byte

l-5 16 1920

dl bz d2

32 32 35 36 47

FS- 2062 Format of &ne Storage-toGtorage In&txctions

20-l

. 1

&folre discuseing the iastructiohs themseLves, we must examine some of

the detaila involved in specifying the number to be placed. by the Attae@Xer

in the liength ~pMif’ic&tipn Byte, the second byte of the instructicw As can

be aecn from Figure 20.2, five operand-field quantities in all must be provide&the baee and displacement of the address of the first and $ecohd oper&nds,

and e numb@ which specifies the length in bees of the date to be manLpulated.To ilkslrste one way of giving this information, ;auppo& we wish $c$ MOVE 23

bytes fran the area of memory beginning at A to the area be&nnldg at $; we

could write MVt! B(23),A ta perform the task. hots tbt onl.y t w ooperands are specified in the c@erdnd field entry of these Instructions, and

that the number hn parentheses, is not an Index reqgietror s$eclfication but

the number of bytes to be moved; it 2s explectad that ‘the Aseemblar IvI,~S, computedisplacements and asWgn base6 for us, eince wa have Wed implied cqerandadd~ssee l Than are aevertd. ather Ways to spaclfy the length sp@ificnttonbyte; these are showri in Flwe 20.3. For an @cpSicit length sp~ci~icM%3n,the ~ttbe provided is used; for an i&plied Leu\g-th, the A@sembLer ~111 &t&mine

an appropriate value in a way to be described mhortly.

I Explicit Ikngth I

gu~ve 23 bytes fraPh A to B, an4 W$ kriow thtrt if R9 i$ USA@ aa 8 base , thediap$&cements computed for A $nd B Will be 1253.6 aad 4?Da, raepecti~ly.

Than to 8chieve the delgired result We could write any of the faU&ving four

instructions corresponding to the first columh of Figure 20.3:

!!!!y!l1 . . ’ ,i..I

, .‘.

’

WC EW3I.AWC X'4?Or (23.9) ,AMN 8(23),293WWC 11491it3,9),X*h!5br9,

20-e

where equivalent decimal and hexadecimal self-defining terms have been used

to specify the displacements dl and d2. ’

It is often the case, however, that one does not want to be requ::red to

specify an explicit length, particularly in cases where the length should be

apparent frcPn the operands involved. For example, suppose the symbol I.3 is

defined in a IX3 or X.X3 statement as in the program segment below,.

WC B,=l20C’ ’ SET FIELD AT B T$ BLMYKSLh"

B D S cu3

It is apparent that if more than 23 bytes were moved by the WC instruction

that the data or instructions following the byte at B+22 cquld be overwritten;

thus the length should be detemlined from the first, or receiving, operand

rather than the second. This, in fact, g what the ABsembler does : if no

explicit length is given, the length attribute of the symbol or expression

in the first operand is used as the length specification. In the example

above it is evident that the length attribute of the symbol B is 23, so that

the correct result is obtained. If the first operand is an expression rather

-than a single term, the length attribute is detemined from the following

rule :

1. . The length attpibute of an expression is the length attributeof the leftmost term.

Thus, if’ we wrote MVC B&+x’>‘-l,=~oc’ ’ the length specified would

be 23, whereas if we wrote MvC X'5'+B-5712OC' ' the length specified

would be 1, because

2. The length attribute of a aelk-defining term is always 1.

In this example, a kulowJ_edge of the baBe and displacement to be assigned

when addressing the symbol B (namely 9 and 47D16) does not give the correct

Length when an itiplied length is given: MVC X’47D’( ,9),A specifies

a length of 1 rather than 23, because X’47D’ is a self-defining term, and

3 l - If an explicit base and displacement are given, the lengthspecification is the length attribute of the expressionWritten for the displacement.

These rules are summarized in Figure 20.4.

20-3

v *

Form ofFirst Operand

AddressI

ILength

Specification SpeciPication 3Rngth Use($

Sl Implied

4 L> ilnplied

dd ,bl) explicit

ddL,bd explicit

iIlQli~git

explicit

iJllplied

explicit

length &ttHbute of 81

length attribute of dg

Figure 20.4 Determination of Length Specification Byte

Because situations occasionally arise where it is useful to specify an implied

length with an explicit base and displacement, and the desired length is ylat

the bane as the length attribute of the displacement expression, an alterrJat;ive

technique is provided. We could have written

Mvc B-B+X'47D'(,g),A

in the example above, and the length attribute of the displacement expretialon

would then be computed to be equal to the length attribute of' B. Such-constructions are cumbersome, and it is preferable to use fi Symbol Length

Attribute Reference, which was mentioned in the discussion cf -l;e~?ne In

Section 11.

A Symbol Length Attribute Reference is written a8 an L f~-)llo~~d by ~nr;

apostrophe followed by a symbol, as in 2'13; it is an absolu4ee te.m wlt;h a

value equal to the length attribute of the symbol. Because s~&~>ln CRYI be

defined in several ways, the following additional rules are mcded:

1. The length attribute of a Location Counter Reference (*) is

the-length of the instruction in which it appears; thus f4wc B(L'++),Awill q$sign i length of six.

.

2. If‘~he~,symbol was defined in an EQU statement tsith * or ti self-

defining term*in the operand field, the length attribute assigned

will be 1.

34 The length attribute of a literal is not defined; thus constructihn~

such as MVC B(L'=C'RAY'),=C'RAY' are incorrect,

* Thus we can remSlt;e our Bimple example above, which ulses a explicit base

and displacement, as MVC X’47D’(LtB,9),A

Qo-4

Before discussing the various instructions in Figure 2&l,, one further1 .

detail must be noted. Because the length specification fits in a single byte,

it may assume one of the 256 possible values between 0 and 253: these

specify lengths between 1 and 2'36. This somewhat peculiar construction is

due to two factors: first, every SS iilStructiOn always operates on '3-t least

one byte; second, while all the instructions listed in Figure 20.1 prolzes$s

data from left to right (in order of increasing addresses), there are other

SS instructions which process data from right to left (in order of decreasing

addresses). In these latter cases, before performing any operations the

CPU must be able to construct the address of the rightmost byte of the operand

string (remember that all operands are addressed at the lowest-numbered

lodation), It is simplest to do this by adding the appropriate length

specification to the effective address of the operand in question, because

there are k+l bytes in a string beginning at location n and extending through

location na-k. Such considerations will normally be of little interest to

the programmer, since he will allow the Assembler to determine the necessary

quantities from the operands provided in the instruction statement. However,

it is sometimes necessary at execution time to compute the number of bytes

to be manipulated, so that the relationship between theactual contents of

the Length Specification byte and the number of bytes involved becomes

important. An illustration of this is given in example (4) later in this

section. Thus, in summary, the Length Specification Byte contains a number

which is one less thanthe number of bytes to be operated on, unless an

explicit length of zero is given, in which case a zero is assembled also.1The following instructions would therefore be assembled as indicated, assuming

the same displacements for the symbols A and B relative to C(R9) as previously.

MVC 8d23)rA WA6MVC BQA)*A LIZ00MVC B(O)oA 0 2 0 0MVC o(L'*),29uz) 0205MVC 15(L'6--4,3J#J3 wi.2WC 84 I)LAbWC H-1(L’H,H),i-I 0 2 0 0MVC HtH,H) aHdt Hb wo7MVC H+B-A( ~99 ,A 0 2 0 0MVC T,B-4 OLA6M V C B-A+4(9),A I1208M-B

e OST ECNJI- EQU

C L 2 360

9 4 7 0 9 1 2 5947I) 9 1 2 59470 9 1 2 50 0 0 0 COlO3OOF 9 4 7 09470 9 1 2 58008 0 0 0 8d008 8 0 0 89360 9 1 2 594?D 947903SC 9l.25

As indicated earlier, the MVC instruct?i.on moves the specified number of

bytes from an area whose lowest-addressed byte is at the effective second .

operand address to an area starting at the first operand address. There are

no restrictions on overlapping of the two areas, SO that various functions

such as propagating a character through an srca or &iJ?ti~~g t.he bytes i.1~ at1

area may be performed as in the folI..owing examples; we need only remember

that air SS instructions are executed in such a way that each byte 1s stored

before the next byte to be operated on is retrieved from memory.

(1) Set the U&byte axa beginning at LINR to blanks.

MVl .liNE,C’ ’ H’OKk t8CDfC E!lhiK A T L I N EMVC LINE+l~lZ9~pLI~E PHOP~Gll~~ THRQUGH REMAXNING AREd

This requires less storage space than

MVC LnJE( 1203 r=A2QCa ’

(because space i.s required for the literal) but slightly more execution

time.

- (2) Shift the 800byte character string beginning at STR to the left; by two

characters, leaving blanks in the vacated positions.

M V C STR(78LSTR+i!MVC STW7812) ,=C’ @ T W O B’LAhI<S l-0 E N D

(3) Exchange the contents of the halfword integers at A and B.

M V C TEMP,AMVC A.0M V C BsTEMP

TNP i s -

-

X L 2A DS He OS w

MiJVt A I33 T E M P O R A R Y LclCAtrONMLIVE; iit l-0 AMWE CjLL) C(A) FRO8 T E M Q TO 8

Note that no registers were changed in the above instruction sequerice*

(4) .R8 and Rp contain respectively the address and length of a message of

less than I20 characters. Move the message to the area named LINE.

BCTR 910 L)tGKEASt L E N G T H BY 11 F O R C P US T C 9,MVC+L STuKE A l LENGTH BYTE O F M V C I N S T R U C T I O N

WC MVC LINEtO) ,O( 81 ML)Vk 4XliiMECT N U M B E R Of CHARA’CfERS

The BCTR is used to reduce the character count from its 'ftrue" value

to the value required by the CPU in the execution of the MVC, namely

one less than the number of bytes to move.

The MVN and MVZ instructions work in exactly the same way as MVC, except

that only the rightmost 4 bits (the "l&merie'" postion of a character) and$

leftmost 4 bits (the "gone" portion of a character) arc moved, respectively,

While these two instructions are occasionally useful for other purposes,,

their main applications concern data in packed decimal format. To illustrate

some simple uses, consider the following two examples.,

. (5) Convert the positive half'word integer at N to a string of 5 EBCDICcharacters beginning at NDEC which give the decimal representation of C(N).

iH 1tN GEI- IWMA~ER TO 8 E C O N V E R T E DLA 295 CuuNT' NuM8ER Of DIGITS I N R2

x SR 0,o CLEAti HLW-CIRDEE FEGISTERD O,=F’lO’ G;ENk&ATfi A DIGITSK O,NDEC-112) STi.wi Q&IT I N O U T P U T S T R I N G8CT 29X COUNI- AND B R A N C H UNTIL D O N EMVZ NDECt 51 r=SX’FF’ A T T A C H Z O N E S FQR E8CDlC REPRESENTAfION

NCEC -dS--

C L 5-

-Note that we could have used the litera.is =?C'O' or =TC"g" in the MSTZ

instruction, with the same results.

(6) Convert the p-digit decimal number in EBCDIC form at NDEC to a fullword

binary integer and store it at M.i

M V N TEMPvNflEC ‘R~EIKIEVE N U M E R I C PClRTXObiS CW D I G I T SL A 3,TEMP AL)d)KESS 4nlF C U R R E N T DlClT I N R 3L A 295 NUMkhkK OF D I G I T SSR 0.0 CLEAR R O F O R DIGiTS1R 14 AphJ R1 F U R rJUM8ER BEING G E N E R A T E D

WLf NH - l,=H'lO' M U L T I P L Y A C C U M U L A T E D P A R T BY 101c 0,0~093) INStRT 0lGIT FRCEi INPUTt N O Z O N E SA R 190 AL)0 TO P A R T I A L S U NLA 3#1(013) INCKEMENT DXGlT A G D R E S S8CT 2,MULT COuNI- A N D LOOPST 1rM STOhE R E S U L T

TEMP i i --

XL5.0’ Iu~vkEs PRkSET JCI ZERO1 D I G I T S M O V E D I N

20-7

We note with reference to these two examples that there are instructions

available in System/360 which considerably simplify the conversion of

' numbers between binary and decimal forms; they will be treated later.

The logical instructions NC, fiC, and XC perform the logical operaMans

described in Figure 17.1 upon two strings of bytes, leaving the result in

the first operand string, and set the CC as in Figure 17.2. Consider the

following examples.

(7) Clear the l20-byte area at LINE to zero.

xc Ll3?E(l2O),LINE

Note that we could also have used the same technique as in example (1)

above; the use of XC is usually slightly slower due to the necessity

, for actually perfoming the XOR operation, but requires less sr,ace in

the program.

(8) Branch to YES if the fullword integer at LUMP is zero.

k Lw4),= or NC L&P( 4),LuMl?BC by= Bc 8,JQ=

In each case the first and second operands are identical so the only

result of the logical operation is to set the CC; no data is changed.

This technique is useful when a register is not free so that performing

the sequence L followed by LTR would be awcskward, or when the data is

not aligned; it will usua:ly be slower, however.

(9) Suppose there are two fullwords X and 2 in memory which contain Pour

pbsitive integers each, packed as illustrated in Figure 14.7. Replacethe second of the integers in the word at X by the corresponding value

from the word at 2.

MVC. TEMIQ~ MUvt IVEUJ V A L U E TQ TEI’4PQRARY L O C A T I O NNG JEMP,MASK E~itilr\tATE ALL 8UT S E C O N D INTEGfiRo c X,MASK SET ALL 8ITS T O 1 tN 20 XNJEGER #OSXYUJNxc K,MASK ~uw SET T H E M JO ZEROoc X,fEMP ii\lhttiT ruEW V A L U E IhIT WORD Af X- - -

TEMP DS X L 4MA5K DC XJ,.4’007800~0’ MASK t)lTS FOR S E C O N D INTEGER POSlTfON

20-8

The CLC instruction compares two strings of bytes, one byte at a time,I

until either an inequality is discovered or the required number of bytes

has been ccPnpared. As was the case for the CL1 instruction, the comparison

is made between unsigned positive logical quantities.

(10) Two positive fullword integers are stored at S and T. Branch to TBJG

if C(T) is algebraically larger than C(S).

CLC w+),SBC 2,TBIG

(11) Two negative fullword integers are stored at S and T. Branch to TNB

if C(T) is algebraically less than or equal to C(S);.

CLC w+),sBC l2,TNB

(12) A list of 100 names and occupations, each contained in a block of 60

bytes, is stored beginning at LIST. If any of the blocks matches the

name and occupation at WH@, branch to F&Jl!JD.

L A 1tCfST LlL~TiALlZE T O A D D R E S S Of F I R S T B L O C KL A 2 , 1 0 0 S E T CLAUNT T O IuJMBER O F B L O C K S

T E S T C L C 0~60,1I,~HG COiJlYAKE B L O C K S8C 8,fOUNG SKANCH iF B L O C K S A R E E Q U A LLA 1,bO~O.l~ OTHkKWISE I N C R E M E N T A D D R E S S BY 688Cf 2,TEST CclurVT DOWN FRClM 100 A N D 8RANCH8C 15,NOTFOUNU Ml NATCH~ING BLOCK W A S FGUND

The remaining two instructions to be examined are TR and TRT. These

are flexible instructions which can greatly simplify many complex programming

tasks; they appear complicated when first encountered, but in reality are

quite straightforward in their operation. We will examine TR first.

Like MVC, the TR instruction moves bytes from the second operand location

to the ffrst operand location, but in a less direct way. The operation actually

performs a sort of pseudo-indexing, as follows:

( 1a an "argument" byte is obtained from the first operand location;

(b) the value of that byte (as an 8-bit logical integer) is used as an

index to access a "function" byte from the second operand location:

the address of the accessed byte is the effective second operand

address plus the value of the argument byte from the first operand;

“:.:

(c) the accessed fu.nctLon byte rep!,aces the argument byte frcm the

first operand string;

(a> this process continues until the,number of bytes indicated by the

length specification byte has been translated.

For example, suppose the string of 5 argument bytea at P contains ~'020104wO3',

and the character string at G contains C'ABCDEF'. Then if we execute the

instruction TR P(51,G the final contents of the 2 bytes at P will be

C'CBEFD'. This is easily seen to be the correct result, as follows: the

first argument byte taken from the first operand location is 02%~; the

function byte at G+X'02' is C'C!', and this replaces the first byte at P.Similarly, the fifth and last byte at P is 0316; the byte at G+X'O3' is C'D',

which is the final byte placed in the string at P. We can use RX instructionsto simulate the action of the TR instruction as follows, where it is assumed

that the symbols L, Bl, Dl, B2, and D2 have the same values as in the TR

instruction being simulated; for purposes of the example, assume that ,Bl and

B2 have values other than 1 or 2.

9r TR Dl(Cd31)dI2I(W Is THE INSTRUCTiON WING SIMULATEDLA 0,L SET COUrvTER Ih RQ’ T O N U M B E R OF BYTES

, SR lrl SkT FIRST OPERAlrtD XNDEX T O 0- SR 2.2 FW iNUEXlNG TA8LE A T 2NO O P E R A N D ADDRE$S

GETARC 1C 2,Ol(lr8I~ r;ET AUGUMENT BYfE, U S E A S X N O E XIC 2,02(23821 HWLACE 1’T BY FlJNCfION BYTE F R O M T A B L ESTC 2,Di~l,61~ STdttE ii\ S T R I N G A T FiRSI- O P E R A N D L O C A T I O NCA l,UOrl~ INCKEMENT F I R S T QPEqAND INOEX 6V 1Kf 0,GETARG LUUP u&TIC L A R G U M E N T BYTES A R E aPROCESSED

The full power of the 5% instruction can be appreciated if we consider

the first example from Section 18, where a character string was to be processedin such a way that all special characters whose EBCDIC representations are

numerically less than C'A' are sonverted to blanks. By setting up anappropriate table, the entirFi! process can be done by one instruction, as

follows. The method used to construct the 256-byte table is neither elegant

nor general; better ways will be illustrated later.TR STR~8Q)rTBL TKACVSLAT’E A L L S P E C I A L C H A R A C T E R S T O B L A N K--a

WL DC 193C' 'DC C’ABCDEFCWIoc 7C' ‘DC Co JKCNNOfWVDC CUP ’DC C’STUVkXY2’DC 6C’ ’DC C’O123456289@DC 6C' '

AWTHINC; 1ESS T H A N C ’ A ’ I S B L A N K E DLkiTTEHS A R E UkCHAfGED .b)LAhK THk NOkPRI hT ING C H A R A C T E R S B E T W E E NPUltnrT L E T T E R S A S I SkkANK WT NO/b-PRXfVT’XNG CHARACIERS

bLAl\rKS F O R AhMTHIhG.. B~ETkEEN! ti?E* A N D COO’UililTS PKlN.X A S ISTAIL-tNOkRS 4RE iEkANKEQ T O O

z?o-10

As a second example of the use of the TR instruction, suppose we wantI

eventually to print the contents of the fullword at W as 8 hexadecirlal digits,and are required to place the 8 EBCDIC characters representing the digits in

a string starting at HEX. (We will see later that the UNl?K instruction does

this more simply.)

L l&J t,i;Ei FULud.lRD T O BE C O N V E R T E DLA 2 , H E X AWKtSS Of C H A R A C T E R B E I N G S-fOlZED I N R 2LA 3,‘8 CWfuT 1N R 3

CLEAR SR 090 CLEAR KO F O R S H I F T I N GSLOL 014 S H I F T A H E X D1GI.T I(biTO R OSK 0~010,2~ STukE Xr\r STKItvG A l H E XL A 2,1(0,2) ~IKKEI’W’AT C H A R A C T E R A D D R E S S B Y 10CT 3 ,CLEAR WAILCH UEUTIL 8’DLGITS A R E S T O R E DTR HEX(8) r=C’01234567~9ABCDEF@ T R A N S L A T E T O E8COIC

We can also index in the opposite direction, as follows:

L o&J GtT FULLhORD TO B E CQNVERTEO1 LA 2,8 CilUE\rTkR A N D IN5EX I N R 2

Sh\If1 S R D C 094 SHifT A D I G I T WTO RlSRl lt28 YUbI TlUN F O R S T O R I N GSK ltHEX-112) STdKii I N C H A R A C T E R S T R I N GBCT 2tSHIFT WECKEASE dN5EX Ah5 S H I F T A G A I N

- TR HEX,TAB TKANSCATE OIGiTS T O EBCOIC REPRESENTdTIDN-Be

t;EX OS C L 8TAB DC G’012345670YAkUM= Q

The TRT instruction is identical to TR in the first two steps which

were labeled (a) and (b) above; it is quite different in that the accessed

byte from the table addressed by the second operand does not replace the

argument byte from the first operand string. The accessed function byte is

examined instead, and if it is zero, (1) it is placed in the rightmost

byte of R2, (2) the address of the argument byte (which caused a nonzero

function byte to be accessed) is placed in the, rightmost 24 bits of Rl; the

remaining bits of Rl and R2 are unchanged, and (3) the operation terminates.

The CC is set to indicate the conditions tabulated in Figure 20.5,

20-11

CC Setting Indication

0 All accessed function bytes were zero.

1 Nonzero function byte was accessed before the lsstargument byte was reached.

'7

2 The nonzero function byte accessed corresponds to 3x.last argument byte.

-- ----

Figure 20.5 Condition Code Settings for TRT Instruction

As an example suppose we are to scan a string of 80+haracters beginning

at CARD for punctuation in the form of periods, ccmmas, and apostrophes;

when one of them is found, a'branch should be made to P, C, or A respectxkely,

with the address of the character in Rl. If none are found, branch to W@UNCT.

First', we will write a program segment using CL1 instructions.

L A L&ART)L A 2,ao

TESTP CL1 O( 11 tc’.‘*BC 8,PCL1 04 11 tC’,’0C 8fCCLX O(l)tCQ"'BC &AL A ld(Ot1~8Cf 2,TESTP8C 15tNOPUNCT

~~u~TIALIZE CHARACTER AQGRESSI'vU)IVIS!~R iIF CHARACPERS TO EXAMII\(ECUWARk TO PERIODti~Al\rCti Xi= FQlAwCOWARE TO CCtWAt)RkNCH 1F FGUhOCOiWARE T O APCSTRiPXEdKA.MH IF FGClRiDulM3iWiSE fNCREMEl\iT C H A R A C T E R A D D R E S S @V 1COU;LT AND.~LOGPi-A&E THE BRAfJCh fF NONE FOUND

The TRT instruction allows us to do the same processing much more rapidly

but at a cost of more memory space.

SRTRT

- 8CBRCh BC

BCBCBC

Tel ocDCDCDC

2t2 UtAK z;(2 TO B E U S E D A S A N INDEXCARD{ 80). T8C SCAIL FUi( P U N C T U A T I O N8tfvClPUhCT - dAA&CH 1IF NOhE FGUND15tBRChi2) USE FUNCTION BYTE AS XNDEX FUR BRANCH15,P PE~l[UD15tC L&‘dMA15,A AWSTROPHEiK'. '~x'oo',x'o4'IC' ,'-C'.'-l~X'OO',X'O8'(C""-C','-I~X'00'tx'~c'Q255-C"")XaOO'

The three nonzero function bytes are located in the positions of the table

which correspond to the values of the EBCDIC representations of the characters

2042

being sought; the nonzero values are multiples of 4 so they can be used to

index the branch instruction at BRCH, which could also have been written

Bc 15,*(2) b If the conditional branch to lY$@UlKT had been omitted,

the program could have gone into an infinite loop at BRCH..

To give a final example of the use of several of these SS instructions

to process variable-length data, suppose we are given a string of charadters

at NAMES which contains some unknown number of names separated by commas

and terminated with a period. Our first task is to construct a table at

LIST of fullword addresses of the first character of each name; the first

byte of each address will contain the number of characters in the name (which

must therefore be less than 256 lettersI

in length), and when the table is

cotiplete the number of names encountered should be stored in the fullword at

NBRNMS. To protect against omitted punctuation or other errors, branch to,L@NGNAME if no punctuation is found within 256 characters of the start of

a name.

SR 393 Ai3 Le>lVTAiNS lNOE% F O R GISTU-3 213 CLEAK FUhCTIGN B Y T E SIJITXH IN R2 .L A L,NAMES I[MITIIALIZE S C A N A D D R E S S

SCAN LR 491 5AVE XMTIAL C H A R A C T E R A D D R E S S I N R 4TRT 0(256~1),WT~ SCAlV FOR PERXQD O R C O M M Af3C 8,LGNGhAME t)RARICH 1F SOKETWING F U N N Y H A P P E N E DS T 4tCfSft3) STuKE AWRESS O F hAME ihl GISTSR L94 CirMPUTE EUAM% LENG’fHS T C lrlISf(3) S T O K E LEJVGTH OF N A M E I N FIRST B Y T EL A 3,4(0,3) iNCR&MENT 11 S?’ A D D R E S SLA l*1(4,1) MciVE A D D R E S S TO S T A R T OF lVEXT N A M EBCT 2,SCAN E)tiAILCH Ii= A C O M M A kJAS EftCOUNVEREDSRI. 3.2 ‘if PEKluD, N O B R A N C H . C O M P U T E A N D S T O R EST 3,NBRNMS AIUM~E~ OF N A M E S FCUNDw-w

fRT8 - 0C JC’. ’ I X’00’rX’cu’ FUl\rCTIOh = L F O R P E R I O DDC tC’,*-C’.‘-l~x~00’,X~02~ ’ FWZTICIN = 2 F Q R C O M M ADC 1 2 5 5 - C ’ ,!WoOOa LERO OTHERhXSE

h4MfS ic-

I*

C’~RQ~NIGREEN,~L)~YKA,OFSTRA~VD,JQNES,SMEDLEY,D~E~APPLE’GC C’,DOE,SMITHWICKrSO~T~AR~~S~~T~~D~ElFULrJONES,~~RP~’

FLAG- OS CWRhNS OS fLIST ns 5OF

20-13

The only unusual feature of the above program segment fs in the use of the

function byte as a branching switch; if a period is encountered, the contents

of R2 wU. be 0000000116 and the BCT instruction will not branch.

Suppose now that the list of addresses is to be sorted so that the names

pointed to will be addressed in alphabetical order if the addresses are taken

in succession beginning at LlST. We will sort by making repeated passes over

the list, making pairwise comparisons among the names and exchanging addresses

when they are not in order, and te.rminat&ng when DO exchanges have been rncde

on one full pass aver the list.

1 0,NBRNMSBCTR 0,O

START LR I,0 :CA 2,lXSTMVI FLAG,0

GETAGR C 3,0(0,2)L 4,4(0,2)CLC 0(256,33,0(4>38C l2,NUEXCHST 3,4(0,2)ST- .4,0(0,2)M V I FLAG,1

NOEXCH C A 2,4(0,2) ..---.8CT 1,GETAORTM FLAG,18C 1, S-FART

b&T N U M B E R O F NdMESMIwS II T O GIVE N U M B E R Of CilMPARWlh&Ilui rrk~UE CGKPARISGN CCiUNtERlr\lTlAL AQORESS fN LIST OF A D D R E S S E SSET FLAG T O S H O W NV0 E X C H A N G E S Y E TGET AEU AODR&SS F R O M T H E L I S TAiLD TbIi iv\rEXT HlGHER O N ECOMPkt(E T H E : hAMES6KANCH if; IN C O R R E C T O R D E R A L R E A D YirTt-iERidlSk E X C H A N G E A D D R E S S E S IN.LXST

IWICATE THAN A N EXCHAN43Z rSCCURRE0llvCREMENT A D D R E S S LIST 9QXNTERJUMP TO 00 AWITHER C O M P A R I S O NNUW, SEk’ IF A N Y E X C H A N G E S W E R E MACIEIf YESi GRANCH fO M A K E ,ANGTHER P A S S

In doing the name comparison above, we have relied on the fact that the

punctuation character at the end of a name has an EBCDIC representation of

smaller value than that of letters -- this state of affairs is often expressed

:by saying that special characters are lower in the EBCDIC col.lating sequence

(the nature1 ordering implied by the value of the character) than letters.

Thus "SMITH, " will compare smaller than "SMITHW", and shorter names will

sort ahead of longer ones with the same beginning letters. If two identiaalnames are'found, the camparison will either branch on equality and no

exchange will be made, or the inequality will be determined by whatever

the characters in the following name happen to be; the addresses of the

identical names will still be adjacent in the sorted list.

Finally, suppose we are required to place the names in alphabetical

order in a string beginning at S#RT, again separated by commas and.ter?.ninated

with a period. *

20-14

. .

c IrNBRhMSLA 2dI STSR 0 . 0LA 4 , S O R T - 1

AGRGUT L 3qOtOw2)XC Oto(0~2~WC OtMCIVE+lLA 4ti(Ot4)

MCVE MVC 0(0,4),01.3)AR 490

-MVI 0/4J~C','LA 2,4(0,2)8CT 1 ~ADiWLTif ‘v 1 tA4i,P,@

CUUl\rTEK FOR lW1”IBER O F N A M E S ’RZ wiu-~ms ADDRESS of ~JRRENT LXST ENTRYKO WrXLA CONTAW L E N G T H CF N A M EA4 WXA~ H A V E A D D R E S S s1F GUTPlJT N A M EUS- ADiMESS f-RUM LIST6;El- AENC;TH 8YTE F R O M T A B L ESTWE XrL M V C LEhGVH FXELDML)Vk ADWXESS T O STARJ O F NEXT N A M ErYlliVE E\rAhlE IlL?G GUTPUT A R E AFuRM ADDkESS GF FULLQlrJXhG P U N C T U A T I O NSTUKE: C O M M A A F T E R N A M EhCKEME~\IT ADGRESS O F L I S T II-EMLAN4 T 9 3itANCt-i I-G G E T N E X T N A M E A D D R E S S;i L tf I A i, 6 ., ‘I 5 Z CC;“:EV’A B Y A P E R I O D

In this portion of the prograrr?,, the punctuatiorl after each name was moved

with the name, but a comma was stored in all cases because the period after

the j.ast nEuge at the end of the original string was likely to appear in a

different position in the final output. !Pwo things should be noted in the

MVC instruction: firs%, the explicit length specification of zero is a

convenient nolxtion for indicating that the actual length to be used ia a

variable quantity to be specified at execution time; and second, since the- true length of the name is stored in the Length Specification Byte, one

additiunal byte (the punctuation) is moved.

20-13

The bx~&e ine-t;ructlon 9s one of the racrst uz~8ual In the System/j60@mmlction x-e*~toire, eincc it allows the pmqpammer to specif‘y that the,

tixecutim 'of another instructian should be pMf&ned. It/ is $n &-type

jnatructisn 'kith mnemonic 37% which works as ;faJ;k~s: '

1. T&e effwtive address ii computed, and tk@ rl digit of' the EX inetruction

* is savtrd.

it. ‘khe ine~~t$ion at the effective addmse iltl memWy (called the subJect

in@xuctkm) rLs placed in the Inatkv&.on Register (IR); note that the

U in the Psw 3~ unchanged, and still cotitains the address: of the

inetruction fo&~ing the EL

3* If th@ new in.st~cti-~~-~~-.tke.IR is ahother M,, a .program interruption

- -"occurs; we shall see shortly that there ie a good reason for this,

- 4. Iif the rl.digit trhich>was saved is zero,,proceed to step 5. OtherW.se,

*he! rightmost byte of I& is ORed into'the second byte of the IR;

Rx1 remains unchanged.

~ 5* The (po9sibly modified) subject Instructkon in the I!3 is now decoded

lnnd executed as 'though it were the original instruction fetched from

memory.

First, consider a few examples of the use of EX in which the rl digit

is zero, 80 that no ORing takes place in the IR.

(1) Sto&. at C the quantity 2*C(A)-C(B), where A and B are fullwords.

4R lrl C L E A R I N D E X TO 0‘CA . 2.14 INCREMENT = 49 L E N G T H O F E X E C U T E D I.NSTNSLA 342

EX EX 0,INSTU)BXLE 192,EX

* :hlst ;:WI

?hAAR -b-V0NOPR 0 ’S bV0

‘ST 0,c

C O M P A R A N D = 12E X E C U T E A N I N S T R U C T I O NI N C R E M E N T BY 4 AN0 L O O P

L O A D R O F R O M A 440BYTE INSTRUCTIONSD O U B L E C(RO) (2-8YTE fNSTRUCTI.ON)P A D D I N G INSTJWCTION t2-BYTE I N S T R U C T I O N )~SUBTR-ACT c (81 (b+YTE I N S T R U C T I O N )STfJRE R E S U L T (4+3YTE XNSTRWCTIONB

This program segment performs a simple four-instruction calculation in a

roundabout way; the list of instructions at INST co6l.d of course be executed

quite independently of the first five instructions, giving the same result

much more rapidly. It illustrates a way to execute instructions which are

"out-of-lineU and not directly in the normal stream of Frogram execution.

(2) Suppose we wish to add three fullword integers stored beginning

at Q, and branch to NOERR, ElRRl, or ERR2 respectively if 0, 1, or 2

overflows occur.

SR1A8CLAABCLAEXBC8CE3c

212OIQOtQ+414,*+02r401Q+814,*+82,4(0,2)0,*+4(2)15,NCIERR15,ERRliSrERR2

C L E A R O V E R F L O W C O U N T E RGET F I R S T I N T E G E RA D D SECIIND f NTEGW?B R A N C H I F N O O V E R F L O WXNDTtA?E O N E O V E R F L O WA D D T H I R D INTEGERB R A N C H I F N O OVERFLDWI N D I C A T E AI\IOTHER OVERFCOh’E X E C U Y fi A 8RANCt-i INSTRUCT I O NO - E R R O R 6FtANCHl-ERROR B R A N C H2-ERROR B R A N C H

In this example, the executed instruction will be one of three unconditional

branches: since this results in the IA being changed, the next instruction

to be executed 'will be located at the branch ,address, as expected.

(3) Suppose we are required to place in R6 the address of some quantity

in memory, and that the desired address is known only to be the effective

address of some RX instruction. To complicate matters, suppose further that

the addressing calculation implied by the RX instruction could make use of

any register but R14 and Rip; we will assume that Rl? is currently being

used as a base register and Rl4 contains the address of the RX instruction

in question. The technique to be used here will be to construct a LA

instruction in memory with the same index, base, and displacement fields as

the RX instruction, and then execute that instruction.

MVC t3LDlA(4),0(14) M O V E R X I N S T R U C T I O N T O W O R K A R E ANI BLDLA+L,X’OF C L E A R O L D R1 D I G I T POSITIQN01 BLDLA+L,X’60 S E T R1, D I G I T T O 6M V I BLDCAtX’41’ I N S E R T elA’ OPCOOE I N T O INSTRUCTfONEX 0,BLDLA E X E C U T E T H E CONSYRUCTED ‘ L O A D A D D R E S S ’

BLDCA &- 2HRb N O W C O N T A I N S T H E D E S I R E D A D D R E S S

4 BYTES ON HALFWORD B O U N D A R Y

21-2

. .

The above instruction sequence changes noregisters (even though RO was

available) and illustrate6 a technique that can be used when all register

content6 must remain untouched.

More powerful u6e can be made of the M: instruction when its rl digit

is not zero, implying modification of a part of the instruction placed in

the 33. For example, suppose we wish to move to Lll%! a message whose address

and length are in 118 and Rg respectively, a6 fn example (4) of Section 20.

‘BCTR 9,O D E C R E A S E L E N G T H SPECXFICATTUN f3Y 1EX 9 , M O V E E X E C U T E T H E M O V E I N S T R U C T I O NB-d

MOVE MVC LfNEI01,0t8) E X E C U T E D INSTRUCTXCV+ L E N G T H = 0

In this case the Length Specification byte is inserted by ORing into the

groper positPon in the IR, tiich has beti preset to zero by an explicit

length specification of zero in the MSE instruction. An advantage of this

method is that no modification is made of the iastruction in 6torageb

A6 another example, suppose We wi6h to branch to ?ES if' the rightmost

byte of R3 contains 00011111~.

-EX 3,CLX EXECCITE T H E COfWAIkTSON0C 89YES PRANCE If E Q U A L I T Y I!5 FtI?‘UND--I

CL1 CL1 CWECK,O E X E C U T E D I N S T R U C T I O NCHECK D C EvOOOLllll’ C O M P A R I S O N Q U A N T I T YIThis.could also be done by the following method, which modiftes storage

but does not use an EX instruction.

STC 3 , T E M P . S T O R E TH,E B Y T E T O B E T E S T E DCL1 TEMP,X’lf C O M P A R E 7.0 DESXRED P A T T E R Nac 8, YES B R A N C H IF E Q U A L

TEM? -;s- c

(4) Store at T the sum of the contents of registers RO through RlL

LA 11,lOCOOP fix 11,ADDER

BCT ll,LOOPST 0,T

ADqER iR- -

0’0

COUNT IN R l lEXECUTE.THE ADO I N S T R U C T I O ND E C R E A S E C O U N T E R A N D R E G I S T E R DTGITS T O R E S U M A T T

R 2 DIGTT MODIFlED I N E X E C U T I O N

21-3

The r2 digit of the AR instruction 5.0 modified in the IR to contain values

which run from 10 down to 1. In practice it is relatively rare that lXX

instructions are used to modify register specification digits in executed

instructions.

As a final example, suppose Rtj contains tin unknown integer which specif9er

a number of bytes to be moved from a string beginning at A to an area Vhcse

address is contained in R7.

LTR 5;5 CbECK NUMIXR I1F i3YTES T O B E MOVEDBC 12,F INIS EXIT.IF NO? G R E A T E R T H A N Z E R OLA 1tA RH C O N T A I N S e F R O M ’ A D D R E S S

TEST c 4,=F ‘2% SEE IF B Y T E C O U N T E X C E E D S 2 5 6BC 4,tAST f? NOT, 90 LAST MoveWC 0wx~7~,0~1~ iwVE 2 5 6 WYTESLA 1,256(0,1) IhiCREMENT ‘ F R O M ’ A D RESSLA 1,25610,71 ~tKREMENT ‘TW AWD

9iI! SS

S 5,--F ‘256’ tXCREASE B Y T E UIUN B Y 256BC 7 r T E S T IF ,NUT Z E R O , T E S T FUR’ FINISHBC 8,FINIS I F C O U N T fS LERUq ALL DUNE

L A S T BCTR 5,oEX

D E C R E A S E B Y T E CUutq BY 1 F O R EXECUtlE5,LMVC COVE L A S T P A R T O F C H A R A C T E R S T R I N G

FrNIS - - -- - e

LMVC m/c 0(097),0(1) MOW% L A S T ‘ P A R T O F E3YtE STRING

The underlined operands in the instructions listed in Figure 21.1

indicate the modifiable portions of each instruction type when it isthe

subject instruction of an EL The last form of operand field entry far SE?

instructions, in tihich two Lx&h Specification Rigits are provided, will

be discussed later.

TYPe Operand

’ RR

Rx

Rs

ST

SS

Figure 21.1 Modific?b?cz Pori,kx~o of Subject Instructions

Two final comments should be made concerning the execute instruction.

First, the reason that an EX may not be the subject instruction of an E'X (as

stated in step 3 of the description above) .i.s that it would be possible for

theCJ?U to remain in a Fetch-Decode Loop (comprising steps 1 through 4) ix'

the EX instruction tried to execute itself, or if a sequence of EX instructions

was circular. This is a very awkward situation to get the CPU out of, and

is avoided most stmply by not aJ.lowing the execution of Execute instrwtions.

Second, the m instruction ie sometimes treated as a branch instrrzction by

saying that it causes an unconditional branch to,the subJet% instruction

followed by an unconditional branch back to the instruction folloWng the

m, unless the subject instruction is itse3.f a successful branch. This

incorrectly descrlbes the contents of the IA, Which remains at the address

of the instruction following the EX, and obscures the method of modific&tion

of the second byte of the subject instruction, which is occasionally described

only by stating "the instruction ia modified, but remains unchanged in memory'.

While the above discussion involving the ZR may not describe precisely the- -

method used in a given model of System/360 for handling Execute instructions,

It provides a correct description of the effect of the instruction.