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COMPUTER ORGANIZATION

• Logic Design

Skill to design digital components

• JAVA Language

Skill to program a computer

• Computer Organization

Skill to build a computer

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PROGRAMMING

The interface to make a computer to perform a task.

The part of the computer that actually executes the “program” is the microprocessor or central processing unit, CPU.

CPU is a digital component that execute instructions.

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TYPES OF INSTRUCTIONS• Data Transfer Instructions

Move data from one place to another including

REGISTERS

MEMORIES

I/O DEVICES

• Data Operation InstructionsPerform operations using one or two data and store the result. Operations include

ARITHMETIC

LOGIC

SHIFT (one data)

• Program Control InstructionsChange the sequence of operations (consecutive instruction flow) conditionally or non-conditionally

• OthersINTERRUPT

HALT

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INSTRUCTION CODESA binary pattern in a specific format. Example of a microprocessor which has a simple instruction set.

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LEVELS OF PROGRAMMING LANGUAGES

• High-level – platform independent

C++

JAVA

FORTRAN

• Assembly Language – microprocessor dependent

Instruction mnemonics representing individual instruction codes

• Machine Language – microprocessor dependent

Actual instruction codes

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COMPILING AND ASSEMBLING

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JAVA COMPILATION PROCESS

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HISTORY OF COMPUTER DEVELOPMENT

ABACUS, Difference Machine (mechanical)

UNIVAC ENIAC (electronic numerical integrator and computer) 1946

MICROPROCESSOR 1971

MAINFRAME

WORKSTATION

DESKTOP 1980s (IBM PC)

INTEL and MICROSOFT

SUPER-COMPUTER (multi-processors)

source: Modern Media C.S. Choy 9

A PC

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GENERIC COMPUTER ORGANIZATION

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• Address BusSpecify a memory location for access by CPU

• Data BusData channel between CPU and other components

• Control BusA collection of individual control signalse.g. a signal to indicate whether a data is to be read into or

written out of CPU

A system may have a hierarchy of buses. For example, it may use its address, data, and control buses to access memory, and an I/O controller. The I/O controller, in turn, may access all I/O devices using a second bus, often called an I/O bus or a local bus.e.g. PCI bus

SYSTEM BUSES

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The procedure a microprocessor goes through to process an instruction.

FETCH DECODE EXECUTE

e.g. Fetch / Memory Read Operation

Memory Mapped I/O – CPU accesses an I/O device as a memory

Isolated I/O – CPU has a separate control signal to indicate an I/O read/write

INSTRUCTION CYCLE

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• Register SectionRegister directly accessible by programs – registers to store operandsRegister not directly accessible by programs – program counter instruction register

• Control UnitThe digital circuit that dictates the action sequence of CPU

Sequential circuit – finite state machineCombinational circuit – instruction decoder

• Arithmetic/Logic UnitPerform the arithmetic and logic operations

CPU INTERNAL ORGANIZATION

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TYPES OF MEMORY

• Read Only Memory, ROMData can only be read and will not be changed even power is off

• Masked ROMProgrammable ROM, PROM

Erasable PROM, EPROM

Electrically Erasable PROM, E2PROM

Flash E2PROM – electrically erasable in blocks of data

• Random Access Memory, RAMUsed to store data that changes. As long as power is on, data is kept

Dynamic RAM, DRAM – require refresh, slower

Static RAM, SRAM – no refresh, faster

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• Lineare.g. 8x2

• Two-Dimensionale.g. 8x2

MEMORY ORGANIATION

Simpler decoders are used instead. For a symmetrical two-dimensional array,

Two n/2 to 2n/2 decoders O(21+n/2)e.g. 4K x 1 ROM

2D requires 3% of LinearN to 2n decoder O(2n)

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• Wider Word Length

• Larger Memory Size

high-order interleaving low-order interleaving

MEMORY SUBSYSTEM CONFIGURATION

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CONTROL LOGIC FOR MEMORY CHIP

e.g. 8x4 memory subsystem constructed from two 8x2 memory chips in a 6-bit address bus

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MULTIBYTE DATA ORGANIZATIONMany data formats are longer than one data word/byte (bit-length of the data bus) so require more than one memory location for storage. It is necessary to define the order of the data in these locations

Big Endian Little Endian

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OTHER MEMORY SUBSYSTEMS

• Cache Memory

Cache memory can be accessed much faster than normal memory chip, and is usually integrated inside a processor chip

• Virtual Memory

A permanent storage device (harddisk) is used as a part of the computer’s memory, expanding the memory space of the computer while minimizing cost

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CPU accesses I/O devices as memories. However, I/O devices can be vastly different in speed and behavior, so an interface circuit is required

• Generic Interface for an Input Device

• Enable Logic

I/O SUBSYSTEM ORGANIZATION

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I/O SUBSYSTEM ORGANIZATION• Generic Interface for an Output Device • Enable Logic

• I/O Device

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I/O devices are usually much slower than CPU. For this reason, they can have timing problem when interfacing with CPU. To solve this problem, most CPUs have a control input signal called READY. The CPU goes into WAIT state when READY is asserted.

An alternative is to use INTERRUPT. An interrupt will direct the attention of the CPU to a self-contained program (interrupt service routine) and return the CPU to its main program after completion.

There are situations where a large amount of data are to be channeled between I/O devices and memory. It will tie up CPU too much if the transfer has to go through CPU. Direct Memory Access, DMA, is a method used to by-pass CPU in these transfers.

I/O SUBSYSTEM ORGANIZATION

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