CS 230: Computer Organization and Assembly Language
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C C M M L L C C M M L L CS 230: Computer CS 230: Computer Organization and Organization and Assembly Language Assembly Language Aviral Shrivastava Department of Computer Science and Engineering School of Computing and Informatics Arizona State University Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB
description
CS 230: Computer Organization and Assembly Language. Aviral Shrivastava. Department of Computer Science and Engineering School of Computing and Informatics Arizona State University. Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB. Announcements. - PowerPoint PPT Presentation
Transcript of CS 230: Computer Organization and Assembly Language
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CS 230: Computer CS 230: Computer Organization and Organization and
Assembly LanguageAssembly LanguageAviral
ShrivastavaDepartment of Computer Science and
EngineeringSchool of Computing and Informatics
Arizona State University
Slides courtesy: Prof. Yann Hang Lee, ASU, Prof. Mary Jane Irwin, PSU, Ande Carle, UCB
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AnnouncementsAnnouncements• Project 3
– MIPS Assembler
• Midterm Reviews
• Quiz 4– Nov 5, 2009– Single-cycle implementation
• Finals– Tuesday, Dec 08, 2009
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What is this?What is this?
001001111011110111111111111000001010111110111111000000000001010010101111101001000000000000100000101011111010010100000000001001001010111110100000000000000001100010101111101000000000000000011100100011111010111000000000000111001000111110111000000000000001100000000001110011100000000000011001001001011100100000000000000000010010100100000001000000000110010110101111101010000000000000011100000000000000000001111000000100100000001100001111110010000010000100010100001000001111111111110111101011111011100100000000000110000011110000000100000100000000000010001111101001010000000000011000000011000001000000000000111011000010010010000100000001000011000010001111101111110000000000010100001001111011110100000000001000000000001111100000000000000000100000000000000000000001000000100001 MIPS machine language code for a
routine to compute and print the sum of the squares of integers between 0 and 100.
int main (int argc, char *argv[])
{
int i;
int sum = 0;
for (i = 0; i <= 100; i = i + 1) sum = sum + i * i;
printf ("The sum from 0 .. 100 is %d\n", sum);
}
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Abstract Abstract Implementation ViewImplementation View
• Two types of functional units:– elements that operate on data values (combinational)– elements that contain state (sequential)
• Single cycle operation• Split memory (Harvard) model - one memory for
instructions and one for data
Address Instruction
InstructionMemory
Write Data
Reg Addr
Reg Addr
Reg Addr
Register
File ALU
DataMemory
Address
Write Data
Read DataPC
Read Data
Read Data
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Fetching InstructionsFetching Instructions
• Fetching instructions involves– reading the instruction from the Instruction Memory– updating the PC to hold the address of the next instruction
– PC is updated every cycle, so it does not need an explicit write control signal
– Instruction Memory is read every cycle, so it doesn’t need an explicit read control signal
ReadAddress
Instruction
InstructionMemory
Add
PC
4
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Executing R Format Executing R Format OperationsOperations
• R format operations (add, sub, slt, and, or)
– perform the indicated (by op and funct) operation on values in rs and rt
– store the result back into the Register File (into location rd)
– Note that Register File is not written every cycle (e.g. sw), so we need an explicit write control signal for the Register File
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
overflowzero
ALU controlRegWrite
R-type:
31 25 20 15 5 0
op rs rt rd functshamt
10
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Load and Store OperationsLoad and Store Operations
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
overflowzero
ALU controlRegWrite
DataMemory
Address
Write Data
Read Data
SignExtend
MemWrite
MemRead
16 32
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Executing Branch Executing Branch OperationsOperations
Instruction
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
zero
ALU control
SignExtend16 32
Shiftleft 2
Add
4 Add
PC
Branchtargetaddress
(to branch control logic)
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Executing Jump Executing Jump OperationsOperations
• Jump operations have to
– replace the lower 28 bits of the PC with the lower 26 bits of the fetched instruction shifted left by 2 bits
ReadAddress
Instruction
InstructionMemory
Shiftleft 2
Jumpaddress
26
4
28
J-Type: op
31 25 0
jump target address
Add
4
PC
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Adding the Pieces Adding the Pieces TogetherTogether
MemtoReg
ReadAddress
Instruction
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovfzero
ALU controlRegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemReadSign
Extend16 32
ALUSrc
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Adding the Branch PortionAdding the Branch Portion
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovfzero
ALU controlRegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemReadSign
Extend16 32
MemtoRegALUSrc
ReadAddress
Instruction
InstructionMemory
Add
PC
4 Shiftleft 2
Add
PCSrc
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26
Adding the Jump Adding the Jump PortionPortion
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovfzero
ALU controlRegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemReadSign
Extend16 32
MemtoRegALUSrc
ReadAddress
Instruction
InstructionMemory
Add
PC
4 Shiftleft 2
Add
PCSrc
0
1Shiftleft 2
Jump
28PC+4[31-28]
32
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26
Instr[25-0]
MIPS Machine (with MIPS Machine (with Controls) Controls)
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
Shiftleft 2
0
1
Jump
32
PC+4[31-28]
28
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ALU ControlALU Control
ALU control input
Function
000 and
001 or
010 add
110 subtract
111 set on less than
ALU's operation based on instruction type and function code
result
32
32
32
operation
a
b
ALU
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ALU ControlALU Control• Controlling the ALU makes use of multiple levels of decoding
– main control unit generates the ALUOp bits– ALU control unit generates ALU control inputs
Instr op
opcode
funct ALUOp
desired action
ALU control input
lw 23 xxxxxx 00 add 010
sw 2b xxxxxx 00 add 010
beq 4 xxxxxx 01 subtract
110
add 0 100000
10 add 010
subt 0 100010
10 subtract
110
and 0 100100
10 and 000
or 0 100101
10 or 001
slt 0 101010
10 slt 111
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ALU Control Truth TableALU Control Truth Table
• Can make use of more don’t cares– since ALUOp does not use the encoding 11– since F5 and F4 are always 10
• Logic comes from the K-maps …
X
X
X
X
X
X
F5 F4 F3 F2 F1 F0 ALUOp1 ALUOp0 Op2 Op1 Op0
X X X X X X 0 0 0 1 0
X X X X X X 1 1 1 0
X X 0 0 0 0 1 0 1 0
X X 0 0 1 0 1 1 1 0
X X 0 1 0 0 1 0 0 0
X X 0 1 0 1 1 0 0 1
X X 1 0 1 0 1 1 1 1
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ALU Control ALU Control Combinational LogicCombinational Logic
• From the truth table can design the ALU Control logic
Operation2
Operation1
Operation0
Operation
ALUOp1
F3
F2
F1
F0
F (5– 0)
ALUOp0
ALUOp
ALU control block
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Datapath with Control Datapath with Control UnitUnit
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
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Main Control UnitMain Control Unit
Instr RegDst ALUSrc MemtoReg
RegWr
MemRd
MemWr
Branch ALUOp1
ALUOp2
R-type
000000
lw
100011
sw
101011
beq
000100 Completely determined by the instruction opcode field Note that a multiplexor whose control input is 0 has a definite
action, even if it is not used in performing the operation
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R-type Instruction R-type Instruction Data/Control FlowData/Control Flow
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
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Main Control UnitMain Control Unit
Instr RegDst ALUSrc MemtoReg
RegWr
MemRd
MemWr
Branch ALUOp1
ALUOp0
R-type
000000
1 0 0 1 X 0 0 1 X
lw
100011
sw
101011
beq
000100
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Load Word Instruction Load Word Instruction Data/Control FlowData/Control Flow
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
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Main Control UnitMain Control Unit
Instr RegDst ALUSrc MemtoReg
RegWr
MemRd MemWr
Branch ALUOp1
ALUOp0
R-type
000000
1 0 0 1 X 0 0 1 X
lw
100011
0 1 1 1 1 0 0 0 0
sw
101011
beq
000100
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Store Word Instruction Store Word Instruction Data/Control FlowData/Control Flow
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
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Main Control UnitMain Control Unit
Instr RegDst ALUSrc MemtoReg
RegWr
MemRd
MemWr
Branch ALUOp1
ALUOp0
R-type
000000
1 0 0 1 X 0 0 1 X
lw
100011
0 1 1 1 1 0 0 0 0
sw
101011
X 1 X 0 X 1 0 0 0
beq
000100
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Branch Instruction Branch Instruction Data/Control FlowData/Control Flow
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
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Main Control UnitMain Control Unit
• Completely determined by the instruction opcode field– Note that a multiplexor whose control input is 0 has a definite
action, even if it is not used in performing the operation
Instr RegDst ALUSrc MemtoReg
RegWr
MemRd
MemWr
Branch ALUOp1
ALUOp0
R-type
000000
1 0 0 1 X 0 0 1 X
lw
100011
0 1 1 1 1 0 0 0 0
sw
101011
X 1 X 0 X 1 0 0 0
beq
000100
X 0 X 0 X 0 1 X 1
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Control Unit LogicControl Unit Logic• From the truth table can design the Main Control logic
Instr[31]Instr[30]Instr[29]Instr[28]Instr[27]Instr[26]
R-type lw sw beqRegDst
ALUSrc
MemtoReg
RegWrite
MemRead
MemWrite
Branch
ALUOp1
ALUOp0
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Complete Datapath with Complete Datapath with Controls Controls
ReadAddress
Instr[31-0]
InstructionMemory
Add
PC
4
Write Data
Read Addr 1
Read Addr 2
Write Addr
Register
File
Read Data 1
Read Data 2
ALU
ovf
zero
RegWrite
DataMemory
Address
Write Data
Read Data
MemWrite
MemRead
SignExtend16 32
MemtoReg
ALUSrc
Shiftleft 2
Add
PCSrc
RegDst
ALUcontrol
1
1
1
00
0
0
1
ALUOp
Instr[5-0]
Instr[15-0]
Instr[25-21]
Instr[20-16]
Instr[15 -11]
ControlUnit
Instr[31-26]
Branch
Shiftleft 2
0
1
Jump
32Instr[25-0]
26PC+4[31-28]
28
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Disadvantages of Single Cycle Disadvantages of Single Cycle ImplementationImplementation
• Uses the clock cycle inefficiently – the clock cycle must be timed to accommodate the slowest instruction– especially problematic for more complex
instructions like floating point multiply
• Is wasteful of area since some functional units must be duplicated since they can not be “shared” during an instruction execution– e.g., need separate adders to do PC update and
branch target address calculations, as well as an ALU to do R-type arithmetic/logic operations and data memory address calculations
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Yoda says…Yoda says…
Use your feelings, Obi-Wan, and find him you will
