CS110ComputerArchitecture

Lecture8:SynchronousDigitalSystems

Instructor:SörenSchwertfeger

http://shtech.org/courses/ca/

School of Information Science and Technology SIST

ShanghaiTech University

1Slides based on UC Berkley's CS61C

LevelsofRepresentation/Interpretation

lw $t0,0($2)lw $t1,4($2)sw $t1,0($2)sw $t0,4($2)

HighLevelLanguageProgram(e.g.,C)

AssemblyLanguageProgram(e.g.,MIPS)

MachineLanguageProgram(MIPS)

HardwareArchitectureDescription(e.g.,blockdiagrams)

Compiler

Assembler

MachineInterpretation

temp=v[k];v[k]=v[k+1];v[k+1]=temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

LogicCircuitDescription(CircuitSchematicDiagrams)

ArchitectureImplementation

Anythingcanberepresentedasanumber,

i.e.,dataorinstructions

2

• ParallelRequestsAssigned tocomputere.g.,Search“Katz”

• ParallelThreadsAssigned tocoree.g.,Lookup,Ads

• ParallelInstructions>1instruction@onetimee.g.,5pipelined instructions

• ParallelData>1dataitem@one timee.g.,Addof4pairsofwords

• HardwaredescriptionsAllgates@onetime

• ProgrammingLanguages3

SmartPhone

WarehouseScale

Computer

SoftwareHardware

HarnessParallelism&AchieveHighPerformance

LogicGates

Core Core…

Memory(Cache)

Input/Output

Computer

CacheMemory

Core

InstructionUnit(s) FunctionalUnit(s)

A3+B3A2+B2A1+B1A0+B0

Today

YouareHere!

HardwareDesign• Nextseveralweeks:howamodernprocessorisbuilt,

startingwithbasicelementsasbuildingblocks• Whystudyhardwaredesign?

– UnderstandcapabilitiesandlimitationsofHWingeneralandprocessorsinparticular

– Whatprocessorscandofastandwhattheycan’tdofast(avoidslowthingsifyouwantyourcodetorunfast!)

– Backgroundformorein-depthHWcourses– Hardtoknowwhatyou’llneedfornext30years– Thereisonlysomuchyoucandowithstandardprocessors:you

mayneedtodesignowncustomHWforextraperformance– Evensomecommercialprocessorstodayhavecustomizablehardware!

4

SynchronousDigitalSystems

5

Synchronous:• Alloperationscoordinatedbyacentralclock

§ “Heartbeat”ofthesystem!

Digital:• Representallvalues bydiscretevalues• Twobinarydigits:1and0• Electricalsignalsaretreatedas1’sand0’s

• 1and0arecomplementsofeachother• High /low voltagefortrue /false,1 /0

Hardwareofaprocessor, suchastheMIPS,isanexampleofaSynchronousDigitalSystem

A Z

Switches:BasicElementofPhysicalImplementations

• Implementingasimplecircuit(arrowshowsactionifwirechangesto“1”orisasserted):

Z ≡ A

A Z

6

On-switch(ifAis“1”orasserted)turns-onlightbulb(Z)

Off-switch(ifAis“0”orunasserted)turns-offlightbulb(Z)

AND

OR

Z ≡ A and B

Z ≡ A or B

A B

A

B

Switches(cont’d)

• Composeswitchesintomorecomplexones(Booleanfunctions):

7

HistoricalNote

• Earlycomputerdesignersbuiltadhoccircuitsfromswitches

• Begantonoticecommonpatternsintheirwork:ANDs,ORs,…

• Master’sthesis(byClaudeShannon,1940)madelinkbetweenworkand19th CenturyMathematicianGeorgeBoole– Calledit“Boolean”inhishonor

• Couldapplymathtogivetheorytohardwaredesign,minimization,…

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Transistors• Highvoltage(Vdd)represents1,ortrue

– Inmodernmicroprocessors,Vdd ~1.0Volt• Lowvoltage(0Voltor Ground)represents0,orfalse• Pickamidpointvoltagetodecideifa0ora1

– Voltagegreaterthanmidpoint=1– Voltagelessthanmidpoint=0– Thisremovesnoiseassignalspropagate– abigadvantageof

digitalsystemsoveranalogsystems• If oneswitchcancontrolanotherswitch,wecanbuilda

computer!• Ourswitches:CMOStransistors

9

CMOSTransistorNetworks• ModerndigitalsystemsdesignedinCMOS– MOS:Metal-OxideonSemiconductor– Cforcomplementary: usepairsofnormally-on andnormally-off switches

• CMOStransistorsactasvoltage-controlledswitches– Similar,thougheasiertoworkwith,thanelectro-mechanicalrelayswitchesfromearlierera

– Useenergyprimarilywhenswitching

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n-channel transitoroff when voltage at Gate is low

on when:voltage(Gate) > voltage (Threshold)

p-channel transistoron when voltage at Gate is low

off when:voltage(Gate) > voltage (Threshold)

CMOSTransistors• Threeterminals: source,gate,anddrain– Switchaction:ifvoltageongateterminalis(someamount)higher/lowerthansourceterminalthenconductingpathestablishedbetweendrainandsourceterminals(switchisclosed)

Gate

Source Drain

Gate

Source Drain

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Notecirclesymboltoindicate“NOT”or“complement”

Gate

DrainSource

field-effecttransistor(FET)=>CMOScircuitsuseacombinationofp-typeandn-typemetal–oxide–semiconductor field-effecttransistors=>

MOSFET

12

GordonMooreIntelCofounder

#oftran

sistorso

nan

integrated

circuit(IC)

Year

#2:Moore’sLaw

Predicts:2XTransistors/chip

every2years

Modernmicroprocessorchipsincludeseveralbilliontransistors

Intel14nmTechnology

13Planviewoftransistors

Sideviewofwiring layers

SenseofScale

14

Source:MarkBohr, IDF14

CMOSCircuitRules• Don’tpassweakvalues=>UseComplementaryPairs

– N-typetransistorspassweak1’s(Vdd - Vth)– N-typetransistorspassstrong0’s(ground)– UseN-typetransistorsonlytopass0’s(Nfornegative)– ConverseforP-typetransistors:Passweak0s,strong1s

• Passweak0’s(Vth),strong1’s(Vdd)• UseP-typetransistorsonlytopass1’s(Pforpositive)

– UsepairsofN-typeandP-typetogetstrongvalues• Neverleaveawireundriven

– Makesurethere’salwaysapathtoVdd orGND

• NevercreateapathfromVdd toGND(ground)– Thiswouldshort-circuitthepowersupply!

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1V

X

Y 0Volt(GND)

x y

1 Volt(Vdd)

0V

whatistherelationship

betweenxandy?

CMOSNetworks

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p-channel transistoron when voltage at Gate is low

off when:voltage(Gate) > voltage (Threshold)

n-channel transitoroff when voltage at Gate is low

on when:voltage(Gate) > voltage (Threshold) Calledaninverterornotgate

1 Volt (Vdd)

0Volt (GND)

what is the relationship between x, y and z?

Two-InputNetworks

1V

X Y

0V

Z

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x y z

0 Volt

1 Volt

0 Volt

1 Volt

0 Volt

0 Volt1 Volt

1 Volt

1 Volt

1 Volt

1 Volt

0 Volt

CalledaNANDgate(NOTAND)

x y

0Volt

1Volt

0Volt

1Volt

0Volt

0Volt

1Volt

1Volt

Clickers/PeerInstruction

1V

X Y

0v

Z

18

Volts

Volts

Volts

Volts

z

0 0 1

0 1 0

0 1 0 1

1 1 0 0

A B C

Administrivia

• FinalHW1scoreswillbepublishednextweek:–Wewillbyhandtakeaquicklookanddeductpointsforbugs,e.g.• Memoryleaks• reverse_list changingtheprovidedlist• Emptyormeaninglesscomments

• Project1.1testcaseswillbeupdatedlatestMonday– gradingsimilartoabove– 11groupsdidnotregistertheirgroupe-mailyet!– 8groupshaveregistrationspendingingradebot!

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Administrivia• BuginHW3gradingscript…• InLab8:– YourprojectteamexplainstheTAandProfyourprojects1.1and1.2

– Bothofyoushouldknowyoursoftwarewell– Ifwefindoneofyouclearlydidcontributemuchless,wewillreducethatstudentspointsalittle

• CheckouttheadditionalmaterialprovidedbyUCBerkeley:– http://inst.eecs.berkeley.edu/~cs61c/resources/sds.pdf– http://inst.eecs.berkeley.edu/~cs61c/resources/boolean.pdf

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PolicyonAssignmentsandIndependentWork

• ALLPROJECTSWILLBEDONEWITHAPARTNER• Withtheexceptionoflaboratoriesandassignmentsthatexplicitlypermityouto

workingroups, allhomeworkandprojectsaretobeYOURworkandyourworkALONE.

• PARTNERTEAMSMAYNOTWORKWITHOTHERPARTNERTEAMS• Youareencouraged todiscussyourassignmentswithotherstudents,andcreditwill

beassignedtostudentswhohelpothers,particularlybyansweringquestionsonPiazza,butweexpectthatwhatyouhandinisyours.

• ItisNOTacceptabletocopysolutions fromother students.• ItisNOTacceptabletocopy(or startyour) solutions fromtheWeb.• ItisNOTacceptabletousePUBLICgithub archives(giving youranswersaway)• Wehavetoolsandmethods, developedovermanyyears,fordetectingthis.You

WILLbecaught,andthepenaltiesWILLbesevere.• AttheminimumFinthecourse,andalettertoyouruniversityrecorddocumenting

theincidenceofcheating.• BothGiverandReceiverareequallyculpableandsufferequalpenalties

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• Commoncombinationallogicsystemshavestandardsymbolscalledlogicgates

– Buffer,NOT

– AND,NAND

– OR,NOR

CombinationalLogicSymbols

Z

AB Z

Z

A

AB

Invertingversions(NOT,NAND,NOR)easiest

toimplement withCMOStransistors (the

switches wehaveavailableandusemost)

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1V

X Y

0V

1V

XY

0V

Remember…

•AND•OR

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BooleanAlgebra

• Useplus“+”forOR– “logicalsum” 1+0=0+1=1(True);1+1=2(True);0+0=0(False)

• UseproductforAND(a�b orimpliedviaab)– “logicalproduct”0*0=0*1=1*0=0(False);1*1=1(True)

• “Hat”tomeancomplement(NOT)• Thusab +a+c

= a�b +a+c= (aANDb)ORaOR(NOTc )

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TruthTablesforCombinationalLogic

25

F Y

AB

CD

0

Exhaustivelistoftheoutputvaluegeneratedforeachcombinationofinputs

HowmanylogicfunctionscanbedefinedwithNinputs?

TruthTableExample#1:y=F(a,b):1iff a≠b

a b y0 0 00 1 11 0 11 1 0

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Y=AB+AB

Y=A+B

XOR

TruthTableExample#2:2-bitAdder

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HowManyRows?

+ C1

A1A0

B1B0

C2

C0

TruthTableExample#3:32-bitUnsignedAdder

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HowManyRows?

TruthTableExample#4:3-inputMajorityCircuit

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Y=ABC+ABC+ABC+ABC

Y=BC+A(BC+BC)

Y=BC+A(B+C)

ThisiscalledSumofProducts form;JustanotherwaytorepresenttheTTasalogicalexpression

Moresimplifiedforms(fewergatesandwires)

BooleanAlgebra:Circuit&AlgebraicSimplification

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RepresentationsofCombinationalLogic(groupsoflogicgates)

TruthTable

GateDiagramBooleanExpression

SumofProducts,ProductofSumsMethods

EnumerateInputs

EnumerateInputs

UseEquivalencybetweenbooleanoperatorsand

gates

LawsofBooleanAlgebra

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XX=0X0=0X1=XXX=XXY=YX

(XY)Z=Z(YZ)X(Y+Z)=XY+XZ

XY+X=XXY+X=X+YXY=X+Y

X+X=1X+1=1X+0=XX+X=X

X+Y=Y+X(X+Y)+Z=Z+(Y+Z)X+YZ=(X+Y)(X+Z)

(X+Y)X=X(X+Y)X=XYX+Y=XY

ComplementarityLawsof0’sand1’s

IdentitiesIdempotentLawsCommutativityAssociativityDistribution

UnitingTheoremUnitingTheoremv.2DeMorgan’s Law

BooleanAlgebraicSimplificationExample

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BooleanAlgebraicSimplificationExample

34

ab c y00000011010001111001101111011111

Question

• SimplifyZ=A+BC+A(BC)

• A: Z=0• B: Z=A(1+BC)• C:Z=(A+BC)• D:Z=BC• E:Z=1

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IntheNews:GooglesAlphaGo beatsworldchampionLeeSedol

• Googlewins4:1• Go:maybe200possiblemovesperturn– 250ormoreturns– even200150 isaboutinfinite(chess:about3580)

• MonteCarloTreeSearch(MCTS)andMachineLearning(NeuralNetworks)

• 1202CPUsund176GPU(or more)

• Onemillion USDprize

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SignalsandWaveformsan-1 an-1 a0

Noisy!Delay!

SignalsandWaveforms:Grouping

SignalsandWaveforms:CircuitDelay

2

3

3 4 5

10 0 1

5 13 4 6

SampleDebuggingWaveform

TypeofCircuits• SynchronousDigitalSystemsconsistoftwobasictypesofcircuits:• CombinationalLogic(CL)circuits

–Outputisafunctionoftheinputsonly,notthehistoryofitsexecution– E.g.,circuitstoaddA,B(ALUs)

• SequentialLogic(SL)• Circuitsthat“remember”orstoreinformation• aka“StateElements”• E.g.,memoriesandregisters(Registers)

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UsesforStateElements

• Placetostorevaluesforlaterre-use:– Registerfiles(like$1-$31inMIPS)– Memory(cachesandmainmemory)

• Helpcontrolflowofinformationbetweencombinational logicblocks– Stateelementsholdupthemovementofinformationatinputtocombinationallogicblockstoallowfororderlypassage

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AccumulatorExample

Want: S=0; for (i=0;i<n;i++)

S = S + Xi

Whydoweneedtocontroltheflowofinformation?

Assume:• EachXvalueisappliedinsuccession,onepercycle• AfterncyclesthesumispresentonS

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SUMXi S

FirstTry:Doesthiswork?

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No!Reason#1:Howtocontrolthenextiterationofthe‘for’loop?Reason#2:Howdowesay:‘S=0’?

Feedback

SecondTry:HowAboutThis?

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Roughtiming…

Registerisusedtoholdupthetransferofdatatoadder

Time

High (1)Low(0)

High (1)Low(0)

RoundedRectangleperclockmeanscouldbe1or0

High (1)Low(0)

Squarewaveclocksetswhenthingschange

SecondTry:HowAboutThis?

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Roughtiming…

Registerisusedtoholdupthetransferofdatatoadder

RoundedRectangleperclockmeanscouldbe1or0

Ximustbereadybeforeclockedgedue toadderdelay

Squarewaveclocksetswhenthingschange

High (1)Low(0)

High (1)Low(0)

High (1)Low(0)

ModelforSynchronousSystems

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• Collectionof CombinationalLogicblocksseparatedbyregisters• Feedbackisoptional• Clocksignal(s)connectsonlytoclockinputofregisters• Clock(CLK):steadysquarewavethatsynchronizesthesystem• Register:severalbitsofstatethatsamplesonrisingedgeofCLK(positiveedge-triggered)orfallingedge(negativeedge-triggered)