Hardware Cryptographic Coprocessor Peter R. Wihl Security in Software.
Cryptographic Hardware and Communications Security Research at
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Cryptographic Hardware and Cryptographic Hardware and Communications Security Research Communications Security Research at Memorial University at Memorial University Prinicipal Researcher: Dr. Howard Heys Electrical and Computer Engineering
Transcript of Cryptographic Hardware and Communications Security Research at
Cryptographic Hardware and Cryptographic Hardware and Communications Security Research Communications Security Research
at Memorial Universityat Memorial University
Prinicipal Researcher:
Dr. Howard HeysElectrical and Computer Engineering
Cryptography: Cryptography: Implementations and Implementations and ApplicationsApplications
Hardware … Software
Lightweight … High Speed
FPGAs, ASICs
Applications:embedded systems such as mobile devices, smartcards, RFID
Designs:iterative small area, low power,
low throughput
Applications:network processors, servers
Designs:pipelined large area, high power,
high throughput
Lightweight CryptographyLightweight Cryptography• Compact and Low Power/Energy
Hardware implementations
application to small embedded devices such as smartcards and RFID tags
• compact block cipher with 64-bit block and 80-bit key
• strong security properties• only ~1000 gates to
implement in 0.18 m CMOS technology
.
[61 :64 ] [77 :80 ] [1 :140 ][141 :144 ]
0 1
S
01
[1 :4 ] [5 :144 ]
144 -bit Register
A0000
P
[81 :144 ][1:80 ]
0 1
4 4 1404 144
4
6480
[1:80 ] [81 :144 ]
Ciphertext/Plaintext 4
144
Plaintext/Ciphertext
+Key
4
PUFFIN: PUFFIN: A Novel LightweightA Novel Lightweight Block CipherBlock Cipher
Side Channel AnalysisSide Channel Analysis
• implementation characteristics can be measured and related to data being processed to attack ciphers: power analysis, timing analysis, fault attacks,
template attacks
Distinguishing keys in a template attack
Side Channel Analysis BoardSide Channel Analysis Board
• testbed to study SCAapplied to FPGA implementations
• initially applied to template attacks on stream ciphers
• can also be used to studypower, timing, and fault attacks
SelfSelf--Synchronizing CiphersSynchronizing Ciphers• encryption at physical layer:
loss or insertion of data due to timing errors can result in permanent synchronization loss
• solution: use ciphertext data at receiver to resynchonize
self-synchronizationdecrypt
1100…0001 0010…1111 1011…0010 sent
?110…000 1010…1111 1001…0010 received
X
????…????????…????????…????
bit error corrupts complete block
bit loss corrupts all subsequent blocks
bit errorbit loss
decrypt
1100…0001 0010…1111 1011…0010 sent
?110…000 1010…1111 1001…0010 received
X
????…????????…????????…????
bit error corrupts complete block
bit loss corrupts all subsequent blocks
bit errorbit loss
Statistical Cipher Feedback (SCFB)Statistical Cipher Feedback (SCFB)
• self-synchronizing hybrid of counter or output feedback (OFB) and cipher feedback (CFB) modes in normal operation, configured as counter/OFB mode
with B bit feedback when n bit sync pattern detected in ciphertext, next B bits
used as initialization vector to block operation
E
PC
ZSCAN
E
PC
ZSCAN
Decrypt
input register input register
Wireless Sensor Network Wireless Sensor Network Security ProtocolsSecurity Protocols
• WSN useful for applications such as biomedical and environmental monitoring
• sensor nodes in network have limited battery life
A N
BS
{IDN,NN}
{IDN | NN | IDA | NA}KIDA,MAC(KIDA*,{ IDN |NN |IDA |NA}KIDA)
{KAN} KIDN, MAC(KIDN*,IDA|NN|{KAN}KIDN)
{KAN} KIDA, MAC(KIDA*,IDN|NA|{KAN}KIDA)
(1)
(2)
(3)
(4)
• cryptographic protocols and algorithms must minimize energy use in sensor nodes
efficient ciphers and protocols that minimize transmission energy are requiredKey Exchange in WSN
WSN Cipher FeedbackWSN Cipher Feedback
• block ciphers with ciphertextfeedback minimizes transmission
energy cost allows for error recover
from lost packets
battery life maximized0 5 10 15 20 25 30
0
0.5
1
1.5
2
2.5
3
3.5
4x 10
4
Payload size (bytes)
Ene
nrgy
Effi
cien
cy (b
ytes
/J)
Implicit IV schemeTinySec schemePeriodic IV without ackPeriodic IV with ackCFB scheme
Future WorkFuture Work
• lightweight embedded applications increasingly important, particularly for wireless applications
• new modes needed for high speed systems susceptible to sync loss
• cryptographic system design and hardware implementation critical to successful realization of embedded applications and high speed communication systems
Sample PublicationsSample Publications(1) H.M. Heys and L. Zhang, “Pipelined Statistical Cipherfeedback: A New Mode for
High Speed Self-Synchronizing Stream Encryption”, to appear in IEEE Transactions on Computers, 2010.
(2) C. Wang and H.M. Heys, “Using a Pipelined S-box in Compact AES Hardware Implementations”, IEEE NEWCAS Conference, Montreal, Canada, 2010.
(3) H. Cheng, H.M. Heys, and C. Wang, "PUFFIN: A Novel Compact Block Cipher Targeted to Embedded Digital Systems", Euromicro DSD 2008, Parma, Italy, 2008.
(4) N. Yu and H.M. Heys, "A Hybrid Approach to Concurrent Error Detection for a Compact ASIC Implementation of AES", CSS 2007, Banff, Alberta, 2007.
(5) L. Zhang and H.M. Heys, "Hardware Design and Analysis of Statistical Cipher Feedback Mode Using Serial Transfer", IEEE CCECE 2007, Vancouver, BC, 2007.
(6) L. Xiao and H.M. Heys, "Software Performance Characterization of Block Cipher Structures", IEE Proceedings - Communications, 2005.
(7) L. Xiao and H.M. Heys, "A Simple Power Analysis Attack Against the Key Schedule of Camellia", Information Processing Letters, Elsevier, 2005.
(8) M. Furlong and H.M. Heys, "A Timing Attack on the CIKS-1 Block Cipher", IEEE CCECE 2005, Saskatoon, Saskatchewan, 2005.
