Creating IPCore Loi 11May2013

7/28/2019 Creating IPCore Loi 11May2013

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REPORT

LCD CONTROLLER ON VIRTEX 5 FPGA

Name: Le Van Loi

DA NANG, 2013


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1. 16 characters x 2 l ines LCD displaying on Vir tex-5 FPGA usin g

VHDL langu age:

a. Design process :

Figur e 1. Design process of LCD_Controller

Building initializing algorithm of LCD

and investigate how to write to

instruction and data register of LCD

Description the behavior of LCD by

VHDL language

Simulation, testing, debugging on chip

Program FPGA


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b. Implementat ion :

o LCD initializing process : prefer to the datasheet of Hitachi

Dot Matrix Liquid Crystal Display Controller/Driver HD44780U

(LCD-II)

o Mode : 4-bit interface, 5x8 dots

For 4-bit interface data, only four bus lines (DB4 to DB7)are used for transfer. Bus lines DB0 to DB3 are disabled.The data transfer between the HD44780U and the MPU iscompleted after the 4-bit data has been transferred twice.

As for the order of data transfer, the four high order bits(for 8-bit operation, DB4 to DB7) are transferred beforethe four low order bits (for 8-bit operation, DB0 to DB3).The busy flag must be checked (one instruction) after the4-bit data has been transferred twice. Two more 4-bitoperations then transfer the busy flag and addresscounter data.


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o Initialization :

o LCD location :

NET LCD_FPGA_DB4 LOC="T9"; # Bank 12,Vcco=3.3V, DCI using 49.9 ohm resistorsNET LCD_FPGA_DB5 LOC="G7"; # Bank 12,Vcco=3.3V, DCI using 49.9 ohm resistorsNET LCD_FPGA_DB6 LOC="G6"; # Bank 12,Vcco=3.3V, DCI using 49.9 ohm resistorsNET LCD_FPGA_DB7 LOC="T11"; # Bank 12,Vcco=3.3V, DCI using 49.9 ohm resistorsNET LCD_FPGA_E LOC="AC9"; # Bank 22,Vcco=3.3V, DCI using 49.9 ohm resistorsNET LCD_FPGA_RS LOC="J17"; # Bank 3, Vcco=2.5V,No DCINET LCD_FPGA_RW LOC="AC10"; # Bank 22,Vcco=3.3V, DCI using 49.9 ohm resistors


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o VHDL module:

Input: Clock (CLK_33MHZ_FPGA LOC="AH17")

Output:

LCD_RS: Selects registers.

o 0: Instruction registers (for write). Busy flag address counter (for read)

o 1 : Data register (for write and read)

LCD_RW: Selects read or write.

o 0: Write

o 1: Read

LCD_E : Starts data read/write.

LCD_DB7->LCD_DB4: 4 bit data

LED_OUT: turn off LED when the displayingfinished

- Display: String START on line 1 and LOI09DT1 on line 2 at the 6th

position.

o To move cursor to a certain position on 1st line of LCD, writing

0x80 -> 0x8F to instruction register.

0x80 : 1st position

0x81: 2nd

.

0x8F: 16th position on the first line

o To move cursor to a certain position on 2st line of LCD, writing

0xC0 -> 0xCFto instruction register.

0xC0 : 1st position

0xC1: 2nd

.

0xCF: 16th position on the 2nd line

-


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- Follow the following table to get the binary data and write to the

DDRAM of LCD:

o S(0x53), T(0x54), A(0x41), R(0x52)


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- Required input signals for Instruction & data register write:

- After description by using VHDL language, we need to test code

using ISIM.

- Simulation using ISIM:

o Just provide a clock and observe the data out on the port.

o DB4-> DB7 followed the initializing process and data writing to

the LCD, so we can fetch data into the Virtex-5 FPGA and

watch the string on the LCD.


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- Finally, programming file to the Virtex-5 FPGA. The result below:

- Prefer to LCD_Control ler ISE project to read mo re detai l

2. Debugging on chip using Chipscope Analyzer:

- Click right mouse to the LCD_Controller top module and select new

source: choose Chipscope definition and constraints file


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Select next and ok.

Continue, double click on debug_on_chip.cdc to setting clock port and data

port that we want to observe the waveform.

Chip scope pro Analyzer will load at the below:

Click Next,

Choose Trigger width is 5 to see the waveform of DB4-> DB7 and

LED_out. Then, click next


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Select Data Depth is 131072 samples

C

l

ic

k

N

e

x

t

,

Then, modify connections of Clock port and Trigger ports:


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Choose the connections for clock signal and trigger/data signals.

After that, return to ISE project

In design tag, double click Analyze design using Chip scope.


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Select new file: LCD_Controller.bit and click waveform to see the signals

after running on chip. Also, observe the result on LCD.

3. Convert ing LCD_Contro l ler modu le into IP cor e and prog ram

Virtex-5 FPGA:

- Previous project : XUPV5-LX110T with system.xmp

- Task: Convert LCD_Controller.vhd into an IP core and add the core

to the above project, program and observe results.

- Firstly, delete LCD_7bit module in the project, open the project and

click Hardware, choose Create and Import Peripherals Wizard:


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Click Next,

Then click Import existing peripheral and press Next


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Next

Enter LCD_Controller.


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Next,

Next, then add LCD_Controller.vhd file and click Next


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Uncheck select bus interface(s), then Next

Continue to uncheck select and configure interrupt(s), then Next


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Next,

Then finish creating the IP core.

Now, add the IP to the project


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Then click OK and choose the connection of the LCD_Controller

Because the minimum frequency of Clock in previous project is 62.5 MHz

and clk of LCD_Controller is 33MHz, we change values of delay in

LCD_Controller.vhd file.

Then add new location for LCD pin to system.ucf file:

# LCD_FPGA_DB4

Net LCD_Controller_0_DB_pin LOC = T9 | IOSTANDARD=LVCMOS33 |

PULLDOWN | SLEW=SLOW | DRIVE=2;

# LCD_FPGA_DB5

Net LCD_Controller_0_DB_pin LOC = G7 | IOSTANDARD=LVCMOS33 |


# LCD_FPGA_DB6

Net LCD_Controller_0_DB_pin LOC = G6 | IOSTANDARD=LVCMOS33 |PULLDOWN | SLEW=SLOW | DRIVE=2;

# LCD_FPGA_DB7

Net LCD_Controller_0_DB_pin LOC = T11 | IOSTANDARD=LVCMOS33 |


# LCD_FPGA_RW

Net LCD_Controller_0_LCD_RW_pin LOC = AC10 | IOSTANDARD=LVCMOS33 |


# LCD_FPGA_RS

Net LCD_Controller_0_LCD_RS_pin LOC = J17 | IOSTANDARD=LVCMOS25 |


# LCD_FPGA_E


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Net LCD_Controller_0_LCD_E_pin LOC = AC9 | IOSTANDARD=LVCMOS33 |


Then Generate bit stream and download bit stream into Virtex-5 FPGA andget the same string START on the first line and LOI-09DT1 on the 2nd

line.

Creating IPCore Loi 11May2013

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