CPU Fetch/Execute Cycle
10
CPU Fetch/Execute Cycle • Computer program • Electronic clock • Computer Memory • Data/address buses • Fetch/Execute Cycle • Accumulator • ALU/Control Unit/Program Counter • CIR/MDR/MAR
description
CPU Fetch/Execute Cycle. Computer program Electronic clock Computer Memory Data/address buses Fetch/Execute Cycle Accumulator ALU/Control Unit/Program Counter CIR/MDR/MAR. Electronic Clock. Internal Bus. Program Counter. Data. Control Unit. Internal Bus. Bus. - PowerPoint PPT Presentation
Transcript of CPU Fetch/Execute Cycle
CPU Fetch/Execute Cycle
• Computer program
• Electronic clock
• Computer Memory
• Data/address buses
• Fetch/Execute Cycle
• Accumulator
• ALU/Control Unit/Program Counter
• CIR/MDR/MAR
Simple MicroprocessorMemory
ElectronicClock
ArithmeticLogic Unit
Accumulator
Control Unit
Memory Address Register
Current Instruction Register
Memory Data Register
Program Counter
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
Simple Microprocessor
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
100
101
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
Simple Microprocessor
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100100 = 100
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
100
101
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
Fetch Phase (1st Instruction)
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100100 = 100
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
100
101
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
10011010
10011010
0100100
1st Instruction Decoded
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100101 = 101
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
101
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
10011010
10011010
0100100
10011010
Load number from memory location 10
1st Instruction Executed
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100101 = 101
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
101
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
00000010
10011010
00001010
10011010
Load number from memory location 10
00000010
Fetch Phase (2nd Instruction)
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100101 = 101
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
101
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
11001011
11001011
01100101
00000010
PC 01100110 = 102
2nd Instruction Decoded
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100110 = 102
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
11001011
11001011
01100101
11001011
Load number from memory location 11
00000010
2nd Instruction Execution
Memory
ElectronicClock
ALU
Accumulator
Control Unit
MAR
CIR
MDR
PC 01100110 = 102
Internal Bus
SpecialInternal Bus
Structure
Data
Bus
Data
Bus Data
Bus
Data
Bus
Internal Bus
Address Bus
Data bus
10
11
12
…
102
00000010
00000011
00000000
10011010
11001011
11101100
(2)
(3)
(R)
00000011
11001011
00001011
11001011
00000010
0000001000000011 + 00000101
00000101
