CPE/EE 427, CPE 527, VLSI Design I:

CPE/EE 427, CPE 527, VLSI Design I: Tutorial #5, Standard cell design flow and Power Analysis

(from vhdl to layout, mu0 processor)

Joel Wilder and Aleksandar Milenkovic, ECE Dept., The University of Alabama in Huntsville

1. INTRODUCTION This tutorial steps you through the process of taking a vhdl design, simulating it using NCLaunch, synthesizing it using Build Gates, re-simulating the gate-level netlist, and then performing auto place-and-route to achieve a finished ASIC. Pads can also be added to your design as shown in previous tutorials. Thus, the vhdl-to-ASIC work flow is illustrated. Also, a simple method to estimate power consumption will be explained towards the end.

You will perform this work based on the 0.5um AMI nwell process (lambda = 0.30um).

2. PREPARE THE CADENCE TOOLS From your home directory, change directories into your cadence working directory:

$ cd cadence

Make a directory for lab5 and change into that directory:

$ mkdir lab5

$ cd lab5

3. VHDL SIMULATION USING NCLAUNCH First, download the vhdl files you will use for this tutorial:

• mu0.vhd -- contains a vhdl description of the mu0 processor

(to learn more about mu0 processor visit http://www.ece.uah.edu/%7Elacasa/tutorials/mu0/mu0desc_files/frame.htm )

• tb_mu0.vhd -- testbench for mu0 component

Also make sure that you have “cds.lib” and “osu.lib” from the previous lab directory.

Now use the following the command to initialize the libraries

cp $CDK_DIR/cdssetup/cdsinit .cdsinit

Next, start NCLaunch in a terminal window at the unix prompt:

$ nclaunch -new

What is NCLaunch?

NCLaunch is a graphical user interface that helps you manage large design projects and lets you configure and launch your Cadence simulation tools.

VLSI Design I, Tutorial 5

NCLaunch is integrated into the Cadence Interleaved Native Compiled Architecture (INCA) and is a component of the SimVision analysis environment.

Want to learn more? Read the NCLaunch User Guide; it is intended for customers who want to simulate Verilog, VHDL, or mixed-language designs using the NCLaunch tool. This manual explains the complete functionality of the tool and gives examples of simulating with NCLaunch. In addition, it serves as a reference guide for finding specific details on using NCLaunch.

Select Multiple Step in the NCLaunch pop-up window:

The first step in the process of compiling the design units is to associate them with libraries.

Select Create cds.lib File… in the Open Design Window and then select Save:

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Select Include default libraries and press OK:

Press OK in the Open Design window and you should see:

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To perform compilation, you should first configure your compiler.

In Tools->VHDL Compiler, enable VHDL 93 features:

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Next, select the design units in the correct order (from the lowest design units to the top level units – i.e., select your testbench file last), and in the NCLaunch toolbar click on the VHDL compile icon (passing over the icon you will see the following text: 'Launch VHDL compiler with current settings'):

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The status should indicate the successful completion of the compilation process.

To perform Elaboration, expand worklib and the design units in it. Select the top level design unit (usually testbench, in our case tb_mu0) and select its entity:

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Click on the ‘Launch Elaborator with the current selection’ icon on the menu.

The status should indicate the successful completion of the elaboration phase.

For simulation, expand the Snapshots directory and select the testbench. Then, click on the Simulation icon on the menu to get the simulation environment loaded:

The SimVison console and Design Browser windows will appear:

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In the Design Browser window, select the top level entity:

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Select the signals you want to inspect:

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Click on the 'waveform' icon on the menu to bring up the waveform window. In the SimVison console, type run 10000 ns; as shown:

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Inspect the waveforms to ensure the design is working properly.

Other cool options:

Click on the 'schematic' icon on the menu to bring up the schematic tracer:

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4. VHDL SYNTHESIS TO GATE-LEVEL NETLIST

Once you know your design is working properly through simulation, you can synthesize your vhdl design into a gate-level netlist in a similar fashion as was done for the verilog design work flow.

1. Create an encounter directory and copy in the technology files (for AMI 0.5um):

$ mkdir encounter

$ cd encounter

$ cp /apps/iit_lib/osu/osu_stdcells/flow/ami05/* . $ cp /home/grad/wilderj/public_html/synopsys/* . (retrieves a script file and a library file) Now you have created the “encounter” folder and filled it with the template files for the AMI 0.5um technology. (identical to what was done in Tutorial 3) You will use the tool Synopsys Design Compiler for logic synthesis. The script file you’ll use with Synopsys is called “compile_dc.tcl”. This file is retrieved as shown above. Now you will open “compile_dc.tcl” in a text editor and modify it according to your accumulator design. This file is a script file for Synopsys and will be executed line by line. To make it easier to modify, all key values are defined in the beginning of the file.

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So the only modifications will be done in the header of the file. Specifically, you need to change the following four values: my_verilog_files ../mu0.vhd The RTL input file that we want to synthesize. my_toplevel_module mu0 The name of the top-level module in the RTL code. my_clock_pin clk The name of the clock pin in the RTL code. my_clock_freq_MHz 50 Tells PKS to optimize the circuit so that it is capable to

operate at least at 100 MHz.

Also look for the following line

analyze –f vhdl…..

And change it to

analyze –f verilog….

Since the Synopsys tool needs some initialization files that are installed in a different directory from your current working directory, you need to temporarily re-assign the OSUcells environment variable. This is done in the following way (at the unix prompt): $ export OSUcells=/apps/cadence2007/osu_soc_v27/synopsys Now everything should be set up to run the Synopsys synthesizer: $ /apps/synopsys/Z-2007.03-SP3/bin/dc_shell-t –f compile_dc.tcl Synopsys will run for a short time. When it is finished, it will return to the command line. Any errors that are generated can most likely be ignored. What you are interested in is the netlist file which Synopsys produces, called mu0.vh.

-mu0.vh file created (gate-level netlist)

-mu0.sdc file created (timing constraints file for encounter) Now, before moving on, we must reset the OSUcells environment variable: $ export OSUcells=/apps/iit_lib/osu/osu_stdcells

Modify encounter.conf and encounter.tcl files as below

$ nedit encounter.conf& In the encounter.conf file, edit the following line as shown: From: To: set my_toplevel MY_TOPLEVEL set my_toplevel mu0

In the encounter.tcl file, look for the command setIP0mode (there should be two instances of this command). Comment those lines with the ‘#’ symbol. You are now ready to perform automatic place and route by typing the following command:

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$ encounter -init encounter.tcl At the encounter 1 prompt in the terminal, type ‘win’ to take a look at the resulting layout

In Encounter, go to Design-> Report -> Summary. Use ‘text only’ format and give OK. Open the .rpt file and record the core size and chip size. Also record the slack time from the timing file generated.

Keep the encounter window open.

Power Analysis : There are two different power calculation methods: Static and Simulation based. In the static method, the probability of clock switching is given to the circuit and the power consumption of the chip is evaluated on that “guesstimate”. This method is not accurate and should not be used when an accurate estimate is desired.

The simulation-based method gives results that are more realistic. In this method, parasitic components of the circuit are extracted first, and then a file (SDF file) containing both gate information and RC parasitic information is created. Then this file will be simulated along with the Verilog netlist, which has been previously created by Encounter, combined with a carefully prepared testbench, which provides the switching information file. The result of this compilation is a VCD file, which will be given to Encounter to evaluate power consumption of the chip.

The testbench plays a critical role in the power evaluation process. In the testbench, the designer must provide all the possible switching conditions for the circuit (i.e., what are the operating cases of the circuit). This can be done by applying all the possible input/clock combinations for the system. In many cases, providing all the possible combinations will lead to a gigantic VCD file. To avoid a big VCD file, the designer should reduce the number of input/clock combinations by defining a representative number of input vectors in the testbench. The evaluated power will provide a reliable estimate of the true power consumption of the chip if stimulus vectors are used that represent the actual function of the chip. In this section, it is shown how to evaluate power consumption of a previously placed and routed digital chip.

You can use this power analysis tutorial for lab 4 too.

Now, in your encounter window, go to Design->Save Design -> SoCE Now go to Timing > Analysis Condition > Specify RC Extraction Mode. A window will pop up. Change the window to this:

Note : All the figures refer to lab4 instances which is ‘accu’. For lab5, this would be ‘mu0’

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Hit “OK” and go to Timing > Extract RC to see this menu pop up:

Hit “OK” again. Now RC parasitic of your design has been evaluated and you are ready to create the SDF file that contains your circuit along with the routing information and parasitic capacitances and resistances.

Go to Timing > Calculate Delay and you will see the following window:

Select a name for your SDF file. For instance, select “accu.sdf” and hit “OK”. You should also create the final netlist file. This file is created by the automatic command line place and route process but it you will save it here to a different name.

Go to Design > save > Netlist and the following window will pop up:

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In a terminal window, go to your encounter working directory and make sure that the files “accu.sdf” and “accu.v” are there. You should open “accu.v” using a text editor and add the following line at the beginning of the file: `timescale 1ns/10ps

`celldefine

and the following line at the end of the file: `endcelldefine

Make sure that the testbench.v file is downloaded before you proceed.

Now you are ready to simulate the verilog files. At the command line run the following to simulate the files: $ ncverilog accu.v testbench.v osu05_stdcells.v +access+r

Running the above command creates the VCD file “accu.vcd”. Now you are ready to go back to Encounter and evaluate the power consumption of the design.

In Encounter, which had been left open in the other terminal, go to Power > Power Analysis > Report power. Give a name for the output file and hit “OK”. Encounter will start analyzing the power of the chip and write the results in the output file.

The output file shows output information of the power analysis. Please take a while and read the file carefully. In the file there are three different power values:

Switching power, internal power and leakage power.

The first power indicates the power consumption of the chip due to the clock switching. The second power shows the cell’s internal power consumption (due to the “short-circuit” case mentioned in class), and the third power is the leakage power consumption of the circuit caused mainly by low threshold voltages. The average internal power dissipation has the most contribution in the chip’s power consumption because the circuit is dominated by flip-flops.

Assignment Based on your efforts of following the VHDL to synthesis to post layout design flow, turn in the following to the lab instructor:

• Functional verification output from simvision (15%)

• Core size, chip size of synthesized design (15%)

• Slack time of routed-design (10%)

• Power analysis report (60%)

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CPE/EE 427, CPE 527, VLSI Design I:

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