CpE 252

Computer Organization & Design

Basic Computer Organization & Design

Dr. T. Eldos 2

Basic Computer (BC) Organization and Design

Instruction Codes

Computer Registers

Computer Instructions

Timing and Control

Instruction Cycle

Memory Reference Instructions

Input-Output and Interrupt

Complete Computer Description

Design of Basic Computer

Design of Accumulator Logic

Dr. T. Eldos 3

Instruction Codes

Program A set of instructions that specify the operations, operands, and the

sequence by which processing has to occur.

Instruction Basic unit of computing, usually divided into operation code, operand,

address, addressing mode, etc.

Instruction Code Group of bits that tell the computer to perform a specific operation (a

sequence of micro-operations)

Basic Addressing Modes Immediate

Register

Memory Direct

Memory Indirect

Dr. T. Eldos 4

Simplest Organization

A processor with

Register to be used as default operand, Accumulator

Memory to hold code and data

Instruction code with two parts

An operation code that tells the processor what to do

An address part that tells the processor where the data is located, to

operate on it along with the register content

AddressOpcode

11 015 12

Binary Operand

15 0

Code and Data Formats

Processor Register; Accumulator (AC)

15 0

Programs

Operands

12-bit address

16-bit data

Dr. T. Eldos 5

Indirect Address

Effective Address (EA) is the address used to access:

An operand for a computation-type instruction, or

A target address for a branch-type instruction

Example

Direct: Address 457 points to the operand (126). EA=457

Indirect: Address 457 points to an address to the operand, it points to

1350, which is the address to the operand (438). EA = M[457]

Instruction Format Direct Address Indirect address

0 ADD 45722

126457

1 ADD 45735

1350457

4381350

I OP Address

Dr. T. Eldos 6

Basic Computer Registers & Memory

IR

TR

AC

DR

MEM

4096 x 16

AR

OUTR

INPR

PC

Reg. Size Name Function

AC 16 Accumulator Processor register

IR 16 Instruction Register Holds instruction code

TR 16 Temporary Register Holds temporary data

DR 16 Data Register Holds memory operand

AR 12 Address Register Holds memory address

PC 12 Program Counter Holds address to next instruction

INPR 8 Input Register Holds input character

OUTR 8 Output Register Holds output character

Dr. T. Eldos 7

Basic Computer with a Common Bus

MEM

DR

IR

TR

INPR

AR

PC

ALU

(Adder & Logic Unit)

OUTR

AC

BU

S M

UX

S2S1S0

E

Address

LDCLRINC CLK

LDCLRINC CLK

LDCLRINC CLK

LDCLRINC CLK

LDCLRINC CLK

LDCLRINC CLK

LD CLK

WE RD

1

2

3

4

5

7

6

IN OUT

INOUT

IN OUT

IN OUT

IN OUT

IN OUT

IN OUT

IN OUT

Dr. T. Eldos 8

BC Components

Memory

Input/Output

Processor

Datapath

ALU

Registers

General purpose like AC and TR

Special purpose like the others

BUS

Control

Clock signal to synchronize the data transfers of all the registers

Bus control signals S2 S1 S0

INC, CLR and LD of all registers

Memory RD and WE signals

Dr. T. Eldos 9

BC Instruction Formats

Non-memory-Reference Instructions; Opcode = 111

I = 0 means Register-Reference Instruction

I = 1 means Input-Output Instruction

Memory-Reference Instructions: Opcode 111

I = 0 means direct addressing

I = 1 means indirect addressing

Opcodes 000 ~ 110 stand for And, Add, Load, …

Memory Operand AddressOpcodeI

11 014 1215

Register Operation1 1 10

11 014 1215

I/O Operation1 1 11

11 014 1215

Dr. T. Eldos 10

MEM, REG and I/O Instructions

5 432 109876543210 Hex(I) Symbol Description

I 000 Mem. Address 0xxx/8xxx AND And memory word with AC

I 001 Mem. Address 1xxx/9xxx ADD Add memory word to AC

I 010 Mem. Address 2xxx/Axxx LDA Load AC from memory

I 011 Mem. Address 3xxx/Bxxx STA Store content of AC into memory

I 100 Mem. Address 4xxx/Cxxx BUN Branch Unconditionally

I 101 Mem. Address 5xxx/Dxxx BSA Branch and Save return Address

I 110 Mem. Address 6xxx/Fxxx ISZ Increment and Skip if Zero

0 111 100000000000 7800 CLA Clear AC

0 111 010000000000 7400 CLE Clear E

0 111 001000000000 7200 CMA Complement AC

0 111 000100000000 7100 CME Complement E

0 111 000010000000 7080 CIR Circulate Right AC and E

0 111 000001000000 7040 CIL Circulate Left AC and E

0 111 000000100000 7020 INC Increment AC

0 111 000000010000 7010 SPA Skip next instruction if AC is Positive

0 111 000000001000 7008 SNA Skip next instruction if AC is Negative

0 111 000000000100 7004 SZA Skip next instruction if AC is Zero

0 111 000000000010 7002 SZE Skip next instruction if E is Zero

0 111 000000000001 7001 HLT Halt computer

1 111 100000000000 F800 INP Input character to AC

1 111 010000000000 F400 OUT Output character from AC

1 111 001000000000 F200 SKI Skip on Input flag

1 111 000100000000 F100 SKO Skip on Output flag

1 111 000010000000 F080 ION Interrupt On

1 111 000001000000 F040 IOF Interrupt Off

Dr. T. Eldos 11

Instruction Set Completeness

Instruction set must provide for constructing programs to evaluate

any computable function

Instruction Types:

Functional Instructions; Arithmetic, Logic, and Shift instructions

ADD, CMA, INC, CIR, CIL, AND & CLA

Transfer Instructions; Register-memory data transfers

LDA & STA

Control Instructions; Program sequencing and control

BUN, BSA & ISZ

Input/Output Instructions; Input and output

INP and OUT

Dr. T. Eldos 12

Instruction Set: Missing Instructions

CMA is register-ref, while AND is memory-ref because it requires a second operand, which is always in memory

Missing instructions:

OR: DeMorgan's NOT & AND

SUB: CMP & ADD with E=1

MUL: ADD repeatedly

DIV: SUB repeatedly

DEC: CMA, INC & CMA

SHR: CIR with E=0

SHL: CIL with E=0

STE: CLE & CME

Example: DEC operation on a memory location content, x = (105)10

LDA: AC = (01101001)2

CMA: AC = (10010110)2

INC: AC = (10010111)2

CMA: AC = (01101000)2, AC = (104)10

Dr. T. Eldos 13

BC Timing & Control

Instruction Register (IR) 15 14 13 12 11 0

Instruction

Decoder7 0

Control Logic

I

Timing

Decoder

7 0

Sequence

Counter

INCCLRCLK

Other Inputs

Control Outputs

D0

D7

T15

T0

Dr. T. Eldos 14

Timing Signals

3-bit Sequence Counter (SC) and 3x8 decoder

SC incremented or cleared (synchronous with CLK)

Example: T0, T1, T2, T3, T4, T0, T1, . . .

Clear SC in T4 if D3, the RTL is D3T4: SC 0

CLK

SC CLR

T0

T1

T2

T3

T4

D3

T0 T1 T2 T3 T4 T0

Dr. T. Eldos 15

Instruction Cycle

Each instruction in the basic computer has 3 or 4 phases:

Instruction Fetch Phase; consumes 2 clock cycles (T0 and T1)

Instruction Decode Phase; consumes 1 clock cycle (T2)

Data Fetch Phase; consumes either 0 or 1 cycle

REG & I/O Instructions has no Data Fetch, so 0 cycles

MEM Instructions has Data Fetch, and consumes 1 Cycle (T3)

Instruction Execute Phase; consumes 1, 2 or 3 cycles

REG & I/O start execution in T3 and completes at the end of T3

MEM instructions fetches data in T3, and starts execution in T4; then

Some finish in T4, like STA

Some finish in T5, like AND

Some finish in T6, like ISZ

Dr. T. Eldos 16

Instruction Cycle Length

Fetch Cycles

Decode CyclesData Fetch Cycles (Memory-Reference; NOP if direct)

Execute Cycles

CLK

T0 T1 T2 T3

All REG & I/O

CLK

T0 T1 T2 T3 T4 T5

AND, ADD, LDA & BSA

CLK

T0 T1 T2 T3 T4

STA & BUN

CLK

T0 T1 T2 T3 T4 T5 T6

ISZ

T0 T1

T0 T1

T0 T1

T0 T1

Instruction Cycle

Instruction Cycle

Instruction Cycle

Instruction Cycle

T2

T2

T2

T2

Dr. T. Eldos 17

Instruction Fetch & Decode

Instruction Fetch Phase

T0: AR PC (S2S1S0=010, AR_LD=1)

T1: IR M [AR], PC PC + 1 (S2S1S0=111, IR_LD=1, PC_INC=1)

Instruction Decode Phase

T2: D0, . . . , D7 Decode IR(14-12), AR IR(11-0), I IR(15)

[Operand Fetch &] Execute Phase

T3, T4, T5 and T6

Two types of instructions

REG & I/O: No data fetch, execute in T3 and finish

MEM execute: Data fetch in T3, execute in T4, T4 & T5, or T4 & T5 & T6

Simply,

T0 causes MUX S’s to select PC and AR to LD

T1 causes MUX S’s to select MEM, IR to LD and PC to INC

So:

S1 is set if T0 or T1 or … (to come later …)

S0 is set if only T1

Dr. T. Eldos 18

Instruction Fetch Controls

MEM

IR

AR

PC

BUS

S0

S1

S2

Address

LDCLRINC CLK

LDCLRINC CLK

LDCLRINC CLK

WE RD

1

2

5

7

IN OUT

IN OUT

IN OUT

T1

T0

Dr. T. Eldos 19

Operand Fetch & Execute Paths

Based on the instruction type, one of four paths will be selected in T3,

Register instructions Identified when D7I’T3=1

Start execution at T3

I/O instructions

Identified when D7IT3=1

Start execution at T3

Memory direct Identified when D’7I’T3=1

Do NOTHING in T3 start execution in T4

Memory indirect Identified when D’7IT3=1

AR M[AR] in T3 and start execution in T4

So, register and input-output instructions execute in T3, while memory instructions fetch data in T3 and start execution in T4

Dr. T. Eldos 20

Instruction Phases & Timing

T3

I/O Instruction

SC 0

REG Instruction

SC 0

SC 0

AR PC

IR M[AR], PC PC+1

Di’s DEC IR(12-14),

AR IR(11-0), I IR(15)

D7 ?

I ?

MEM Instruction

SC 0

I ?

AR M[AR] NOP

0 1

0 10 1

T0

T1

T2

T4 orT4 & T5 orT4, T5 & T6

T3 T3

T3

Instruction Execute

Data Fetch

Instruction Decode

Instruction Fetch

Dr. T. Eldos 21

Register Reference Instructions

Identified when D7=1 & I=0, operation specified in IR(11-0)

Execution starts with timing signal T3

Let r = D7I’T3 and Bi = IR(i) , i = 11, 10, 9, …, 0

Instruction Condition Operation

- - - r: SC 0 ; clear at the end of T3

CLA rB11: AC 0CLE rB10: E 0CMA rB9: AC AC’CME rB8: E E’CIR rB7: AC shr AC, AC(15) E, E AC(0)CIL rB6: AC shl AC, AC(0) E, E AC(15)INC rB5: AC AC + 1SPA rB4: if (AC(15) = 0) then (PC PC+1)SNA rB3: if (AC(15) = 1) then (PC PC+1)SZA rB2: if (AC = 0) then (PC PC+1)SZE rB1: if (E = 0) then (PC PC+1)HLT rB0: S 0 ; S is a start-stop flip-flop

Dr. T. Eldos 22

Memory Reference Instructions

Effective Address in AR if T2I’ or T3I

So, by end of T3 AR points to the operand in memory

Memory assumed fast enough to complete reading or writing in 1

cycle

Memory reference instructions start with T4

Instruction Opcode OperationCondition

AND D0 AC AC M[AR]ADD D1 AC AC + M[AR], E Cout

LDA D2 AC M[AR]STA D3 M[AR] ACBUN D4 PC ARBSA D5 M[AR] PC, PC AR + 1ISZ D6 M[AR] M[AR] + 1, M[AR]+1=0: PC PC+1

Dr. T. Eldos 23

Memory Reference Instructions Details

Instruction Condition Microoperations

AND D0T4: DR M[AR]

D0T5: AC AC DR, SC 0

ADD D1T4: DR M[AR]

D1T5: AC AC + DR, E Cout, SC 0

LDA D2T4: DR M[AR]

D2T5: AC DR, SC 0

STA D3T4: M[AR] AC, SC 0

BUN D4T4: PC AR, SC 0

BSA D5T4: M[AR] PC, AR AR + 1

D5T5: PC AR, SC 0

ISZ D6T4: DR M[AR]

D6T5: DR DR + 1

D6T6: M[AR] DR, DR=0: PC PC + 1, SC 0

Dr. T. Eldos 24

Branch After Saving Address (BSA)

Call subroutine at address 135 while executing at address 20

Return address, which is 21 is saved to location 135

Transfer execution to the next location, i.e. 136

At the end, an indirect unconditional branch is to the beginning,

which is 135, i.e. to where it finds the return address, which is 21

Memory, PC after execution

21

0 BSA 135

Next instruction

Subroutine

20

PC = 21

AR = 135

136

1 BUN 135

Memory, PC, AR at time T4

0 BSA 135

Next instruction

Subroutine

20

21

135

PC = 136

1 BUN 135

Dr. T. Eldos 25

Memory-Reference Instructions - Execution

DRM[AR] DRM[AR] DRM[AR] M[AR]PC,

ARAR+1

AND ADD LDA BSA

PC AR

SC 0

DRM[AR]

M[AR] AC,

SC 0

STA BUNISZ

ACACDR,

SC0

ACAC+DR,

ECout, SC0

ACDR,

SC0

PCAR,

SC0

DRDR+1

M[AR]DR,

DR=0: PCPC+1,

SC0

T4

T6

T5

D0 D3 D1 D4 D5D6 D2

Dr. T. Eldos 26

Input/Output and Interrupt

Line Style

Thick are Parallel

Thin are Serial

Dashed are control

Line Color

Blue from BUS

Red to ALU

FGI and FGO modified by both

the control unit and the external

devices

Transmitter Interface

OUTR

AC(H) AC(L)

INPR

Receiver Interface

FGO

FGI

Co

mp

ute

r R

eg

iste

rs

&

Inp

ut-

Ou

tpu

t F

lag

s

Dr. T. Eldos 27

Input-Output Configuration

The keyboard sends and receives serial information

The serial information from the keyboard is shifted into INPR

The serial information for the printer is stored in the OUTR

INPR and OUTR communicate with the computer in parallel and

with the outside serially

The flags are needed to synchronize the timing difference between

I/O device and the computer

INPR Input register - 8 bits

OUTR Output register - 8 bits

FGI Input flag - 1 bit

FGO Output flag - 1 bit

IEN Interrupt enable - 1 bit

Dr. T. Eldos 28

I/O Reference Instructions

I/O Instructions identified when D7=1 and I=1

I/O Instruction is specified in B11 ~ B6 of IR

Execution starts with timing signal T3

I/O instructions include flags control and interrupt control

p = D7IT3 and Bi = IR(i) , i = 11, 10, 9, …, 6

Instruction Condition Microoperations

INP pB11: AC(0-7) INPR, FGI 0

OUT pB10: OUTR AC(0-7), FGO 0

SKI pB9: FGI=1: PC PC+1

SKO pB8: FGO=1: PC PC+1

ION pB7: IEN 1

IOF pB6: IEN 0

Dr. T. Eldos 29

CPU and I/O Device Interactions

Can get input only if FGI=1 and can send output only if FGO=1

This explains the initial condition of FGI and FGO

FGI=0

Initially FGI = 0

AC INPR

FGI 0

More ?

STOP

START

Yes

Yes

No

NoINP

FGO=0

Initially FGO = 1

OUTR AC

FGO 0

More ?

STOP

START

Yes

Yes

No

NoOUT

Dr. T. Eldos 30

Program-Controlled Input/Output

CPU continuously involved

CPU slowed down to I/O speed, wasting much of its time

Simple and little hardware

Input

WAIT: SKI

BUN WAIT

INP

STA BUFOutput

LDA BUF

WAIT: SKO

BUN WAIT

OUT

Dr. T. Eldos 31

Interrupt-Initiated Input/Output

Open communication only when some data has to be passed,

through interrupt.

The I/O interface, instead of the CPU, monitors the I/O device

When the interface finds that the I/O device is ready for data transfer,

it generates an interrupt request to the CPU

Upon detecting an interrupt, the CPU stops momentarily the task it is

doing, branches to the service routine to process the data transfer,

and then returns

IEN is an interrupt-enable flip-flop that can be set and cleared by

instructions

Dr. T. Eldos 32

CPU and I/O Device Interactions

IEN

FGI

=1

SET R

R ?

FGO

M[0] PC

Save Return Address

Fetch & Decode

Instruction

=0

R 0, IEN 0

Reset R & IEN

PC 001

Branch to Location 1

=1

=0

=1

=1

=0

=0

Exe

cu

te In

stru

ctio

n

Dr. T. Eldos 33

Interrupt Cycle & Instruction Cycle

The computer has two cycles:

Instruction cycle; the normal instruction execution behavior

Interrupt cycle, deviation from the normal coarse of action

The interrupt cycle is a hardware implementation of a branch and

save return address operation

If interrupt is enabled (IEN=1) and at least one of the flags is set

(FGO=1 or FGI=1), then:

Current PC is saved to memory location 0

Control is transferred to location 1 (where a branch instruction to the

interrupt service routine is stored)

At the end of the interrupt service routine, an Indirect unconditional

branch to location 0 is executed, to take us back to the takeoff point

Dr. T. Eldos 34

Interrupt Cycle & Instruction Cycle

Register Transfer Statements for Interrupt Cycle

IEN(FGI+FGO)(T’0T’1T’2): R 1

Necessary to update R only after decoding, to avoid executing

microoperations from both sides (instruction and interrupt cycle)

The fetch and decode phases of the instruction cycle must be

modified

The T0, T1 and T2 conditions must be ANDed with R, to become R’T0, R’T1 and R’T2

The interrupt cycle :

RT0: AR 0, TR PC

RT1: M[AR] TR, PC 0

RT2: PC PC + 1, IEN 0, R 0, SC 0

We can only INC, LD or CLR the PC, we CLR then INC to perform

PC 1

Dr. T. Eldos 35

Complete Computer Description

I/O Instruction

SC 0

REG Instruction

SC 0

SC 0 , IEN 0, R 0

AR PC

AR M[AR], PC PC+1

Di’s DEC IR(14-12),

AR IR(11-0), I IR(15)

D7 ?

I ?

MEM Instruction

SC 0

I ?

AR M[AR] NOP

0 1

0 10 1

R’T0

R’T1

R’T2

T3

T4 orT4 & T5 orT4 & T5 & T6

T3 T3

T3

R ?1 0

AR 0, TR PC

M[AR] TR, PC 0

PC PC+1,

IEN 0, SC 0, R 0

RT0

RT1

RT2 IEN

(FG

I+F

GO

): R

1

Dr. T. Eldos 36

Complete Computer Description – Part 1Instruction Fetch, Instruction Decode & Data Fetch

Interrupt Instruction Cycle, Let T0’T1’T2’ = x & IEN(FGI+FGO) = INT

x INT: R 1

RT0: AR 0, TR PC

RT1: M[AR] TR, PC 0

RT2: PC PC + 1, IEN 0, R 0, SC 0

Ordinary Cycle

Fetch R’T0: AR PC

R’T1: IR M[AR], PC PC + 1

Decode R’T2: D0 ~D7 DEC IR(14-12), AR IR(11-0), I IR(15)

Indirect D’7IT3: AR M[AR]

Dr. T. Eldos 37

Complete Computer Description – Part 2Memory-Reference Instruction Execution

AND D0T4: DR M[AR]

D0T5: AC AC . DR, SC 0

ADD D1T4: DR M[AR]

D1T5: AC AC + DR, E Cout, SC 0

LDA D2T4: DR M[AR]

D2T5: AC DR, SC 0

STA D3T4: M[AR] AC, SC 0

BUN D4T4: PC AR, SC 0

BSA D5T4: M[AR] PC, AR AR + 1

PC AR, SC 0

ISZ D6T4: DR M[AR]

D6T5: DR DR + 1

D6T6: M[AR] DR, DR=0: PC PC + 1, SC 0

Dr. T. Eldos 38

Complete Computer Description – Part 3

Register Reference execution, Let D7I’T3=r and IR(i)=Bi, i = 0, 1, 2, ..., 11

r: SC 0

CLA rB11: AC 0

CLE rB10: E 0

CMA rB9: AC AC’

CME rB8: E E’

CIR rB7: AC shr AC, AC(15) E, E AC(0)

CIL rB6; AC shl AC, AC(0) E, E AC(15)

INC rB5: AC AC + 1

SPA rB4: AC(15) =0: PC PC + 1

SNA rB3: AC(15) =1: PC PC + 1

SZA rB2: AC = 0: PC PC + 1

SZE rB1: E = 0: PC PC + 1

HLT rB0: S 0

Input/Output Reference: Execution, Let D7IT3=p and IR(i)=Bi, i = 6, 7, 8, 9, 10, 11

p: SC 0

INP pB11: AC(0-7) INPR, FGI 0

OUT pB10: OUTR AC(0-7), FGO 0

SKI pB9: FGI =1: PC PC + 1

SKO pB8; FGO =1: PC PC + 1

ION pB7: IEN 1

IOF pB6: IEN 0

Dr. T. Eldos 39

Design of Basic Computer (BC)

Hardware Components of BC

A memory unit: 4096 x 16

Registers: AR, PC, DR, AC, IR, TR, OUTR, INPR, and SC

Flip-Flops (Status): I, S, E, R, IEN, FGI, and FGO

Decoders a 3x8 Opcode decoder and a 3x8 timing decoder

Common bus: 16 bits

Adder/Logic Unit

Control Logic Gates

Registers Controls

Read and Write Controls of Memory

Set, Clear, or Complement Controls of the flip-flops

S2, S1, S0 Controls to select a register for the bus

Adder/Logic Unit Controls

Dr. T. Eldos 40

Register Control

To find the controls of AR, scan all of the register transfer

statements that change the content of AR.

Below is a list of them

R’T0: AR PC LD AR

R’T2: AR IR(11-0) LD AR

D’7 I T3: AR M[AR] LD AR

RT0: AR 0 CLR AR

D5T4: AR AR + 1 INC AR

In terms of each input, they are:

AR_LD = R’T0 + R’T2 + D’7IT3

AR_CLR = RT0

AR_INC = D5T4

Controls of the rest (registers, memory, status and other flip flops)

follow the same rule

To see how easy, the LD of TR is simply the condition R T0

Dr. T. Eldos 41

Address Register Control Logic

T4

AR

LDCLRINC CLK

BUS BUS

D5

T0

R

T2

I

T3

D7

CLK

Dr. T. Eldos 42

MEM WE Logic

R

OPCode

Instruction Decoder

D0

Counter

Timing Decoder

T0

Memory

WE

Memory Write Statements

RT1: M[AR]TR

D3T4: M[AR]AC

D4T4: M[AR]PC

D6T6: M[AR]DR

Dr. T. Eldos 43

Flag Control and Flag Control Logic

To find the controls of Interrupt Flip-Flop, IEN, scan all of the

register transfer statements that change the content of IEN. In terms

of p = D7IT3, they are

pB7: IEN 1 from I/O Instruction

pB6: IEN 0 from I/O Instruction

RT2: IEN 0 from interrupt

So, J=pB7 and K=pB6 + RT2

IEN

J Q

K

B6

B7

RT2

I

T3

D7

CLK

IEN

p

Dr. T. Eldos 44

Bus Controls

Scan the statements that cause the bus to be loaded by registers or

memory

AR as an example has the following effect on the bus

D4T4: PC AR

D5T5: PC AR

Then x1 = D4T4 + D5T5

Do the rest x2, x3, …, x7

x1

x2

x3

x4

x5

x6

x7

Encoder

S2

S1

S0

Bus Multiplexer Select Lines

x1 x2 x3 x4 x5 x6 x7 S2 S1 S0 Register

0 0 0 0 0 0 0 0 0 0 none1 0 0 0 0 0 0 0 0 1 AR0 1 0 0 0 0 0 0 1 0 PC0 0 1 0 0 0 0 0 1 1 DR0 0 0 1 0 0 0 1 0 0 AC0 0 0 0 1 0 0 1 0 1 IR0 0 0 0 0 1 0 1 1 0 TR0 0 0 0 0 0 1 1 1 1 MEM

Do we really

do this?

Dr. T. Eldos 45

Encode-Decode: is this how we do it?

X0 X2 X4X1 X3 X5 X6 X7

A

B

C

AR0

PC0

DR0

AC0

IR0

TR0

MEM0

BUS0

None

Dr. T. Eldos 46

X0 X2 X4X1 X3 X5 X6 X7

A0

B0

C0

D0

E0

F0

G0

H0

BUS0

Not really !

Dr. T. Eldos 47

Register Control: The Accumulator

Condition MicrooperationD0T5: AC AC DRD1T5: AC AC + DRD2T5: AC DRpB11: AC(0-7) INPRrB9: AC AC’rB7 : AC shr AC, AC(15) ErB6 : AC shl AC, AC(0) ErB11 : AC 0rB5 : AC AC + 1

Note: r = D7I’T3

AC

LDCLRINC CLK

ALU BUS

B5

B11

B9

B6

B7

p

T5

D0

D1

D2

B11

CLK

AND

ADD

DR

INPR

CMA

CIR

CIL

CLA

INC

ALU Controls

T3

D7

rI’

Dr. T. Eldos 48

Adder Logic Circuit: 1 bit path

AND

CLK

LD

DR

CMA

ADD

INPR

CIL

CIR

ACi

Q

AC1+1

J Q

AC1-1

Q

DRi

D Q

FAB

S CiCi+1

A

From INPR

From DR

From AC

ALU Controls

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