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Course Topics - Outline

Lecture 1 - Introduction Lecture 2 - Lexical conventions Lecture 3 - Data types Lecture 4 - Operators Lecture 5 - Behavioral modeling A Lecture 6 – Behavioral modeling B Lecture 7 – Behavioral modeling C Lecture 8 – Data flow modeling Lecture 9 – Gate Level modeling Lecture 10 – Tasks and Functions Lecture 11 – Advanced Modeling Techniques Lecture 12 - Coding Styles and Test Benches Lecture 13 - Switch Level modeling

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Lecture 13 - Switch Level modeling

Introduction Switch-Modeling Elements MOS Switches CMOS Switches Bidirectional Switches Delay Specifications Power and Ground Signal Strengths Resistive Switches trireg net Capacitive networks Exercise 13

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How to describe a switch-level circuit?

In rare cases, circuit designer engineers are asked to design the leaf-level modules, using transistors.

Verilog provides the ability to design digital circuits only at a MOS-transistor level, i.e., transistors function as switches – either conduct or are open.

Logic levels 0, 1, X, Z are supported and the drive strength associated with them.

Introduction

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Switch primitives

Ideal switches – without a prefixed letter “r” Resistive switches – with a prefixed letter “r”

● Resistive switches rnmos rpmos rcmos

● MOS switches nmos pmos cmos

● Resistive Bidirectional switches rtran rtranif0 rtranif1

● Bidirectional switches tran tranif0 tranif1

● Power and ground nets supply1 supply0

● Pullup and pulldown pullup pulldown

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NMOS and PMOS Switches

● NMOS & PMOS switches are declared with keywords nmos & pmos

Switch elements Instantiation Format: switch_name [instance_name] (output, input, control) ; // instance_name is optional (drain, source, gate)

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CMOS Switch

CMOS switches are declared with the keyword cmos.

A CMOS device can be modeled with an nmos and a pmos devices.

cmos switch instantiation format: cmos [instance_name](output,input,ncontrol,pcontrol) ;

Instance name is optional

// no instance name given

cmos(output ,input, ncontrol, pcontrol) ;

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CMOS Switch cont.

ncontrol and pcontrol are normally complements of each other. When the ncontrol signal is 1 and pcontrol signal is 0, the switch conducts. If ncontrol is 0 and pcontrol is 1, the output of the switch is high impedance value.

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Example – CMOS Inverter

module my_not (input x, output f) ; // internal declaration supply1 vdd ; supply0 gnd ; pmos p1 (f, vdd, x) ; // NOT gate body nmos n1 (f, gnd, x) ; endmodule

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Example – CMOS 2-to-1 Multiplexer

module my_mux (out, s, i0, i1); output out ; input s, i0, i1 ; wire sbar ; //internal wire not (sbar, s) ; //instantiate cmos switches // (out,in,ncontrol,pcontrol) cmos (out, i0, sbar, s) ; cmos (out, i1, s, sbar) ; endmodule

sbar

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Example - CMOS NAND Gate

module my_nand (input x, y, output f) ; supply1 vdd ; supply0 gnd ; wire a ; // NAND gate body pmos p1 (f, vdd, x) ; pmos p2 (f, vdd, y) ; nmos n1 (f, a, x) ; nmos n2(a, gnd, y) ; endmodule

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Example - Pseudo NMOS NOR Gate

module my_pseudo_nor(input x, y, output f) ;

supply0 gnd ;

// Pseudo nMOS gate body

nmos nx (f, gnd, x) ;

nmos ny (f, gnd, y) ;

pullup (f) ;

endmodule

f

Pseudo : using pullup resistor instead of 2 serial-connected pmos gates

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Bidirectional switches

nmos, pmos and cmos gates conduct from drain to source.

It is important to have devices that conduct in both directions.

In such cases, signals on either side of the device can be the driver signal.

Bidirectional switches are provided for this purpose.

Three keywords are used to define bidirectional switches: tran, tranif0, and tranifl.

Symbols for these switches and their instantiation formats are shown in the following slide:

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Bidirectional switches – cont.

Bidirectional switches instantiation: tran [instance_name] (inout1, inout2) ; tranif0 [instance_name] (inout1, inout2, control) ; tranif1 [instance_name] (inout1, inout2, control) ; ● instance_name is optional

inout2

inout2 inout2

inout1

inout1 inout1

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Bidirectional switches – cont.

tran switch acts as a buffer between the two signals inoutl and inout2. Either inoutl or inout2 can be the driver signal.

tranif0 switch connects the two signals inoutl and inout2 only if the control signal is logical 0. If the control signal is a logical 1, the non-driver signal gets a high impedance value Z. The driver signal retains value from its driver.

tranif1 switch conducts if the control signal is a logical 1.

Example: 2:1 mux modeled by tranif’s tranif0 UpperTran(out, in1, sel) ; tranif1 LowerTran(out, in2, sel) ;

out sel

in1

in2

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Delay Specifications - MOS/CMOS Switches

Specify no delay:

n,p,cmos [instance_name](output, input, …) ;

Specify propagation delay only:

n,p,cmos #(prop_delay)[instance_name](output, input, …) ;

Specify both rise and fall times:

n,p,cmos #(rise,fall)[instance_name](output, input, …) ;

Specify rise, fall, and turn-off times:

n,p,cmos #(rise,fall,off)[instance_name](output, input, …) ;

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Delay Specifications - Bidirectional Switches

Specify no delay

bdsw_name [instance name](in,out,control) ;

Specify a turn-on and turn-off delay

bdsw_name #(t_on_off)[instance name](in,out,control) ;

Specify separately turn-on and turn-off delays

bdsw_name #(t_on, t_off)[instance name](in,out,control) ;

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Power and Ground

The power (Vdd, logic 1) and Ground (Vss, logic 0) sources are needed when transistor-level circuits are designed.

Power and Ground sources are defined with keywords supply1 and supply0.

supply1 and supply0 place logical 1 and 0 continuously on nets throughout the simulation. Supply1 vdd ; supply0 gnd ; assign a = vdd ; // connect a to vdd – voltage source assign b = gnd ; // connect b to gnd - ground

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Signal Strengths

Signal strength can be weakened or attenuated by the resistance of the wires.

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Resistive Switches

nmos, pmos, cmos and bidirectional switches can be modeled as resistive devices.

Resistive switches have higher source-to-drain impedance than regular switches and reduce the strength of signals passing through them.

Resistive switches are declared with keywords having an “r” prefixed to the corresponding regular switch keyword.

Resistive switches have the same syntax as regular switches. rnmos rpmos // resistive nmos and pmos switches rcmos // resistive cmos switch rtran rtranif0 rtranif1 // resistive bidirectional switches

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Single Strength Reduction

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trireg net

trireg net stores a value. Used to model charge storage nodes. A trireg can be one of two states:

- The Driven State When at least one driver of a trireg has a value of 1, 0, or x, that value propagates into the trireg and is the trireg’s driven value. - Capacitive State When all the drivers of a trireg net are at the high impedance state (z), the trireg net retains its last driven value; the high impedance value does not propagate from the driver to the trireg. The strength of the value on the trireg net in the capacitive

state is small, medium, or large, depending on the size specified in the declaration of the trireg.

The strength of a trireg in the driven state is strong, pull, or weak depending on the strength of the driver.

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trireg net – cont.

● trireg net, stores a value unlike regular net.

● If the trireg net is not driven, then it has charge strength. Otherwise it has the strength of its driver.

trireg syntax: trireg <charge_strength>? <delay>? <list_of_variables> ; Example: // a charge storage node of strength small trireg (small) #(3, 3, 10) storeit ;

trireg net declaration: trireg strength range delays list_of_identifiers = expression ;

Driving net declaration:

<nettype><drive_strength>?<delay>?<list_of_assingments>;

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Capacitive network with trireg nets

Driven state Capacitive state An example of trireg net At simulation time 0 a, b, and c = 1 x = 0 y -> 0 z -> driven state and = strong0

At simulation time 10 b = 0 y -> a high-impedance /* The HiZ value does not

propagate from wire y into trireg z */ z -> capacitive state and = medium0

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Verilog Coding Style

Use meaningful names for signals and variables. Don't mix level and edge sensitive in one always block. Avoid mixing positive and negative edge-triggered flip-flops. Use parentheses to optimize logic structure. Use continuous assign statements for simple combo logic. Use non-blocking for sequential and blocking for combo logic Don't mix blocking and non-blocking assignments in one

always block. Be careful with multiple assignments to the same variable. Always thinks about design reuse: Files 200-300 lines max. Parameters. Add comments as often as you can. Write readable code.

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Exercise 13

Part1: Design CMOS NOR Gate. Use 2 nmos and 2 pmos gates. Don’t forget to connect power and ground. Test and verify Gate functionality

Part2: Design 1Bit Full Adder Design. Use my_not module CMOS inverter from lecture. Design my_xor module.

Add the inverters and CMOS gates. Test & Verify design.

Part3: Design D Latch. Reuse the my_not module. Add the inverters and CMOS gates. Test & Verify design.

Part4: Design CMOS D-Flip-Flop built from 2 consecutive Master-Slave D Latches. Test & Verify design.