Course Summary - ANUcourses.cecs.anu.edu.au/courses/ENGN3213/lectures/... · 3213: Digital Systems...
Transcript of Course Summary - ANUcourses.cecs.anu.edu.au/courses/ENGN3213/lectures/... · 3213: Digital Systems...
1. Course overview 2. Intro to PICOBLAZE, C and Number systems and Boolean Algebra 3. Course overview with microprocessor MU0 (I) 4. Course overview with microprocessor MU0 (II) 5. Verilog HDL 6. Digital system components using schematics and Verilog 7. Combinational logic standard forms. Karnaugh maps 8. Combinational ccts and configurable logic devices 9. Simple Sequential circuits, flip flops10. Sequential circuits, counters, registers, memories11. Nonideal effects in digital circuits12. Finite State Machines13. Design of FSMs14. Register Transfer Level Systems (RTL) systems15. Design of RTL Systems16. Nonideal effects in complex digital systems (Karnaugh maps)17. Complex RTL design18. The PICOBLAZE Softcore19. Assembly language programming20. C and Assembly21. Other microprocessor architectures
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Course Summary
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Controllers The state description is primary
FSM producing control signals
Control signals determine actions performed in other parts of the system
Autonomous Controller: fixed sequence of states independent of inputs
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RTL approach Digital system divided into Data and Control subsystems.
The state of a system consists of the contents of its registers.
Functioning of system performed in a sequence of register
transfers synchronous to the clock.
The register transfer is a transformation performed on a datum while the datum is transferred from one register to another.
The sequencing of the register transfers is controlled by the control subsystem
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Sequential Execution Graphs
Unfolded
Loop
Only one node can be executed at a time
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Group Sequential Execution Graph In group sequential execution graphs each group can start when the preceding has been executed
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Transfer Concurrent into Sequential Execution Graph Any concurrent execution graph can be converted into an equivalent sequential graph by sequencing of the concurrent nodes
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Digital Systems using RTL Approach Microprocessors
MU0 PICOBLAZE RP calculator
Navigation systems Image processing systems Telecommunications
Routers, switches Modems Radios
Settop boxes, cellphones, GPS receivers,...
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A Radio Receiver “Design a radio receiver to communicate digital data” (ignore analog and other performance specs)
Modulation scheme based on Binary Phase Shift Keying (BPSK) – but issues with carrier offsets
Instead use Differential Binary Phase Shift Keying (DBPSK or simply DPSK)
DBPSK used in IEEE802.11b (WiFi). Also adopt Barker code to do autocorrelation for timing extraction. However 802.11b based on Direct Sequence Spread Spectrum
(DSSS)
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Receive signals via analog RF Front End
Radios consist of analog front ends and digital baseband processors
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Mathematics of Demodulation Radiowave propagates from a transmitter to a receiver on a modulated sinusoidal carrier
Signal = A exp jωC t + φ
Mixers multiply the signal by a local oscillator sine wave with quadrature components, producing a low pass filtered baseband signal
I = A cos Ωt + φ Q = A sin Ωt + φ
note Ω = ωC− ωLO the carrier offset
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How do BPSK and DPSK work?
Only modulate φ and ignore A.
BPSK A digital 1 = 0o phase shift A digital 0 = π phase shift
DBPSK A digital 1 = Change phase by π A digital 0 = No phase change
But Ω the carrier offset causes an error
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BPSK and DBPSK
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Wireless Impairments Crucial... Carrier offset, Ω (Differential coding) Symbol timing synchronisation (Timing recovery FSM) Data extraction
As in IEEE802.11b we ignore.. Random noise (Error coding) Intersymbol interference (Equalisation)
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BPSK No Carrier Offset: I,Q look like...
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BPSK with Carrier Offset: I/Q look like...
Carrier offset flips the bit every phase change!!
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DBPSK No Carrier Offset
Data: 1 1 1 1 1 1 1 1 1
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DBPSK With Carrier Offset
Data: 1 1 1 1 1 1 1 1 1
Small Carrier offset harmless if the intersymbol phase difference unaffected
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Datapath
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ADC Interface (like KBD and Button Interfaces) Roles of ADC Interface
Handle the ADC sampling protocol / oversample at Ns times symbol rate Provide I and Q 16 bit streams valid at posedge SysClk Provide a measure of the minimum acceptable signal strength (Received signal strength indicator, RSSI)
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Finite Input Response Filter
Filtering reduces the occupied bandwidth to the minimum possible (Nyqiust => 1/(2TS) Best filtering is matched filtering where the filter impulse response is the same as the time reversed symbol pulse shape (autocorrelation) However practical considerations affect the actual implementation
Filtering involves convolution
Where x(k) is the input sequence, b(k) are the filter tap weightsand y(k) is the output
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Finite Input Response Filter (Tapped Delay Line)
16 bit D flipflop
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Simple FIR involves multiplicationOne solution: Use Cascaded Integrator Comb filters
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Demodulation of DBPSK Oversampled I and Q samples: I(k) Q(k) Oversampling rate Ns per symbol Use the inner product (dot product)
Z(k) = I(k) I(k+Ns) + Q(k) Q(k+Ns)
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Inner product implementation
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Early late Algorithm: apply to inner product, Z(k)Pilots Barker
If Z(k) > 0 and Z(k) > Z(k1), Z(k+1)then data bit = 1 for kth sample
If Z(k) < 0 for Ns samples then data bit = 0
After detecting a 1 jump Ns/2 samples
Z(k)
Samples
, 0
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Early late FSM
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Extraction of Information Bits Use the barker bit sequence to find the first info bit
= [1, 1, 1, −1, −1, −1, 1, −1, −1, 1, −1]
Could use pattern matching as in the Morse code translator – but data is corrupted by noise – one wrong Barker bit and the pattern matcher will fail
As in IEEE802.11b use autocorrelation to minimise effect of noise. AutoCorr(k) = barker * d(k),d(k1),...,d(k10)
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Autocorrelation
Crosscorrelation similar to convolution
Where x(k) is the input sequence, b(k) is the Barker sequenceand y(k) is the output
The first info bit is the one located right after the Barker sequence and the input sequence is aligned with the Barker sequence at the maximum of the crosscorrelation
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DBPSK RTL Design
PICOBLAZE...yet another RTL system
PicoBlaze 8bit Embedded Microcontroller User Guide
for SpartanII, ...FPGAs
(XAPP213.pdf on the web)
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PICOBLAZE KCPSM
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PICOBLAZE KCPSM ARCHITECTURE
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PICOBLAZE KCPSM• Soft Core Processor
– Not behavioral VHDL – manually precompiled
• Built by instantiation of Xilinx raw primitives – still easily simulated
with Modelsim
• Size is most important emphasis
– Only 96 Slices – consider that your XC3S500E “cheap” FPGA
has 4656 slices!
• Primary Uses
– Take the place of a complex state machine
• Some tasks seem more naturally suited to sequential software
• Changing software will be faster than changing VHDL
– Could handle some data processing
• Simple external interface
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PICOBLAZE KCPSM
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PICOBLAZE KCPSM,2,3
• Kcoded programmable state machine
• “State machine based on constants” in
several ways
– Constant data values for ALU
– Constant port addresses
– Constant instruction addresses
• Written by Ken Chapman
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Some features
All instructions take 2 clock cycles
• Programs maximum 1024 instructions in Spartan III
– Clearly designed so program memory could fit
in 1 BRAM (1kx18) (265x16 in SPARTAN II)
– Dictated by size of block ram, and size of
address field in opcode structure
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Block diagram of a SinglePurpose Processor (FSMD – Finite State Machine with Datapath)
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Block diagram of a GeneralPurpose Processor (Microcontroller)
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MU0
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PICOBLAZE KCPSM ARCHITECTURE
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PICOBLAZE KCPSM3
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PicoBlaze Programming Model
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How to use...
Assembly code
KCPSM MACROVHDL
KCPSM.exe >ROM
ISE designflow
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Instructions
Logical Group
LOAD sX,kk
AND sX,kk
OR sX,kk
XOR sX,kk
LOAD sX,sY
AND sX,sY
OR sX,sY
XOR sX,sY
I
Shift and Rotate Group
SR0 sX
SR1 sX
SRX sX
SRA sX
RR sX
SL0 sX
SL1 sX
SLX sX
SLA sX
RL sX
Input/Output Group
INPUT sX,pp
INPUT sX,(sY)
OUTPUT sX,pp
OUTPUT sX,(sY)
Interrupt Group
RETURNI ENABLE
RETURNI DISABLE
ENABLE INTERRUPT
DISABLE INTERRUPT
Arithmetic Group
ADD sX,kk
ADDCY sX,kk
SUB sX,kk
SUBCY sX,kk
ADD sX,sY
ADDCY sX,sY
SUB sX,sY
SUBCY sX,sY
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Instructions
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Arithmetic Logic
• Operands are
– sX and
• Constant, or…
• Another register sY
• Result goes in sX
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Logical• LOAD sx, kk
– Puts constant kk in the Sx register
• AND sx,kk
– Result in sx
• OR sX,kk
• XOR sX,kk
• All instructions with another S register as well
– LOAD sx,sy AND sx,sy OR sx,sy XOR sx,sy
– Result goes in Sx register
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Arithmetic• ADD
– Adds two 8bit numbers
– Affects Carry, Zero Flags
• ADDCY
– Same as ADD, but uses carry flag as Cin
• SUB, SUBCY
– sX = sX – sY (or constant)
– C flag indicates when underflow has occurred
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Shifts and Rotates Rightmost bit goes to C flag• SR0 sx, SR1 sx
– Shift right, bringing in ‘0’ or ‘1’
• SRX sX
– Shift right, sign extending
• SRA sx
– Rotate right through carry
• RR sx
– Rotate right without carry (carry still gets
rightmost bit as its shifted)
• JUMP aa
– Unconditionally jump to address aa (hex)
• JUMP Z, aa
– Jump if the Z flag is set to address aa
• JUMP NZ, aa
• JUMP C, aa
– Jump if the C flag is set to address aa
• JUMP NC, aa
Program Control : JUMP
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Program Control : Call/Return
• CALL (all the same varieties as jump)
– Jump to address aa and put return address
on the stack
– Use for subroutines
– Spartan III Picoblaze has a 31element stack,
so you can have subroutine entry up to 31
levels
• RETURN (same conditional varieties)
– Pops the last pushed PC address from the
stack and goes there.
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Definition of Flags
Z = 1 if result = 0 0 otherwise
zero condition
Carry flag C overflow, underflow, or various conditions
Zero flag Z
Example* C = 1 if result > 281 or result < 0 0 otherwise
*Applies only to addition or subtraction related instructions, refer to following slides otherwise
Flags are set or reset after ALU operations
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Syntax and Terminology Syntax Example Definition
sX
KK
PORT(KK)
PORT((sX))
RAM(KK)
s15
14
PORT(2)
PORT((s10))
RAM(4)
Value at register 15
Value 14
Input value from port 2
Input value from port specified by
register 10
Value from RAM location 4
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Addressing modes
Direct mode
INPUT s10, 28
ADD s10, s15
PORT(28) → s10
s10 + s15 → s10
Indirect modeINPUT s9, s2
STORE s3, s10
PORT((s2)) → s9
s3 → RAM((s10))
s2 + 15 + C → s2
s7 – 7 → s7
Immediate modeADDCY s2, 15
SUB s7, 7
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PicoBlaze ALU Instruction Set Summary (1)
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PicoBlaze ALU Instruction Set Summary (2)
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PicoBlaze ALU Instruction Set Summary (3)