EE 582 Physical Design Automation of VLSI Circuits and Systems

Prof. Dae Hyun Kim

School of Electrical Engineering and Computer Science Washington State University

Course Information

2 Physical Design Automation of VLSI Circuits and Systems

Table of Contents

• Introduction

• Course information

• What we will study

• About my research lab

3 Physical Design Automation of VLSI Circuits and Systems

Course Information

• Instructor: Prof. Dae Hyun Kim • Office: EME 504 • Email: daehyun@eecs.wsu.edu

• Class room: Thompson Hall 105 • Class time: T/Th 12pm – 1:15pm • Office hours: T/Th 1:30pm – 3pm

– or by appointment

• Class webpage

– http://eecs.wsu.edu/~daehyun/teaching/2015_EE582/

mailto:daehyun@eecs.wsu.eduhttp://eecs.wsu.edu/%7Edaehyun/teaching/2015_EE582/

4 Physical Design Automation of VLSI Circuits and Systems

Course Information

• No official prerequisites. • Students are expected to have knowledge of

– Logic circuits (EE 214) – Linear circuit analysis (EE 261) – Digital system design (EE 324) – VLSI (EE 434 / EE 466) – C/C++ programming

• Structural programming / OOP / pointer handling – Data structures and algorithms (CptS 122 / CptS 450)

5 Physical Design Automation of VLSI Circuits and Systems

Course Information

• Textbook – No required textbook.

• Recommended – VLSI Physical Design Automation: Theory and Practice, Sadiq M. Sait, Wspc,

1999 ($70 / $14) – Algorithms for VLSI Physical Design Automation, 3/E, Naveed Sherwani,

Springer, 1998 ($100 / $3) – Practical Problems in VLSI Physical Design Automation, Sung Kyu Lim, Springer,

2008 ($127 / $32)

6 Physical Design Automation of VLSI Circuits and Systems

Course Information

• Grading – Assignments (#: 10~14): 30% – Midterm exam : 15% – Final exam: 15% – Project: 40%

7 Physical Design Automation of VLSI Circuits and Systems

You Should Take This Course If You

• want to learn how to design digital VLSI layouts.

• are interested in joining chip vendors such as Qualcomm, Apple, Intel, Samsung, … as a chip designer, CAD engineer, product engineer, etc.

• are interested in CAD.

• want to join CAD companies such as Cadence, Synopsys, Mentor Graphics, …

• want to become a VLSI expert.

• are interested in joining my lab.

8 Physical Design Automation of VLSI Circuits and Systems

What we will study

• Physical design automation algorithms for the design of VLSI circuits and systems.

• Questions – What is “physical design”? – What is “design automation”?

9 Physical Design Automation of VLSI Circuits and Systems

VLSI Design

System Specification

Functional Design

RTL Code (HDL)

Synthesis

Physical Design

Fabrication

64-bit integer multiplier / 1GHz / 0.1mm2 / 0.1mW Freq Area Power

C/C++, Verilog, VHDL, …

module imul_64 (a, b, clk, out64); input a, b, clk; output out64; … endmodule

Netlist

Layout

Bare die

Packaging Chip

10 Physical Design Automation of VLSI Circuits and Systems

From RTL Code to a Chip

RTL Code (HDL)

11 Physical Design Automation of VLSI Circuits and Systems

From RTL Code to a Chip

RTL Code (HDL)

Synthesis

Tech-specific logic gates

Tech library (e.g., 45nm)

12 Physical Design Automation of VLSI Circuits and Systems

From RTL Code to a Chip

RTL Code (HDL)

Synthesis

Physical Design

13 Physical Design Automation of VLSI Circuits and Systems

From RTL Code to a Chip

RTL Code (HDL)

Synthesis

Physical Design

Fabrication

14 Physical Design Automation of VLSI Circuits and Systems

From RTL Code to a Chip

RTL Code (HDL)

Synthesis

Physical Design

Fabrication

Packaging

15 Physical Design Automation of VLSI Circuits and Systems

VLSI Design

Full custom ASIC Design Manual Automatic

TRs Manually drawn Standard-cell based Placement & Routing Custom Automatic

Development time Several months A few days ~ weeks

16 Physical Design Automation of VLSI Circuits and Systems

What is Done in the Physical Design

RTL Code (HDL)

Synthesis

Physical Design

Netlist → Physical layout

17 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

• Provides – good performance – low power – small area – …

• Other design styles

– FPGA – PLA – …

18 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

• Standard cells – A set of logic gates – Have the same height. – Width varies. – Pre-characterized for timing and power analysis.

INV NAND2

19 Physical Design Automation of VLSI Circuits and Systems

Standard Cells (Layout)

in out

p-welln-well

n-wellp-well

VDD

GND

poly (gate)

metal 1

contact

n+ (n-implant)

p+ (p-implant)

cell bounrary

in1

p-welln-well

n-wellp-well

VDD

GND

in2

out

INV NAND2

in outin1 outin2

20 Physical Design Automation of VLSI Circuits and Systems

Standard Cells (Layout)

in out

p-welln-well

n-wellp-well

VDD

GND

M3

M2

M1

substrate

p-epi

n+ n+ p+ p+n-well

p+ n+

Top-down view Side view

21 Physical Design Automation of VLSI Circuits and Systems

Design Rules

in out

p-welln-well

n-wellp-well

VDD

GND

①

①: Min. distance (poly, contact) ②: Min. distance (metal 1) ③: Min. distance (p-active, n-well boundary) ④: Min. width (poly) ⑤: Min. width (metal 1) ⑥: Min. distance (contact) ⑦: Min. distance (contact, n-well bounrary)

②

③

④ ⑤

⑥

⑦

22 Physical Design Automation of VLSI Circuits and Systems

Standard Cells (Abstract)

INV NAND2

in outin1 outin2

in out

VDD

GND

in1

VDD

GND

in2

out

metal 1

cell bounrary

23 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

in outin1

outin2

metal 1

cell bounrary

via12

metal 2

in1

VDD

GND

in2

out

in out

VDD

GND

in1 in2out

VDD

in out

24 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

• Deal with – Standard cells (pre-drawn and pre-characterized) – Routing layers (M1, via12, M2, via23, …)

25 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

• Intellectual Property (IP) blocks – Pre-created blocks

• Memory • Arithmetic • Cryptographic • DSP • Controller • …

26 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

I/O cell

Macro

Standard cells

27 Physical Design Automation of VLSI Circuits and Systems

Delay Calculation & Timing Analysis

• Pre-characterized cells

Input transition (ns) Output capacitance (fF)

5th 3rd

Delay (29ps)

Index_1

Index_2

28 Physical Design Automation of VLSI Circuits and Systems

Delay Calculation

• Interconnect delay

w

t

l

s

𝑅𝑅 = 𝜌𝜌𝑙𝑙

𝑡𝑡 ∙ 𝑤𝑤 𝐶𝐶 = 𝜖𝜖𝑡𝑡 ∙ 𝑙𝑙𝑠𝑠 𝐷𝐷𝐷𝐷𝑙𝑙𝐷𝐷𝐷𝐷 ∝ 𝑅𝑅𝐶𝐶 ∝ 𝑙𝑙

2

modeling

29 Physical Design Automation of VLSI Circuits and Systems

Timing Analysis

d1 d2

d3 d4

d5 d6 d7

d8

d9

d10 d11

d12 d13

30 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

• What should we do? – Find the locations of the macros. – Find the locations of the standard cells. – Route the macros and the standard cells.

• Power/ground • Signal • Clock • Bus

– Extract parasitic RC. – Analyze the final layout.

• Timing (clock frequency) • Power consumption (dynamic / leakage) • Area • Power integrity • Signal integrity • Thermal

31 Physical Design Automation of VLSI Circuits and Systems

Standard-Cell-Based Design

Floorplanning (macro placement)

Placement (standard cell placement)

Pre-CTS optimization

Clock-Tree Synthesis (CTS)

Post-CTS optimization

Routing

Post-routing optimization

32 Physical Design Automation of VLSI Circuits and Systems

What You Need to Know

• VLSI • Graph theory • Linear optimization • Non-linear optimization • Computational geometry • Data structure and algorithms • Programming • …

33 Physical Design Automation of VLSI Circuits and Systems

My Research Lab

• Lab – CADETS (CAD for Emerging Technologies and Systems)

• Research

– Design and analysis of VLSI circuits and systems using emerging technologies

• 3D ICs, CNT transistors/interconnects, nanowire transistors/interconnects, …

• Design methodologies, techniques, optimization algorithms • Applications for ultra-low-power, energy-efficient, high-performance

VLSI circuits and systems

34 Physical Design Automation of VLSI Circuits and Systems

CAD / EDA Conferences & Journals

• Conferences – Asia and South Pacific Design Automation Conference (ASPDAC) – Design Automation Conference (DAC) – Design, Automation & Test in Europe (DATE) – International Conference on Computer-Aided Design (ICCAD) – International Symposium on Physical Design (ISPD)

• Journals

– IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD)

– ACM Transactions on Design Automation of Electronic Systems (TODAES) – IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI)

EE 582�Physical Design Automation of VLSI Circuits and Systems��Prof. Dae Hyun Kim�School of Electrical Engineering and Computer Science�Washington State UniversityTable of ContentsCourse InformationCourse InformationCourse InformationCourse InformationYou Should Take This Course If YouWhat we will studyVLSI DesignFrom RTL Code to a ChipFrom RTL Code to a ChipFrom RTL Code to a ChipFrom RTL Code to a ChipFrom RTL Code to a ChipVLSI DesignWhat is Done in the Physical DesignStandard-Cell-Based DesignStandard-Cell-Based DesignStandard Cells (Layout)Standard Cells (Layout)Design RulesStandard Cells (Abstract)Standard-Cell-Based DesignStandard-Cell-Based DesignStandard-Cell-Based DesignStandard-Cell-Based DesignDelay Calculation & Timing AnalysisDelay CalculationTiming AnalysisStandard-Cell-Based DesignStandard-Cell-Based DesignWhat You Need to KnowMy Research LabCAD / EDA Conferences & Journals