Counters
25
Counters Discussion D8.3
description
Counters . Discussion D8.3. Counters. Divide-by-8 Counter Behavioral Counter in Verilog Counter using One-Hot State Machine. Divide-by-8 Counter. A state diagram for a divide by 8 counter . Present state Next state. State Q2 Q1 Q0 D2 D1 D0. s0 0 0 0 0 0 1 - PowerPoint PPT Presentation
Transcript of Counters
Counters
Discussion D8.3
Counters
• Divide-by-8 Counter• Behavioral Counter in Verilog• Counter using One-Hot State Machine
Divide-by-8 Counter
A state diagram for a divide by 8 counter
s0000
s1001
s2010
s3011
s7111
s6110
s5101
s4100
Divide-by-8 Counter
A state-transition table
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 D2 D1 D0Present state Next state
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
Q0
Q1
Q2
D0
D1
D2
Divide-by-8 Counter
Q2Q1 Q0
00 01 11 10
0
1 1 11
1
D2
D2 = ~Q2 & Q1 & Q0 | Q2 & ~Q1 | Q2 & ~Q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
Q2Q1 Q0
00 01 11 10
0
1
1
11
1
D1
D1 = ~Q1 & Q0 | Q1 & ~Q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
Q2Q1 Q0
00 01 11 10
0
1
1
11
1
D0
D0 = ~Q0
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 D2 D1 D0Present state Next state
Divide-by-8 Counter
A Divide by 8 counterCircuit using D Flip-flops
D Q
!QCLK
D Q
!QCLK
D Q
!QCLK
Q2
Q1
Q0
Q2
Q1
Q0
CLK
module DFF (D, clk, clr, Q);
input clk ;wire clk ;input clr ;wire clr ;input D ;wire D ;
output Q ;reg Q ;
always @(posedge clk or posedge clr)if(clr == 1)
Q <= 0;else
Q <= D;
endmodule
CLK
D Q
~Qclk
D Q
~Q
clr
module count3 ( Q ,clr ,clk );
input clr ;wire clr ;input clk ;wire clk ;
output [2:0] Q ;wire [2:0] Q ;wire [2:0] D ;
assign D[2] = ~Q[2] & Q[1] & Q[0] | Q[2] & ~Q[1] | Q[2] & ~Q[0];
assign D[1] = ~Q[1] & Q[0]
| Q[1] & ~Q[0];
assign D[0] = ~Q[0];
DFF U2(.D(D[2]), .clk(clk), .clr(clr), .Q(Q[2]));DFF U1(.D(D[1]), .clk(clk), .clr(clr), .Q(Q[1]));DFF U0(.D(D[0]), .clk(clk), .clr(clr), .Q(Q[0]));
endmodule
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
Q0
Q1
Q2
D0
D1
D2
count3 Simulation
Counters
• Divide-by-8 Counter• Behavioral Counter in Verilog• Counter using One-Hot State Machine
3-Bit Counter
always @(posedge clk or posedge clr) begin if(clr == 1)
Q <= 0; else
Q <= Q + 1; end
Behavior
count3clr
clkQ(2 downto 0)
module counter3 (clk, clr, Q );
input clr ;wire clr ;input clk ;wire clk ;
output [2:0] Q ;reg [2:0] Q ;
// 3-bit counteralways @(posedge clk or posedge clr) begin if(clr == 1)
Q <= 0; else
Q <= Q + 1; end
endmodule
counter3.v
Asynchronous clear
Output count incrementson rising edge of clk
counter3 Simulation
Recall Divide-by-8 Counter
Use Q2, Q1, Q0 as inputs to a combinational circuitto produce an arbitrary waveform.
s0 0 0 0 0 0 1s1 0 0 1 0 1 0s2 0 1 0 0 1 1s3 0 1 1 1 0 0s4 1 0 0 1 0 1s5 1 0 1 1 1 0s6 1 1 0 1 1 1s7 1 1 1 0 0 0
State Q2 Q1 Q0 D2 D1 D0Present state Next state
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
Q0
Q1
Q2
D0
D1
D2
s0 0 0 0 0 0 1 1s1 0 0 1 0 1 0 1s2 0 1 0 0 1 1 0s3 0 1 1 1 0 0 0s4 1 0 0 1 0 1 0s5 1 0 1 1 1 0 1s6 1 1 0 1 1 1 0s7 1 1 1 0 0 0 1
State Q2 Q1 Q0 D2 D1 D0 y
Example
Q2Q1 Q0
00 01 11 10
0
1
1 1
1 1
y = ~Q2 & ~Q1 | Q2 & Q0
1 1 0 0 0 1 0 1 1 1 0 0 0 1 0 1
Counters
• Divide-by-8 Counter• Behavioral Counter in Verilog• Counter using One-Hot State Machine
One-Hot State Machines
Instead of using the minimum number of flip-flops (3) to implement the state machine, one-hot encoding uses one flip-flop per state (8) to implement the state machine.
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
CLK
D Q
~QCLK
D Q
~Q
Q0
Q1
Q2
D0
D1
D2
s0000
s1001
s2010
s3011
s7111
s6110
s5101
s4100
Why use One-Hot State Machines?
Using one-hot encoding or one flip-flop per state (8) will normally simplify the combinational logic at the expense of more flip-flops.
D Q
!QCLK
D Q
!QCLK
D Q
!QCLK
Q2
Q1
Q0
Q2
Q1
Q0
CLKLet's see how for the 3-bit counter
s0000
s1001
s2010
s3011
s7111
s6110
s5101
s4100
s0000
s1001
s2010
s3011
s7111
s6110
s5101
s4100
One-Hot Encoding
s0 0 0 0 s1s1 0 0 1 s2s2 0 1 0 s3s3 0 1 1 s4s4 1 0 0 s5s5 1 0 1 s6s6 1 1 0 s7s7 1 1 1 s0
State Q2 Q1 Q0 D[0:7]Present state Next state
Think of each state as a flip-flop
D[i] = s[i-1]
This is just a ring counter!
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
s0
s1
s2
s3
s4
s5
s6
s7
Q0
Q2
Q1
s0 0 0 0 s1 0 0 1 s2 0 1 0 s3 0 1 1 s4 1 0 0s5 1 0 1s6 1 1 0s7 1 1 1
State Q2 Q1 Q0
Q2 = s4 | s5 | s6 | s7
Q1 = s2 | s3 | s6 | s7
Q0 = s1 | s3 | s5 | s7
3-bit Counter
module cnt3hot1(clk,clr,Q);
input clk;input clr;output [2:0] Q;wire [2:0] Q;reg [0:7] s;
// 8-bit Ring Counter always @(posedge clk or posedge clr)begin if(clr == 1)
s <= 8'b10000000; else
begin s[0] <= s[7]; s[1:7] <= s[0:6];end
end
// 3-bit counterassign Q[2] = s[4] | s[5] | s[6] | s[7];assign Q[1] = s[2] | s[3] | s[6] | s[7];assign Q[0] = s[1] | s[3] | s[5] | s[7];
endmodule
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
D Q
clk
s0
s1
s2
s3
s4
s5
s6
s7
Q0
Q2
Q1
