COSC1078 Introduction to Information Technology Lecture 14 Revision and Review

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Lecture 14: Review Intro to IT COSC1078 Introduction to Information Technology Lecture 14 Revision and Review James Harland [email protected]

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James Harland [email protected]. COSC1078 Introduction to Information Technology Lecture 14 Revision and Review. Introduction to IT. 1-4 Introduction, Images, Audio, Video 5-6 Computer Fundamentals Assignment 1, WebLearn Test 1 7 Review - PowerPoint PPT Presentation

Transcript of COSC1078 Introduction to Information Technology Lecture 14 Revision and Review

Page 1: COSC1078 Introduction to Information Technology Lecture 14 Revision and Review

Lecture 14: Review Intro to IT

COSC1078 Introduction to Information Technology

Lecture 14

Revision and ReviewJames Harland

[email protected]

Page 2: COSC1078 Introduction to Information Technology Lecture 14 Revision and Review

Lecture 14: Review Intro to IT

Introduction to IT

1-4 Introduction, Images, Audio, Video

5-6 Computer Fundamentals Assignment 1, WebLearn Test 1

7 Review

8 Operating Systems WebLearn Test 2

9 Operating Systems Assignment 2

10 Internet

11 Internet Security   WebLearn Test 3

12 Future of IT Assignment 3, Peer and Self Assessment

Page 3: COSC1078 Introduction to Information Technology Lecture 14 Revision and Review

Lecture 14: Review Intro to IT

Overview

Questions?

Floating point numbers

“Week 6 lectures”

Questions?

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Lecture 14: Review Intro to IT

Excess Notation

Bit pattern Value

111 3

110 2

101 1

100 0

011 -1

010 -2

001 -3

000 -4

A different encoding of the numbers

“naive” bit pattern encodes 4 more than actual value

100 (looks like 4) encodes 0101 (looks like 5) encodes 1110 (looks like 6) encodes 2….

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Floating Point

sign bitMantissa

exponent

1 bit for sign3 bits for exponent4 bits for mantissa100.101

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Floating Point

01011001 means +ve 0.1001 shifted 101 place= 1.001

Mantissa: digit sequence (1st digit always 1)

Exponent: where to put the . This is generally given in ‘excess’ notation

Binary form of 2.423 x 104

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Memory

Memory differs in performance and cost

Processor is typically much faster than memory

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Memory

Arranged as a hierarchy of cache

Level 1Level 2

Level 3

Main Memory

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Lecture 14: Review Intro to IT

Processing

ALU

CPUBUS

REGISTERS

MEMORY

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Lecture 14: Review Intro to IT

Machine Instructions

1. Move first value from memory into register 12. Move second value from memory into

register 23. If register 2 is zero, go to Step 64. Divide register 1 by register 2 & store result

in register 35. Store register 3 value in memory6. Stop

“Divide two numbers”

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Lecture 14: Review Intro to IT

Instructions in Binary?01010100001010101010100110100010101001101001010010100011100010101010100101111001001010…

LOAD register 1LOAD register 2JUMP ….STORE ….

1010110010110011000100100011001100111111

MEMORY

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One Scheme

16-bit operation codes (simple example)

Operation Code(4 bits)

Operand (12 bits)

Represent as 4 Hexadecimal numbers (0-9,A-F)Each instruction is two bytes long

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One Scheme

156C LOAD register 5 from memory 6C166D LOAD register 6 from memory 6D5056 ADD register 5 & 6 & store in register 0306E STORE register 0 to memory 6EC000 HALT....(up to 216 = 65,536 different instructions)

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Fetch Decode Execute

FETCH

EXECUTE DECODE

Machinecycle

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Two special registers

Instruction register: holds current instructionProgram counter: address of next instruction

Fetch: Put instruction specified by program counter into instruction registerIncrement program counter by two

Decode: Work out what to do

Execute: Perform the instruction

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Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A0Address Contents

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A0FETCH

156C

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A2FETCH

156C

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A2DECODE

156C

6C 2B

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A2

EXEC

156C

6C 2B

2B5

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A2 FETCH

166D

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A4 FETCH

166D

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A4 DECODE

166D

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A4 EXEC

166D

6D FF

FF6

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

A6 FETCH

5056

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Lecture 14: Review Intro to IT

Processing

A0 15A1 6CA2 16A3 6DA4 50A5 56A6 30A7 C0A8 C0A9 00

Program Counter

InstructionRegister

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Processing

Program Counter

InstructionRegister

EXEC

B258

B4

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Processing

Program Counter

InstructionRegister

EXEC

B258

58

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Connecting devices

??

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Universal Serial Bus (USB)

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Memory-mapped I/O

Program Counter

InstructionRegister

C4 EXEC

3634

34 FF

FF6

Just like writing to a memory address

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Direct Memory Access (DMA)

Put some data in memory!

OK

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Direct Memory Access

Direct Memory Access means that

doesn’t have to wait for the

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Busy Bertie the bus …

Von Neumann bottleneck

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Conclusion

Assignment 2 specified sometime this week

Finish reading book!