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37
Gabriel Chidolue Successive Refinement: A Methodology for Incremental Specification of Power Intent Verification Technologist Design Verification Technology – Mentor Graphics September 2015

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Page 1: Corporate Title – 36pt, Three Lines Max. Anchor: …...Based upon Tcl —Tcl syntax and semantics —Can be mixed with non-UPF Tcl And HDLs —SystemVerilog, Verilog, —VHDL, and

Gabriel Chidolue

Successive Refinement: A Methodology for Incremental Specification

of Power Intent

Verification Technologist

Design Verification Technology – Mentor Graphics

September 2015

Source: Notes are in Tahoma, regular, 8 point, italic, flush left, vertically aligned from the bottom of text box.

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Why are we here? — UPF methodology is still evolving in practice — Best practices are being identified

The right UPF methodology will — Ensure successful usage of IP — Enable more efficient verification — Ease retargeting to different technologies — Simplify debugging — Decrease risk

Introduction

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Done in Collaboration with ARM

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An Evolving Standard — Accellera UPF in 2007 (1.0) — IEEE 1801-2009 UPF (2.0) — IEEE 1801-2013 UPF (2.1) — IEEE 1801a-2014 UPF (2.2) — IEEE 1801-2015 UPF (3.0)

– (In development now)

For Power Intent — To define power management — To optimize power consumption

For Power Analysis (in 3.0) — Component Power Modeling

Based upon Tcl — Tcl syntax and semantics — Can be mixed with non-UPF Tcl

And HDLs — SystemVerilog, Verilog, — VHDL, and (in 3.0) SystemC

For Verification — Simulation or Emulation — Static/Formal Verification

For Implementation — Synthesis, DFT, P&R, etc.

What is UPF?

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Power Domains — Independently powered regions — Enable application of different

power reduction techniques in each region

State Retention — To save essential data when power

is off — To enable quick resumption after

power up

Isolation — To ensure correct electrical/logical

interactions between domains in different power states

Level Shifting — To ensure correct communication

between different voltage levels

Power Mgmt Concepts

PMB

Processor

Core

RAM

Power Domain 1 Power Domain 2

Power Domain 3 Power Domain 4

Iso_en

1.0v 0.8v

011000 1100 0011

011000 1100 0011

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RTL is augmented with UPF — To define power management architecture

RTL + UPF verification — To ensure that power architecture

completely supports planned power states of design

— To ensure that design works correctly under power management

RTL + UPF implementation — Synthesis, test insertion, place & route, etc. — UPF may be updated by user or tool

NL + UPF verification — Power aware equivalence checking, static

analysis, simulation, emulation, etc.

UPF 1.0 Design Flow

UPF

UPF

UPF Sim

ula

tion, Logic

al E

quiv

ale

nce C

heckin

g, …

Netlist

Synthesis

Netlist

Place & Route

RTL

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The UPF 1.0 Flow is implementation-oriented — Verification requires target technology information

But target technology may be unknown until later

This leads to — Making assumptions that turn out to be invalid — Having to redo verification again later — Delaying verification until late in the flow — Doing less than thorough verification — Having to redo verification entirely if retargeting

Successive Refinement addresses these issues

Issues With This Flow

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Successive Refinement

IP Provider: • Creates IP source

• Creates low power

implementation

constraints

IP Licensee/User: • Configures IP for context

• Validates configuration

• Freezes “Golden Source”

• Implements configuration

• Verifies implementation

against “Golden Source”

RTL

Constraint UPF

+ Configuration UPF

+

Implementation UPF

+

Implementation UPF

Implementation UPF

Sim

ula

tio

n, L

ogi

cal E

qu

ival

ence

Ch

ecki

ng,

…

Netlist

Synthesis

Netlist

P&R

Soft IP Golden Source

IP Creation 1 IP Configuration 2 IP Implementation 3

RTL Constraint

UPF

RTL Constraint

Configuration UPF

© 2013 ARM Ltd

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Constraint UPF — Power intent inherent in the IP

– power domains/states/isolation/retention etc.

— Part of source IP, travels with RTL

Configuration UPF — Application-specific configuration of instances

– Composite power domains, supply sets, power states, logic expressions, isolation and retention strategies etc.

— Required for verification

Implementation UPF — Technology-specific implementation of system

– Supply expressions, supply nets/ports, switches, etc.

— Required for implementation

UPF Layers

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ARM® Cortex®-MPCore Processor IP

Cortex MPCore PDCORTEX

Processor <n> PDCPU <n>

Instruction cache RAM

Processor <n> with no RAM

Data cache RAM

TLB RAM

L2 with no RAM

Master Interface

APB

ATB

Advanced SIMD and Floating-point

L2

PDL2

PDSIMD <n>

L1 Duplicate tag RAM

0

L1 Duplicate tag RAM

1

L1 Duplicate tag RAM

2

L1 Duplicate tag RAM

3

L2 cache RAM

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Defines Atomic Power Domains

Defines Retention Constraints

Defines Isolation Constraints

Defines Fundamental Power States

Defines Abstract Retention States

Defines Power State Constraints

Constraint UPF File

These Specify How

the IP Can and Cannot be

Used in a System

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Atomic Power Domains

# Create the L2 Cache domain

create_power_domain PDL2 –elements \

“u_ca_l2/u_ca_l2_datarams \

u_ca_l2/u_ca_l2_tagrams \

u_ca_l2/u_cascu_l1d_tagrams” \

-atomic

# Create the SIMD power domain

create_power_domain PDSIMD0 \

–elements “u_ca_advsimd0” -atomic

# Create the CPU0 power domain

create_power_domain PDCPU0 \

–elements “u_ca_cpu0” -atomic

# Create the cluster power domain

create_power_domain PDCORTEX \

–elements {.} -atomic

New feature in UPF 2.1

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Retention and Isolation Constraints

set_retention_elements PDCPU0_RETN –elements “u_ca_cpu0”

# default is isolate low

set_port_attributes –elements “u_ca_hierarchy” \

-applies_to outputs \

-clamp_value 0

# some ports need to be clamped high

set_port_attributes \

-ports “u_ca_hierarchy/out1” \

-clamp_value 1

Retain all state in

this block if any

state is retained

Use these clamp

values if isolation is

used on these ports

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Domain/Supply Power States

add_power_state PDSIMD0 –domain \

-state {RUN -logic_expr {primary == ON}} \

-state {SHD -logic_expr {primary == OFF}}

add_power_state PDSIMD0.primary –supply \

-state {ON -simstate NORMAL \

-state {OFF -simstate CORRUPT \

add_power_state PDSIMD0 –domain –update \

-state {RET}

Fundamental

Optional

Logic and Supply

Expressions will be

specified later

Defined in case

retention will be

used, for constraints

Defined in case

retention will be

used, for constraints

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Domain Power State Dependencies

add_power_state PDCPU0 -domain \

-state {RUN

-logic_expr {primary==ON && PDSIMD0==RUN}} \

-state {SHD

-logic_expr {primary==OFF && PDSIMD0==SHD}} \

-state {RET

-logic_expr {primary==OFF && PDSIMD0==RET}}

add_power_state PDCORTEX -domain \

-state {RUN -logic_expr {primary==ON && PDL2==RUN && PDCPU0==RUN}} \

-state {DMT -logic_expr {primary==OFF && PDL2==RUN && PDCPU0==SHD}} \

-state {SHD -logic_expr {primary==OFF && PDL2==SHD && PDCPU0==SHD}}

Depends upon

PDSIMD0 power states

Depends upon

PDCPU0 power states

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Power State Constraints

Specific Illegal Power States add_power_state PDCORTEX -update \ -state CPU0_RET_ONLY -illegal \

{-logic_expr {primary == ON && PDL2 == RUN &&

PDCPU0 == RET && PDSIMD0 == RUN}}

All undefined Power States are illegal add_power_state PDCORTEX –update -complete

Uses the optional RET state

to constrain use of retention

(if retention is used at all)

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Load Constraint UPF for each Instance

load_upf -scope MPCoreInst CORTEX_constraints.upf

Define Control Inputs

Define Retention Strategies

Define Isolation Strategies

Update Power States with Control Conditions

Refine Power States as Required

Configuration UPF File

All Configuration Info

Will Be Checked

Against Constraints

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MPCore Instance in a System

System PDSOC

Cortex MPCore PDCORTEX

Processor <n> PDCPU <n> Instruction

cache RAM

Processor <n> with no RAM

Data cache RAM

TLB RAM

L2 with no RAM Advanced SIMD and Floating-point

L2

PDL2

PDSIMD <n>

L1 Duplicate tag RAM

0

L1 Duplicate tag RAM

1

L1 Duplicate tag RAM

2

L1 Duplicate tag RAM

3

L2 cache RAM

Master Interface

APB

ATB

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Control Inputs for MPCore Instance

System PDSOC

Cortex MPCore PDCORTEX

Processor <n> PDCPU <n>

Instruction cache RAM

Processor <n> with no RAM

Data cache RAM

TLB RAM

L2 with no RAM Advanced SIMD and Floating-point

L2

PDL2

PDSIMD <n>

L1 Duplicate tag RAM

0

L1 Duplicate tag RAM

1

L1 Duplicate tag RAM

2

L1 Duplicate tag RAM

3

L2 cache RAM

Master Interface

APB

ATB

nRETNCPU0 nISOLATECPU0

Iso

Retention

nPWRUP_CPU0 … nPWRUP_RETN

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create_logic_port nRETNCPU0

create_logic_net nRETNCPU0

connect_logic_net nRETNCPU0 \

-ports nRETNCPU0

create_logic_port nISOLATECPU0

create_logic_net nISOLATECPU0

connect_logic_net nISOLATECPU0 \

-ports nISOLATECPU0

create_logic_port nPWRUP_CPU0

create_logic_net nPWRUP_CPU0

connect_logic_net nPWRUP_CPU0 \

-ports nPWRUP_CPU0

create_logic_port nPWRUP_RETN

create_logic_net nPWRUP_RETN

connect_logic_net nPWRUP_RETN \

-ports nPWRUP_RETN

Control Inputs for PDCPU0

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Retention Strategies

set_retention ret_cpu0 -domain PDCPU0 \

-retention_supply_set PDCPU0.retention \

-save_signal {nRETNCPU0 negedge} \

-restore_signal {nRETNCPU0 posedge}

Must satisfy

retention constraints

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Isolation Strategies

# -------- cpu clamp 0 ---------

set_isolation iso_cpu_0 -domain PDCPU0 \

-isolation_supply_set PDCORTEX.primary \

-clamp_value 0 \

-applies_to outputs \

-isolation_signal nISOLATECPU0 \

-isolation_sense low

# -------- cpu clamp 1 ---------

set_isolation iso_cpu_1 -domain PDCPU0 \

-isolation_supply_set PDCORTEX.primary \

-clamp_value 1 \

-elements “u_ca_hierarchy/out1” \

-isolation_signal nISOLATECPU0 \

-isolation_sense low

Must satisfy

isolation constraints

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PDCPU0 Supply Power State Updates

add_power_state PDCPU0.primary –supply \

-state {ON -simstate NORMAL} \

-state {OFF -simstate CORRUPT}

add_power_state PDCPU0.primary –supply -update \

-state {ON -logic_expr {nPWRUP_CPU0==0}} \

-state {OFF -logic_expr {nPWRUP_CPU0==1}}

create_power_domain PDCPU0 -update \

-supply {retention}

add_power_state PDCPU0.retention –supply \

-state {ON -simstate NORMAL -logic_expr {nPWRUP_RETN==0}} \

-state {OFF -simstate CORRUPT -logic_expr {nPWRUP_RETN==1}} \

Primary supply and its

Power States defined in

the Constraint UPF

Primary supply power

state updated in

Configuration UPF

Retention supply and its

power states defined in

Configuration UPF

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PDCPU0 Domain Power States Updates

add_power_state PDCPU0 -domain \

-state {RUN -logic_expr {primary==ON && PDSIMD0==RUN}} \

-state {SHD -logic_expr {primary==OFF && PDSIMD0==SHD}} \

-state {RET -logic_expr {primary==OFF && PDSIMD0==RET}}

add_power_state PDCPU0 -domain -update \

-state {RUN -logic_expr {retention==ON && nRETNCPU0==1 && nISOLATECPU0==1}} \

-state {RET -logic_expr {retention==ON && nRETNCPU0==0 && nISOLATECPU0==0}} \

-state {SHD -logic_expr {retention==OFF}}

Power States defined

in the Constraint UPF

Power States

updated in the

Configuration UPF

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Refining Power States

• What if there are two different retention states?

– Sleep: clock gated, domain isolated, reverse biased

– Deep Sleep: power gated, state saved in balloon latch

• Use branching refinement add_power_state PDCPU0 –domain -update \

-state {SLEEP \

-logic_expr {PDSIMD0 == RET && nPDSIMD0_SLP == 2`b10} \

-state {DEEPSLEEP \

-logic_expr {PDSIMD0 == RET && nPDSIMD0_SLP == 2`b01}

For more information, see DVCon 2015 paper

“Unleashing the Full Power of UPF Power States”

by E. Marschner, J. Biggs

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IP

constraint

UPF

IP

constraint

UPF

IP1

IP1

constraint

UPF

Verification can start already

Is IP component usage OK? Power domain partitioning, isolation/retention

requirements, power state constraints all satisfied

Is power domain interface logic OK? Isolation is used where needed by power states

Are power domain dependencies OK? Control signals aren’t corrupted at wrong times

Are power control protocols OK? Power down/up control sequencing is correct Control of isolation and state retention is correct

Is power management design OK? Design still functions correctly under power

management

Verifying the Power Management Architecture

IP1

Power Mgmt

Architecture

configuration

UPF

IP2 IP3

Power Aware

Verification

State-Based (Logical)

Technology Independent

Verify that

Constraints are

Satisfied

HDL + Constraint UPF + Configuration UPF:

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Load Configuration UPF for the System

load_upf SoC_configuration.upf

Create Supply Network Elements

Create Power Switches

Update Supply Sets with Supply Nets

Update Power States with States and Voltages

Specify Other Technology Info as Required

Implementation UPF File

Configuration Imposes

Requirements on the

Implementation

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System Power Distribution

System PDSOC

Cortex MPCore PDCORTEX

Processor <n> PDCPU <n> Instruction

cache RAM

Processor <n> with no RAM

Data cache RAM

TLB RAM

L2 with no RAM Advanced SIMD and Floating-point

L2

PDL2

PDSIMD <n>

L1 Duplicate tag RAM

0

L1 Duplicate tag RAM

1

L1 Duplicate tag RAM

2

L1 Duplicate tag RAM

3

L2 cache RAM

Master Interface

APB

ATB

VDD VSS

nP

WR

UP

CO

RTE

X

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Define Supply Network

create_supply_port VDD

create_supply_port VSS

create_supply_net VDDCORTEX -domain PDCORTEX

create_supply_net VDDCPU0 -domain PDCPU0

create_supply_net VDDRCPU0 -domain PDCPU0

create_power_switch …

connect_supply_net …

create_supply_set -update …

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Define Power Switches

create_power_switch ps_CORTEX_primary -domain PDCORTEX \

-input_supply_port { VDD VDD } \

-output_supply_port { VDDCORTEX VDDCORTEX } \

-control_port { nPWRUPCORTEX nPWRUPCORTEX } \

-on_state { on_state VDD {!nPWRUPCORTEX} } \

-off_state { off_state {nPWRUPCORTEX} }

Switches input VDD to

output VDDCORTEX

under control of

nPWRUPCORTEX

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Bind Supply Sets to Nets

create_supply_set PDCORTEX.primary -update \

-function {power VDDCORTEX} -function {ground VSS}

create_supply_set PDCPU0.primary -update \

-function {power VDDCPU0} -function {ground VSS}

create_supply_set PDCPU0.retention -update \

-function {power VDDRCPU0} -function {ground VSS}

Common Ground

Different Power Rails

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Update Supply Power States

add_power_state PDCPU0.primary –supply -update \

-state {ON \

-supply_expr {power=={FULL_ON 0.81} && ground=={FULL_ON 0.00}}} \

-state {OFF \

-supply_expr {power=={OFF}}}

Technology-Specific

Voltage Levels

Implementation-

Specific Supply

Switching Decisions

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Technology Info — Add threshold information to level shifter strategies

Library Cells — Map strategies to available ISO, LS, RET cells

Location — Add -location info to strategies based on available cells

Port States and PSTs — Add primary supply constraints for the system

Other Technology Info

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IP

constraint

UPF

IP

constraint

UPF

IP1

IP1

constraint

UPF

Verifying Power Management Implementation

IP1

Power Mgmt

Architecture

configuration

UPF

IP2 IP3

System

Implementation

implementation

UPF

Power Aware

Verification

IP1 IP2 IP3

Voltage-Based (Electrical)

Technology Dependent

(Implementation Flow)

Verify Technology-Specific

Implementation Details

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Successive Refinement enables — Clear communication between IP Provider and Consumer

– Decreased risk and more successful usage of IP

— Separation of Logical Design from Implementation – Earlier verification, before technology is known – Easier retargeting to different technologies – Easier debugging at each stage

— Preservation of Verification Equity – No need to re-verify logical configuration for new technology

Summary

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Where to Learn more …

Verification Academy — verificationacademy.com — Various videos, courses and webinars

Past DVCon papers — Feb 2015 USA, Successive Refinement : A methodology for incremental

specification of Power Intent Adnan Khan, Eamonn Quiqley, John Biggs ARM Ltd, Erich Marschner Mentor Graphics

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Set presentation title in Verdana 36pt. Black

Set presentation title in Verdana 36pt. Black

36pt Headline - AFTA

36pt Headline - AFTA

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BRIEF NAME (ARIAL BLACK 36PT, ALL CAPS )

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Note - TCL

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TCL - bit.edu.cn

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HDLS 05 UK-D-F (Apr-13).pdf

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Title 36pt Arial Regular one or two lines

Title 36pt Arial Regular one or two lines

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