conventionalpci_2dot3andpci3dot0_whatsnew

Copyright 2003, PCI-SIG, All Rights Reserved 2

PCI 2.3 and PCI 3.0 Key ChangesPCI 2.3 and PCI 3.0 Key Changes

Dan NealSenior Consultant

QuestTech


QuestTech


Agenda

Background9 Changes in PCI 2.1 and PCI 2.2

Key changes in PCI 2.3 Key changes in PCI 3.0


BackgroundBackground



PCI 2.1 Key Changes

9 66 MHz PCI provided a significant performance improvement

9 Addition of Delayed Transaction also allowed a significant performance improvement


PCI 2.2 incorporated new ECNs, such as:9 New Capabilities structure to expand configuration space

Certain capabilities added to PCI starting in PCI 2.2 are supported by adding a set of registers to a linked list called the Capabilities List.

This optional data structure is indicated in the PCI Status Register by setting the Capabilities List bit (bit 4) to indicate that the Capabilities Pointer is located at offset 34h. This register points to the first item in the list of capabilities.


A4h

E0h ID for XCapability X

5Ch ID for YCapability Y

00h ID for ZCapability Z

Offset 34h

5Ch

4Ah

E0h

Capabilities Pointer


PCI 2.2 incorporated new ECNs (cont)

9New PME# signal for remote wake up capability

9Adds a 3.3VAux signal defining a standard source of power for power management wake events




9Defines a Max Retry Time Devices cannot Retry a memory write request for longer than 10 us Some displays were found to hold off accesses with retry, while the

frame buffer was used in refreshing the screen (BW was good enough to support the screen refresh, but not simultaneously handle new accesses).

This is an item tested at the workshops. 9Message signaled interrupts was added, giving I/O

controllers ability to deliver message based interrupts




9A definition for Spread Spectrum Clocking was added This adds a low frequency variation about the clock

frequency to reduce EMI (30-33 KHz variation, -1%)

9 Incorporates an alternative access method to VPD Alternative enables less expensive use of EEPROMS



Key Changes in PCI 2.3Key Changes in PCI 2.3



A very significant change with PCI 2.3:

9Support for 5V Add-in Cards removed PCI 2.3 is the last PCI Spec defined to allow the 5V Keyed option

slot. 9Add-in card designers that want their cards to plug

into these option slots must utilize the Universal Add-in Card. 9When added performance is required, system

designers are encouraged to migrate their 33 MHz or 66 MHz PCI option slots to PCI-X 66, which will accept all PCI 2.3 compliant Add-in cards.



2.3 Spec Change Requiring Silicon Change:

9Chapter 6 Configuration Space

Added Interrupt Disable bit to the command register.

Added Interrupt Status bit to the status register.



Other General PCI 2.3 Spec changes:

9 Incorporated Errata list9 Use of multiple names for the same thing were changed to be

consistent: I.e. change to Add-in Card, and System Board.9 Preface: Updated ECN list



2.3 Spec Changes Requiring system or Add-in Card Changes:

9 Support for 5V Add-in Card removed (test, figures, etc) Chapter 1 Introduction:

Sections 1.3, 1.4, & 1.5 modified to indicate the 5V keyed card is no longer supported and included references to PCI-X spec and its higher operating frequencies.

Chapter 4 Electrical Specification: Removed support for 5V keyed Add-in Cards. Section 4.3.5 Moved 3.3V system timing budget description from section 7.7.5

to this section. Table 4-11 Reversed the position of the 3.3V and 5V System Environment

columns. Table 4-13 Deleted the 5V Add-in Card column.

Chapter 5 Mechanical Specification Deleted the 5V keyed Add-in Card and Micro Channel figures



2.3 Spec Changes Requiring system or Add-in Card Changes (cont):

9 Added Reset Timing parameter Tpvrh = 100 ms minimum (power valid to reset high) This ECN adds a timing requirement to guarantee a minimum time

between power valid and reset deassertion Gives time for FPGAs to be loaded, prior to accessing the device

during configuration.



2.3 Spec Changes whose implementation is optional

9 Added SMBus ECN as chapter 8

This ECN adds a two-wire management interface to the PCI connector.

Chapter 2 Signal Definition: Section 2.2.10 The SMBus signals were added.

Chapter 4 Table 4-11 Added SMBus signals to the table



2.3 Spec Changes whose implementation is optional (cont)

9Added the Low Profile ECN (Chapter 5 Mechanical)

This ECN added a new mechanical form factor to the PCI Local Bus Specification for low profile systems

Low Profile PCI cards have the same signal protocol, electrical definitions, and configuration definitions as standard PCI cards.



2.3 Spec Changes whose implementation is optional (cont)

9 Incorporated the Add-in Card Trace Impedance ECN.

Chapter 4 Electrical Specification, Section 4.4.3.3: This extends the impedance range to 51 100 ohms. Change needed for compatibility with PCI-X

9Added Extensible Firmware Interface to the Code Type item in Chapter 6 Configuration Space, Section 6.3.1.2



Other 2.3 Spec Changes9 Chapter 3 Bus Operation:

Section 3.7.4.2 A reference to section 6.8.2.1 was added for parity errors.

Section 3.6.3 Changed from Address/Data stepping to IDSEL Stepping. Make more similar to PCI-X (change from add/data stepping to

IDSEL stepping to be more like PCI-X (add/data stepping not allowed in PCI-X)

9 Chapter 4 Electrical Specification:

Table 4-11 Added PCIXCAP signal to the table Table 4-13 Deleted the 5V Add-in Card column.



Other 2.3 Changes (cont)

9 Appendix D Class Codes: Updated appendix D with new class code assignments - See additions to Base Class 01h, Base Class 02h, Base Class 06h, Base Class 07h, Base Class 0Ch, Base Class 0Dh, and Base Class 11h.

9 Appendix H Capability IDs: Updated appendix H with new Capability IDs Added IDs 7-0xC.

9 Appendix I Vital Product Data: Added VPD read-only keywords of FG, LC, & PG. These new keywords are intended to be used only in designs based on PICMG specifications.


Key Changes planned in PCI 3.0

Key Changes planned in PCI 3.0


Key Changes PCI 3.0Key Changes PCI 3.0

PCI 3.0 Status:9Member review accomplished9Publication waiting on finalization of MSI-X

ECN MSI-X ECN is against PCI 2.3 However, MSI-X ECN content was included in PCI 3.0 member

review draft (ECN and PCI 3.0 review in parallel)9PCI 3.0 to be published 2nd half 2003



The primary change for PCI 3.0: Support for the 5V Keyed option slot is removed

9 PCI 3.0 is the first PCI Spec that no longer allows support for the 5V Keyed option slot. Add-in card designers that want their cards to plug into 3.0

compliant systems must utilize the Universal Add-in Card or the 3.3V Add-in Card.

9 When added performance is required, system designers are encouraged to migrate their 33 MHz or 66 MHz PCI option slots to PCI-X 66, which will accept all PCI 2.3 compliant Add-in cards.



Other PCI 3.0 Changes:9 The MSI-X ECN was added



MSI9 Message Signaled Interrupts (MSI) is an optional feature that

enables a device function to request service by writing a system-specified data value to a system-specified address (using a PCI DWORD memory write transaction).

9 System software initializes the message address and message data (referred to as the vector) during device configuration, allocating one or more vectors to each MSI capable function.



MSI-X

9 MSI-X defines a separate optional extension to basic MSI functionality.

9 Many of the characteristics of MSI-X are identical to those of MSI.

9 MSI-X additional capabilities include, a larger maximum number of vectors per function the ability for software to control aliasing, when fewer vectors are

allocated than requested the ability for each vector to use an independent address and data

value, specified by a table that resides in Memory Space.



MSI and MSI-X ECN9 MSI and MSI-X each support per-vector masking.

Per-vector masking is an optional extension to MSI, and a standard feature with MSI-X.

9 A function that supports the per-vector masking extension to MSI is still backward compatible with system software that is unaware of the extension.

9 MSI-X also supports a Function Mask bit, which when set masks all of the vectors associated with a function.



Per-vector masking9 Per-vector masking is managed through a Mask and Pending bit

pair per MSI vector or MSI-X Table entry. 9 An MSI vector is masked when its associated Mask bit is set. 9 An MSI-X vector is masked when its associated MSI-X Table

entry Mask bit or the MSI-X Function Mask bit is set. 9 While a vector is masked,

the function is prohibited from sending the associated message,

and the function must set the associated Pending bit whenever the function would otherwise send the message.



MSI-X ECN9 A function is permitted to implement both MSI and MSI-X, but

system software is prohibited from enabling both at the same time.

9 For the sake of software backward compatibility, MSI and MSI-X use separate and independent capability structures.

9 On functions that support both MSI and MSI-X, system software that supports only MSI can still enable and use MSI without any modification.



MSI Capability Structure

Message Data

Next Pointer

Capability ID

Message Address

Message ControlCapability Pointer

Capability Pointer + 04h

Capability Structure for 32-bit Message Address


9 To request service, an MSI function writes the contents of the Message Data register to the address specified by the contents of the Message Address register.

9 The message control register indicates the functions capabilities and provides system software control over MSI.




Message Upper AddressMessage Data

Next Pointer

Capability ID

Message Address

Message Control Capability Pointer



Capability Pointer + 0Ch

Capability Structure for 64-bit Message Address

9 To request service, an MSI function writes the contents of the Message Data register to the address specified by the contents of the Message Address register.

9 The message control register indicates the functions capabilities and provides system software control over MSI.




Pending BitsMask Bits

Message Data

Next Pointer

Capability ID

ReservedMessage Address





Capability Structure for 32-bit Message Address and Per-vector Masking





Pending BitsMask Bits

Message Upper AddressMessage Data

Next Pointer

Capability ID

Reserved

Message Address





Capability Structure for 64-bit Message Address and Per-vector Masking





MSI-X Capability and Table Structures

PBABIR

TableBIR

PBA Offset

Next Pointer

Capability ID

Table Offset

Message Control CP +00h

MSI-X Capability Structure

CP +00h

CP +00h

31 16 15 8 7 0

9 Different from MSI, the MSI-X capability structure points to an MSI-X Table Structure and a MSI-X Pending Bit Array (PBA) structure, each residing in Memory Space.

9 Each structure is mapped by a Base Address register (BAR) belonging to the function. A BAR Indicator register (BIR) indicates which BAR, and maps Memory space.




Msg AddressMsg Upper AddrMsg DataVector Ctrl



..

Msg Data

.

Msg Upper Addr Msg Address

.

Vector Ctrl entry 0 Base

MSI-X Table Structure

DWORD3 DWORD2 DWORD1 DWORD0

entry 1 Base +1*16

entry 2 Base +2*16

entry (N-1) Base +(N-1)*16

.. ..




Pending Bits ((N-1) div 64)*64 through N-1

Pending Bits 64 through 127

Pending Bits 0 through 63

.

QWORD0 Base

MSI-X PBA Structure

63 62 61 . .2 1 0

QWORD1 Base + 1*8

QWORD0 Base

QWORD((N-1) div 64) Base+((N-1) div 64)*8



Enabling and Sending Message Interrupts9 Both MSI and MSI-X are disabled following reset.9 System configuration software sets either the MSI Enable bit or

the MSI-X Enable bit to enable either MSI or MSI-X, but never both simultaneously.

9 Once MSI or MSI-X is enabled, and one or more vectors is unmasked, the function is permitted to send messages.

9 To send a message, a function does a DWORD memory write to the appropriate message address with the appropriate message data.


Discussion /Discussion /Question and AnswerQuestion and Answer

To get answers to technical questions send Email To get answers to technical questions send Email toto techsupptechsupp@@pcisigpcisig.com.com

Key Changes PCI (2.1 2.2 - 2.3 3.0)


Thank you for attending the 2003 PCI-SIG Developers Conference.

For more information please go to www.pcisig.com

conventionalpci_2dot3andpci3dot0_whatsnew

Documents

Transcript of conventionalpci_2dot3andpci3dot0_whatsnew