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Logic Design Laboratory (10CSL38)

Mohan H G, Assistant Professor

CONTENTS

Sl. No. Experiment Page No

1a Given a 4-variable logic expression, simplify it using Entered Variable

Map and realize the simplified logic expression using 8:1 multiplexer IC.

2a Realize a J-K Master / Slave Flip-Flop using NAND gates and verify its

truth table.

3a Design and implement a mod-n (n<8) synchronous up counter using J-K

Flip-Flop ICs and demonstrate its working.

4a Design and implement a ring counter using 4-bit shift register and

demonstrate its working.

5a Design and implement an asynchronous counter using decade counter IC to

count up from 0 to n (n<=9) and demonstrate its working.

6a Design and construct a 4-bit R-2R ladder D/A converter using Op- Amp.

Determine its accuracy and resolution.

1b Design and develop the Verilog /VHDL code for an 8:1 multiplexer.

Simulate and verify its working.

2b Design and develop the Verilog / VHDL code for D Flip-Flop with

positive-edge triggering. Simulate and verify its working.

3b Design and develop the Verilog / VHDL code for mod-8 up counter.


4b Design and develop the Verilog / VHDL code for switched tail counter.




List of IC Numbers

IC Number

NAND Gate (2-input) 7400

NOR Gate (2-input) 7402

NOT Gate 7404

AND Gate (2-input) 7408

NAND Gate ( 3-input) 7410

AND Gate (3-input) 7411

OR Gate (3-input) 7432

Multiplexer 74151

Shift Register 7495

Decade Counter 7490



Components :

Sl. No. Particulars Specification Quantity

1 Multiplexer IC 74151 1

2 NOT Gate 7404 1

3 Trainer Kit - 1

4 Patch Cords - 20

Background:

Multiplexer means many into one. It is a circuit with many inputs but only one output. By

applying control signals, it can steer any input to the output.

The number of inputs to a multiplexer is multiple of 2 (2, 4, 8, 16, …) but the number of

output is always one. Hence, it is also called as data selector and control inputs are

termed as select inputs.

The circuit has n input signals, m control signals and 1 output signal. m control signals

can select at the most 2m

input signals, thus n <= 2m

.

Multiplexer is sometimes called as universal logic circuit because a 2n to 1 multiplexer

can be used as a design solution for any n variable truth table.

In Entered Variable Map, one of the input variable is placed inside the Karnaugh Map,

this variable is called as Map Entered Variable (MEV). The method records how this

variable is related to the output. Hence, the method reduces K-map size by one degree.

For instance, a 4 variable problem has 24 = 16 locations in K-map, using EVM method it

can be reduced to 24 - 1

= 23 = 8 locations in EVM.

1a Given a 4-variable logic expression, simplify it using Entered Variable

Map and realize the simplified logic expression using 8:1 multiplexer IC.

Aim : To simplify a given 4-variable logic expression using EVM and realize it using a 8:1

Multiplexer IC.



Function Table :

Inputs Outputs Observation

A B C 𝐄𝐍 Q 𝐐

X X X 1 1 1 If EN pin is at logical high value then irrespective

of the input values, the output will be 1.

0 0 0 0 D0 D0 If EN pin is at logical zero value and the input is 0 0 0

then the output will be D0

















EVM Method :

The method works as follows

Let’s consider A, B and C variables to be fed as select inputs and fourth variable D to be

present as data input using Entered Variable Map method.

All combinations of 3 select inputs and the data input is written in the truth table.

Corresponding Q value (the output) is written using the given logic expression.

Observe how the MEV variable D is related to the output and make the corresponding

entries in the MEV map.

Don’t care (X) values can be treated as either 1 or 0.

For the 8 combinations of control inputs, the corresponding 8 inputs for the MUX is

noted. Using these 8 inputs, the 8:1 MUX circuit can be designed and implemented.

Entry in MEV Map for all possible values of MEV (D) and Output (Q)

MEV Output Entry in

MEV Map

MEV Output Entry in

MEV Map D Q D Q

0 0 0

0 1 1

1 0 1 X

0 1 D

0 X 0

1 0 1 0

0 1 1

0 X 1

1 1 1 1

0 0 D

0 X X

1 1 1 X

0 0 0

1 X X

1 X 0 X



Input: A 4 variable logic Expression, f (A,B,C,D) = ∑(2,4,5,7,10,11,14) + ∑’ d(8,9,12,13,15)

Decimal

Value

Inputs MEV Output Entry in MEV Map

A B C D Q

0 0 0 0 0 0 D0 = D . 0 + D . 0 = 0

1 0 0 0 1 0

2 0 0 1 0 1 D1 = D . 1 + D . 0 = D

3 0 0 1 1 0

4 0 1 0 0 1 D2 = D . 1 + D . 1 = 1

5 0 1 0 1 1

6 0 1 1 0 0 D3 = D . 0 + D . 1 = D

7 0 1 1 1 1

8 1 0 0 0 X D4 = D . X + D . X = X

9 1 0 0 1 X

10 1 0 1 0 1 D5 = D . 1 + D . 1 = 1

11 1 0 1 1 1

12 1 1 0 0 X D6 = D . X + D . X = X

13 1 1 0 1 X

14 1 1 1 0 1 D7 = D . 1 + D . X = 1

15 1 1 1 1 X

Procedure :

1. Verify all the components and patch cords for their good working condition.

2. Connect A, B, C, D to the input ports and Q to the output port of the trainer kit.

3. Don’t care (X) entries in the EVM can be connected to either Ground or Vcc.

4. Use IC 7404 to get D , connect pin 14 to Vcc, pin 7 to Ground and input D to pin 1.

5. Connect IC 74151 pins to pin 2 of IC 7404 where ever D is required.

6. Make the connection as shown in the circuit diagram.

7. Give the power supply to the trainer kit.



8. Provide the input data to circuit via trainer kit switches (A, B, C and D) and verify the

truth table.

Circuit :



Components :


1 Shift Register IC 7495 1

2 Trainer Kit - 1

3 Patch Cords - 20

Background:

A shift register is a cascade of flip flops, sharing the same clock, in which the output of

each flip-flop is connected to the “data” input of the next flip-flop in the chain. The

circuit shifts the “bit array” stored in it by one position. Shifting of data takes place at

each transition of the clock input.

A ring counter is a counter, where the output of one flip-flop connects directly into the

input of another to produce a particular output pattern. The ability to load the flip-flops to

particular state permits a repeatable output pattern.

There are two types of ring counters:

A straight ring counter (Overbeck counter) connects the output of the last shift

register to the first shift register input and circulates a single one (or zero) bit

around the ring.

For example, in a 4-bit register, with initial register values of 1000, the repeating

pattern is: 1000, 0100, 0010, 0001, 1000...

A twisted ring counter (Johnson counter) connects the complement of the output

of the last shift register to the input of the first register and circulates a stream of

ones followed by zeros around the ring.

4a Design and implement a ring counter using 4-bit shift register and

demonstrate its working.

Aim : To design a ring counter using 4-bit shift register.



For example, in a 4-bit register counter, with initial register values of 0000, the

repeating pattern is: 0000, 1000, 1100, 1110, 1111, 0111, 0011, 0001, 0000...

IC 7495:

Circuit for Ring Counter :

The Pins A, B, C and D are used to load the flip flops with required values. QA, QB, QC and QD

are outputs of individual flip flops. The output of last flip flop (QD) is fed as input to the first flip

flop through pin 1. Pin 1 is input to the first flip flop. The state table is shown for the pattern

“1000”.

Procedure :

1. Verify all the components and patch cords for their good working condition.

2. Make connection as shown in the circuit diagram.

3. Connect pin 7 of 7495 IC to GND and pin 14 to VCC.



4. Connect A, B, C, D and MODE (pin 2, 3, 4, 5, 6) to the input ports of the trainer kit.

5. Connect QA, QB, QC and QD (pin 13, 12, 11, 10) to the output ports of the trainer kit.

6. Provide feedback by connecting pin 10 to pin 1.

7. Short pin 8 and pin 9 to clock pulse, use MonoPulse or 1 Hz TTL.

8. Give supply to the trainer kit.

9. Select the pattern for ring counter by setting the input pins A, B, C, D to the required

pattern. For example to load 1000 value. Set A, B, C and D input values to 1, 0, 0 and 0

respectively.

10. To load the 4-bit input to the ring counter set the MODE pin 6 to 1. When MODE pin is

set to 1 the pattern is loaded to respective flip flops parallely in a single clock cycle.

11. After loading the pattern, set the mode pin 6 to 0 inorder to start the ring counter

operation. Apply clock pulses to check the working. Observe the right shifting of data on

each clock pulse.

12. If clock pin 8 and 9 are connected to MonoPulse then keep pressing the clock pulse till

the original pattern repeats. If clock pin 8 and 9 are connected to TTL then clock pulses

are applied automatically.

13. Give different patterns of inputs and verify the working of ring counter.

Workout: Johnson Counter (Switched Tail Counter) :



Components :


1 Decade Counter IC 7490 1

2 2 input - AND Gate 7408 1

3 Trainer Kit - 1

4 Patch Cords - 20

Background:

A counter is a register that goes through a predetermined sequence of states upon the

application of input pulses. In asynchronous counter a clock signal is provided for one

flip-flop and its output is provided as clock source for next flip-flop. The output of

asynchronous counter is not synchronized with clock signal.

A decade counter follows a sequence of 10 states and returns to zero after the count of

nine. Such a counter must have atleast 4 flip flops to represent each decimal digit, since a

decimal digit is represented by a binary code with atleast 4 bits.

IC 7490:

The 74LS90 is a simple counter, it can count from 0 to 9 cyclically in its natural mode. It

counts the input pulses and the output is received as a 4-bit binary number through pins

QA, QB, QC and QD.

The binary output is reset to 0000 at every tenth pulse and count starts from 0 again. A

pulse is also generated (at pin 9) as it resets its output to 0000.

The chip can count up to other maximum numbers and return to zero by changing the

modes of 7490. These modes are set by changing the connection of reset pins R1 - R4. For

example, if either R1 & R2 are high or R3 & R4 are ground, then it will reset QA, QB,

5a Design and implement an asynchronous counter using decade counter IC

to count up from 0 to n (n<=9) and demonstrate its working.

Aim : To design an asynchronous counter for a given modulo n.



QC and QD to 0. If resets R3 & R4 are high, then the count on QA, QB, QC and QD goes to

1001.

Function Table:

Input Output

R1 R2 R3 R4 QD QC QB QA

H H L X 0 0 0 0

H H X L 0 0 0 0

L X H H 1 0 0 1

X L H H 1 0 0 1

L X L X COUNT

X L X L COUNT

L X X L COUNT

X L L X COUNT

It can be noted that the outputs will be set to 0000 whenever R1and R2 are high. And the outputs

will be set to 1001 whenever R3and R4 are high. All four R1, R2, R3 and R4 cannot be high at

the same time. In all other cases, the outputs will follow the counter.

State Diagram:



Working :

1. Connect power supply VCC to pin 5 and GND to pin 10 of IC 7490.

2. Connect pin 14 to mono pulse or TTL (1KHz) and output pins are QA (pin 12), QB

(pin 9), QC (pin 8) and QD (pin 11) to the output port of trainer kit.

3. Note that QD is MSB pin followed by QC, QB, QA. QD must be leftmost output and QA

is rightmost output.

4. Reset pins R1, R2, R3 and R4 are connect to GND, i.e pin 2, pin 3, pin 6 and pin 7 to

GND.

5. Apply clock pulse using mono-pulse or TTL, the counter starts counting from “0” to “9”

repeatedly. This verifies the working of decade counter.

Designing Mod 5 Counter :

Mod 5 counter must count from 0 to 4, which means when the output becomes 0101, it

must be reset to 0. The counter can be reset to 0 by making R1 and R2 values as 1 (High).

Observe the number 0101, where QD = 0, QC = 1, QB = 0 and QA = 1.

Consider only those output values which are high. In this case QC and QA are high.

Thus, counter must be reset to 0 when ever QC and QA are high.

Provide QC and QA as input to the AND Gate, and connect the output of AND Gate to

R1 and R2.

When ever QC and QA are high, the output of AND Gate will be high, since AND Gate

output is connected to R1 and R2, the counter will be reset to 0.



Circuit for Mod 5 Counter



must be reset to 0. Where QD = 0, QC = 1, QB = 1 and QA = 1.

Counter must be reset to 0 when ever QC, QB and QA are high.

Perform AND operation of QC, QB and QA and connect the output of AND operation to

R1 and R2. The AND operation od QC, QB and QA can be done as shown in the circuit.

When ever QC, QB and QA are high, the output of AND Operation will be high, since

the output is connected to R1 and R2, the counter will be reset to 0.






must be reset to 0. Where QD = 0, QC = 1, QB = 0 and QA = 0.

The counter must be reset to 0 when ever QC is high. Hence, directly connect QC to R1

and R2.


Designing Other Modulo’s:

Mod 2 counter can be obtained by directly connecting QB to R1 and R2.

Mod 3 counter can be obtained by connecting AND operation output of QA and QB to

R1 and R2.

Mod 6 counter can be obtained by connecting AND operation output of QB and QC to

R1 and R2.

Mod 8 counter can be obtained by directly connecting QD to R1 and R2.



Components :


1 Op-Amp μA 741 1

2 Resistors 1 KΩ, 2.2 KΩ 4, 6

3 Trainer Kit - 1

4 Bread Board - 1

5 Volt Meter - 1

6 Connecting Wires - 20

Background:

Digital to analog converter (DAC) is used to get analog voltage corresponding to an input digital

data. Data in binary digital form can be converted to corresponding analog form by using a R-2R

ladder (binary weighted resistor) network and a summing amplifier.

A digital to analog converter accepts an n-bit input word in binary and produces an analog signal

proportion to it. There are mainly two techniques used for analog to digital conversion.

1. Binary weighted resistor D/A converter

2. R/2R ladder D/A converter

In these techniques the shunt resistors are used to generate n binary weighted currents. These

currents are added according to switch positions controlled by the digital input and then

converted into voltage to get analog voltage equivalent to digital input. R/2R ladder uses only

two resistor values. This avoids resistance spread drawback.

6a Design and construct a 4-bit R-2R ladder D/A converter using Op-Amp. Determine

its accuracy and resolution.

Aim : To design a D/A converter using μA 741 IC and find its accuracy and resolution.

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