Contact Resistance Reduction Technology Using Aluminum Implant and Segregation for Strained...

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 6, JUNE 2010 1279

Contact Resistance Reduction Technology UsingAluminum Implant and Segregation for Strained

p-FinFETs With Silicon–Germanium Source/DrainMantavya Sinha, Student Member, IEEE, Rinus Tek Po Lee, Student Member, IEEE,

Eng Fong Chor, Senior Member, IEEE, and Yee-Chia Yeo, Member, IEEE

Abstract—We have demonstrated the introduction of an addi-tional aluminum (Al) implant step in the fabrication of strainedp-FinFETs with silicon–germanium (SiGe) source/drain (S/D). Alis implanted into the p+-SiGe S/D region at energy of 10 keVand a dose of 2 × 1014 atoms/cm2, followed by its segregationat the NiSiGe/p+-SiGe S/D interface during germanosilicidation.The presence of Al at this interface leads to lowering of theeffective Schottky barrier height for hole conduction, which, inessence, lowers the S/D contact resistance RC . RC is a dominantcomponent of the FinFET parasitic series resistance RSD, whichis lowered by approximately 25% using this technology, corre-spondingly leading to a substantial increase in the saturation drivecurrent. The novel Al-segregated NiSiGe/p+-SiGe S/D contactjunction in p-FinFETs does not degrade short-channel effects orthe NiSiGe film morphology.

Index Terms—Al implant, contact resistance, FinFET, NiSiGe,series resistance.

I. INTRODUCTION

MULTIPLE-GATE FETs or FinFETs have better con-trol of short-channel effects (SCE) than planar bulk

MOSFETs and ultrathin-body MOSFETs, allow gate lengthscaling into the sub-10-nm regime, and could be potentiallyadopted in sub-22-nm technology generations [1]–[13]. Byusing a low-channel doping concentration, FinFETs suffer lessfrom mobility degradation due to impurity scattering and vari-ability in device characteristics due to random dopant fluctu-ation. Nevertheless, there are challenges associated with theadoption of FinFET or multiple-gate FETs for manufacturing.A prominent issue is the high source/drain (S/D) parasiticseries resistance RSD, wherein the contact resistance RC atthe silicide/(heavily doped S/D) interface is a major contributorto RSD [14]. RC is inversely proportional to the fin widthWFIN and increases with device scaling, posing a bottleneckfor the achievement of high drive current in aggressively scaledFinFETs. RC is an exponential function of the Schottky barrier

Manuscript received July 15, 2009; revised December 4, 2009; acceptedMarch 3, 2010. Date of publication April 22, 2010; date of current versionMay 19, 2010. This work was supported by the National Research Founda-tion, Singapore, under Grant NRF-RF2008-09. The review of this paper wasarranged by Editor C.-Y. Lu.

The authors are with the Department of Electrical and Computer En-gineering, National University of Singapore, Singapore 117576 (e-mail:[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2010.2045682

height ΦB at the silicide/(heavily doped S/D) interface [15].Hence, various techniques to reduce ΦB have been pro-posed and integrated in n-FETs, e.g., novel silicides (suchas nickel–aluminide silicide and nickel–dysprosium silicide),dopant segregation Schottky (DSS) involving arsenic im-plant, and sulfur and selenium segregation [16]–[20]. Forp-FETs, DSS contact (involving boron implant) and a novelsilicide (nickel–platinum germanosilicide) contact have beenreported [21], [22].

While silicon–germanium (SiGe) S/D stressors and nickel-based germanosilicide S/D contacts are an integral part of thep-FETs in mainstream CMOS technology, the Schottky barrierheight Φp

B for holes at the germanosilicide/SiGe interface isstill above 0.2 eV. Recently, we have demonstrated the low-ering of the effective Schottky barrier height of holes Φp

B fornickel germanosilicide (NiSiGe) on SiGe from 0.4 eV to sub-0.1 eV using a novel aluminum (Al) ion implant into SiGe andits segregation after nickel (Ni) deposition and germanosilici-dation at the NiSiGe/SiGe interface [23]. Al was implantedat energy of 10 keV at a dose in the range of 2 × 1014 to2 × 1015 atoms/cm2, which does not affect the NiSiGe filmmorphology and its bulk electrical properties. The loweringof Φp

B is attributed to the thinning of the Schottky barrierwidth at the NiSiGe/SiGe interface, due to the interfacial dipolegenerated by Al atoms. This dipole could be due to the presenceof acceptor-type trap levels generated by Al in the silicon (andSiGe) bandgap near the valence band, which are filled withelectrons, although it must be mentioned that determination ofthe exact mechanism requires further experimental study.

In this paper, we demonstrate the integration of the novelAl implant and segregation technology at the NiSiGe/p+-SiGeS/D contact interface in strained p-channel FinFETs and reportdetailed device characterization results, which show RC andRSD reduction due to the Al implant, contributing to drivecurrent enhancement.

II. EXPERIMENTAL

A. Fabrication of p-Channel FinFETs WithAl-Segregated Contacts

Two-hundred-millimeter silicon-on-insulator substrates with70-nm-thick (001) silicon (Si) and 140-nm-thick buried siliconoxide (BOX) were used as starting substrates. Fig. 1(a) showsthe key steps used for fabricating trigate p-channel FinFETs

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1280 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 57, NO. 6, JUNE 2010

Fig. 1. (a) Process flow used for fabricating strained p-channel trigate FinFETs with Al implant and segregation at the NiSiGe contact. The Al implant stepwas skipped for control p-FinFETs. Critical process steps for the formation of Al-segregated NiSiGe/p+-SiGe S/D contact are also illustrated in (b)–(d). AfterSiGe epitaxial growth to form raised S/D stressors in strained p-FinFETs, dopant implant and activation was performed, followed by the first step in the contactformation process. (b) Blanket Al implant at a dose of 2 × 1014 atoms/cm2 and energy of 10 keV. This was followed by (c) 10-nm nickel deposition. Finally, (d)germanosilicidation was performed at 400 ◦C for 30 s, followed by SPM cleaning to remove the unreacted nickel. During NiSiGe formation, Al segregates nearthe NiSiGe/p+-SiGe interfacial region.

with Al-segregated NiSiGe/p+-SiGe S/D. The channel orien-tation, i.e., source-to-drain direction, is 〈110〉. The Si layer wasfirst thinned down to 40 nm using dry oxidation followed bydilute HF etch. Threshold voltage adjust implant was performedon all wafers using phosphorus (P) at energy of 22 keV and adose of 4 × 1013 atoms/cm2 through 10 nm of sacrificial sili-con dioxide (SiO2) layer, which was deposited using plasma-enhanced chemical vapor deposition (PECVD). Activation ofphosphorus dopants was performed using a 1000 ◦C 60-s an-neal. A 70-nm-thick PECVD SiO2 hardmask was deposited onthe wafers. Using 248-nm lithography, photoresist lines downto a width of ∼170 nm were defined on the hardmask. Resisttrimming using N2−O2 plasma further reduced the photoresistlinewidth to ∼90 nm. The photoresist pattern was transferred tothe underlying PECVD SiO2 using reactive-ion etching (RIE).After resist removal, isotropic wet etch using diluted hydrofluo-ric acid (DHF) was utilized to trim the linewidth of the PECVDSiO2 pattern down to ∼50 nm. Finally, the SiO2 hardmaskpattern was transferred to the underlying Si active layer bymesa etching using a highly selective RIE process involvingHBr−Cl2−HeO2 plasma. Si fins having a fin height HFin of∼40 nm and a fin width WFin of ∼50 nm were thus formed.

After removal of the hardmask on the fins, a 3-nm-thick SiO2

gate dielectric was thermally grown, followed by deposition ofa 80-nm-thick polycrystalline silicon (poly-Si) electrode mate-rial using low-pressure chemical vapor deposition (LPCVD).This was followed by deposition of sacrificial PECVD SiO2

with a thickness of 10 nm. Gate implant was performed throughthe PEVCD SiO2 layer using BF2 at energy of 10 keV and adose of 2.5 × 1014 atoms/cm2. The implant was performed ata 45◦ angle to the normal of the wafers with eight rotations toensure that the entire volume of the gate material is implanted,considering the 3-D topography of the poly-Si enveloping theSi fin. Similar to the fin definition process, the gate length LG

down to 60 nm was defined using 248-nm lithography, resisttrimming, and RIE (with 70 nm of PECVD SiO2 as hardmask).

The poly-Si gate etch used a HBr−Cl2−He−O2 plasma, and anoptimized overetching step was performed to remove the poly-Si stringers from the fin sidewalls. The gate hardmask was notremoved at this stage.

After gate definition, source and drain extension implantwas performed through 10 nm of spacer liner oxide (PECVDSiO2), involving BF2 at energy of 15 keV and a dose of1 × 1014 atoms/cm2. Silicon nitride (SiN) with a thickness of40 nm was then deposited using LPCVD. SiN spacers wereformed by dry etch, and an optimized overetch step was usedto remove the SiN stringers from the fin sidewalls. This wasfollowed by the selective growth of a SiGe epilayer with a Geconcentration of 26% and a thickness of 45 nm on the Si S/Dregions. The absence of SiN spacer stringers around the finenables SiGe to grow on the fin sidewalls for enhanced couplingof compressive strain to the transistor channel [10]. The gatehardmask was then removed by DHF, followed by deep S/Dimplant at energy of 5 keV and a dose of 4 × 1015 atoms/cm2.Dopant activation anneal was carried out at 1000 ◦C for 1 s.

After dopant activation, the first step of the contact formationprocess was implantation of Al at energy of 10 keV and adose of 2 × 1014 atoms/cm2 [Fig. 1(b)]. All p-FinFETs (exceptcontrol devices) in this paper received the same Al implant doseof 2 × 1014 atoms/cm2 (at energy of 10 keV), unless otherwisementioned. It is this additional implant step that leads to thelowering of NiSiGe/p+-SiGe S/D contact resistance, whichwill be discussed later. The control wafer did not go throughany Al implant. All wafers received standard DHF cleaningbefore deposition of 10 nm of Ni [Fig. 1(c)]. The wafers werethermally annealed at 400 ◦C for 30 s to form NiSiGe S/Dcontact (and NiSi gate contact). The germanosilicide formationprocess causes segregation of Al at NiSiGe/p+-SiGe, as illus-trated in Fig. 1(d). Unreacted Ni was selectively etched using a4 : 1 mixture of sulfuric acid and hydrogen peroxide (SPM) at120 ◦C for 90 s. All devices were electrically characterized atthe silicide level.

SINHA et al.: ALUMINUM IMPLANT AND SEGREGATION FOR p-FinFETs WITH SiGe S/D 1281

Fig. 2. (a) Top-view SEM image of a strained p-FinFET device that wentthrough Al-segregated NiSiGe/p+-SiGe S/D contact formation. The introduc-tion of Al does not affect the NiSiGe film morphology. (b) Cross-sectional TEMimage of a strained p-FinFET. FIB cut is done along line A-A′, as shown in (a),which is not on the part of the gate line that runs across the active fin region.The actual physical gate length for this device is therefore slightly smaller than125 nm. The NiSiGe film thickness is estimated to be ∼25 nm.

B. Fabrication of p+/n Contact Diodes With Al Segregated atSilicide Contact

For fabrication of p+/n contact diodes to emulate the drain-to-substrate junction in the fabricated p-FinFETs, 200-mmn-type bulk Si (001) wafers (1–10 Ωcm) were used as startingsubstrates. These diodes were fabricated to compare the junc-tion leakage currents with and without Al implant. Two hundrednanometers of SiO2 was grown on the substrate wafer by wetoxidation and then patterned and dry etched to define square ac-tive areas having a 85 μm × 85 μm dimension. A Si0.74Ge0.26

epilayer with a thickness of 45 nm was grown in the activeareas using LPCVD. This was followed by BF2 implantationat energy of 5 keV and a dose of 4 × 1015 atoms/cm2 to formp+ regions. Dopant activation was performed at 1000 ◦C for 1 s.In one wafer, Al was then implanted at energy of 10 keV and adose of 2 × 1014 atoms/cm2. The control wafer did not receiveany Al implant. After DHF cleaning for native SiO2 removal,10 nm of Ni was deposited using an e-beam evaporator, anda germanosilicidation anneal was performed at 400 ◦C for30 s to form NiSiGe. Unreacted Ni was removed using SPMto complete diode fabrication.

III. RESULTS AND DISCUSSION

A. Morphology and I–V Characteristics of p-FinFETs WithAl-Segregated NiSiGe/p+-SiGe S/D Interface

Fig. 2(a) shows the top-view scanning electron microscopy(SEM) image (rotated and tilted at 45◦) of a completedp-FinFET that underwent Al implant and NiSiGe S/D contactformation. The NiSiGe film is uniform with no evidence ofagglomeration. Fig. 2(b) shows the cross-sectional transmissionelectron microscopy (TEM) image of a fabricated p-FinFETwith Al implant and contact formation with focussed ion beam(FIB) cut along line A-A′, as illustrated in the SEM image ofFig. 2(a). Due to off-centering of the FIB cut, the TEM imageshows the gate stack to be on top of the BOX layer, insteadof it being on top of the Si fin. With 10 nm of Ni used forgermanosilicidation, the actual NiSiGe thickness is obtained tobe ∼25 nm, close to the expected value of ∼22 nm [24]. The

Al implant did not affect the NiSiGe film morphology, which isconsistent with our earlier demonstration [23].

Fig. 3(a) shows the IDS–VGS plot of a pair of p-FinFETswith and without Al implant. The devices have an LG valueof 105 nm and a WFin value of 50 nm. VTSAT values for all p-FinFETs in this paper were extracted using the constant-currentmethod [25]. The saturation threshold voltage VTSAT is definedto be the VGS at which IDS is 1 μA/μm at a fixed VDS of−1.2 V. The two devices in Fig. 3(a) also have similar drain-induced barrier lowering (DIBL) of ∼45 mV/V, subthresholdswing (SS) of ∼95 mV/dec, VTSAT of ∼ −0.125 V, andOFF-state current IOFF on the order of 10−10 A/μm. SCEsare perfectly matched, indicating comparable effective channellengths. In Fig. 3(a), IDS enhancement is visible in both linearand saturation regions. Fig. 3(b) plots the IDS–VDS characteris-tics of the same pair of p-FinFETs at various gate overdrives(VGS − VTSAT) from 0 to −1.2 V in steps of −0.2 V. AtVGS − VTSAT = VDS = −1.2 V, the saturation drive currentIDSAT is ∼30% higher in the p-FinFET with Al-segregatedNiSiGe/p+-SiGe S/D junction, as compared with the controlp-FinFET without Al implant.

Fig. 4(a) plots IOFF versus IDSAT for p-FinFETs with andwithout Al implant. IOFF and IDSAT were extracted at VGS val-ues of 0 and −1.2 V, respectively, with VDS kept at −1.2 V. Eachdata set (with or without Al implant) comprises 30–40 deviceswith LG ranging from 60 to 230 nm. It can be observed thatthe enhancement in IDSAT, i.e., ΔIDSAT, at a fixed IOFF forFinFETs with Al-segregated NiSiGe/p+-SiGe S/D junctionover the control FinFETs increases with scaling of LG.FinFETs with a smaller LG have a larger IOFF and a corre-spondingly higher ΔIDSAT with Al implant. This is due to theenhanced effect of RSD reduction on ΔIDSAT in short-channeldevices, which will be discussed in more detail in the next sec-tion. Fig. 4(b) shows the statistical plot of drive current at a fixedgate overdrive of −1.2 V and VDS = −1.2 V for two sets of p-channel FinFET devices with and without Al implant, havingan LG of 105 nm and an WFin of 50 nm. The control deviceshave a mean drive current of ∼ 204 μA/μm, which increasesto ∼ 264 μA/μm for the FinFET devices with Al-segregatedNiSiGe/p+-SiGe junctions, giving a ∼29% enhancement.

B. Series Resistance Extraction

Fig. 5 shows a plot of total resistance RTotal versus LG forp-FinFETs with and without Al-segregated NiSiGe/p+-SiGeS/D junction at a linear gate overdrive (VGS − VTLIN) of −2and −1.8 V, where VTLIN is the threshold voltage obtained fromthe IDS–VGS curve in the linear region. The same set of devices,as plotted in Fig. 4(a) and (b), was used for series resistanceextraction. At each gate length in Fig. 5, one RTotal data point isobtained from an average of eight to ten devices. With VDS keptat a low value of −50 mV to ensure MOSFET operation in thelinear region, and the device maintained under strong inversionby keeping VGS − VTLIN � 0.5VDS, RTotal is given by [25]

RTotal =VDS

IDS= RCH + RSD

=LG − ΔL

WeffμeffCox(VGS − VTLIN)+ RSD (1)


Fig. 3. (a) IDS–VGS characteristics of a pair of strained p-FinFETs with and without Al implant. The devices have a gate length LG of 105 nm and a fin widthWFin of 50 nm and have comparable SCEs. (b) IDS–VDS characteristics of the same pair of p-FinFETs showing that Al implant and segregation contributes to∼30% higher IDSAT at VDS = VGS − VTSAT = −1.2 V.

Fig. 4. (a) IDSAT–IOFF plot for strained p-FinFETs with and without Al implant showing a significant enhancement in saturation drive current IDSAT withAl implant. (b) Statistical box plot of IDSAT at a gate overdrive and VDS of −1.2 V, for two sets of FinFETs with LG = 105 nm and WFin = 50 nm, with andwithout Al implant at a dose of 2 × 1014 atoms/cm2. The box is determined by the 25th and 75th percentiles. The whiskers are determined by the 1st and 99thpercentiles. The curve next to the box plots shows the normal distribution of data points.

where RCH is the FinFET channel resistance, Weff is theeffective channel width, μeff is the effective channel mobility,Cox is the oxide capacitance per unit area, and ΔL is thedifference between the physical gate length (same as LG) andthe effective channel length Leff . Leff and LG are particularlydifferent for devices with lightly doped drain (LDD) structures,where the channel can extend into the LDD at higher gatevoltages. Equation (1) can further be written as

RTotal = ALG + B (2)

where A and B are given by

A = 1/WeffμeffCox(VGS − VTLIN) (3)

B =RSD − AΔL. (4)

Linear regression was used to fit the RTotal versus LG plotfor devices with and without Al implant, at the two different

(VGS − VTLIN) values of −1.8 and −2 V, as shown in Fig. 5.The slope and y-intercept of the linear regression fits are used toextract two sets of A and B using (2), each for devices with andwithout Al implant. The two (VGS − VTLIN) values are selectedclose to each other because, although ΔL and RSD are assumedto be constant in (1)–(4), they do have a weak dependenceon VGS. The extracted values of A and B are, in turn, least-squares-error fitted using (4) to quantify ΔL and RSD (inset ofFig. 5). RSD for control p-FinFETs (without Al implant) andp-FinFETs with Al implant (Al-segregated NiSiGe/p+-SiGeS/D junction) are evaluated to be 783 and 617 Ω · μm, respec-tively, giving a drop of approximately 25%. It should be notedhere that, in (1)–(4), it has been assumed that μeff is not afunction of LG, which may not be true due to the presence ofSiGe S/D region in the p-FinFETs used in this paper, and hencemay introduce some errors in the accurate extraction of RSD.

The interfacial contact resistivity ρC (and, hence, RC) at theNiSiGe/p+-SiGe interface is an exponential function of ΦB at


Fig. 5. Plot of RTotal versus LG for strained p-FinFETs with and without Alimplant in the linear region at VGS–VTLIN of −1.8 and −2 V. (Inset) Plot ofparameter B versus parameter A [two sets of values each for devices with andwithout Al implant and extracted using (1) and (2)]. Open symbols representthe control devices (without Al implant), whereas closed symbols are for theAl-implanted devices. Linear regression fit of data gives a y-axis intercept thatallows for extraction of RSD. The dashed line is the linear fit of data for controldevices, whereas the solid line is the linear fit of data for Al-implanted devices.

Fig. 6. Mean saturation drive current in p-FinFETs with and without Alimplant at gate lengths LG of 230 and 80 nm. IDSAT enhancement increaseswith gate length reduction.

the interface and is given by ρC ∝ e((4Π√

εSiGem∗/h)[ΦB/√

ND]),where εSiGe is the permittivity of SiGe, m∗ is the effectivemass of hole, h is the Planck’s constant, and ND is the dopingconcentration in the p+-SiGe S/D region [15]. With ∼77%drop in the hole Schottky barrier height of NiSiGe on SiGe,from 0.4 eV (for control sample without Al) to 0.12 eV (forsample with Al implant at a dose of 2 × 1014 atoms/cm2), RC

is bound to drop, leading to a drop in RSD [23]. Thus, the IDSAT

enhancement is attributed to reduction in RC (and, hence, RSD)due to the presence of Al-segregated NiSiGe/p+-SiGe S/Djunction. Note that this drop in the hole Schottky barrier heightof NiSiGe on SiGe is extracted using test structures that didnot go through the S/D implant and anneal process used forFinFETs [23].

As LG is reduced from 230 to 80 nm, IDSAT enhancementincreases from 25% to 35%, as shown in Fig. 6. The impactof RSD reduction on drive current enhancement is higher fordevices with a smaller gate length, which is in good agreementwith published work [26], [27]. For each of the two device splits(with and without Al implant), the sample size for evaluationof the mean IDSAT at each LG is ∼15. The measurement

Fig. 7. Plot of saturation drive current versus DIBL for strained p-FinFETs.All measured data are plotted as circles for p-FinFETs without Al implant(control) and as solid triangles for p-FinFETs with Al implant. A higherenhancement in drive current with Al implant and segregation is achieved athigher DIBL.

Fig. 8. IOFF extracted at VGS = 0 V is plotted against VTSAT, which showsthat the transistor OFF-state leakage current is not affected by Al implant at adose of 2 × 1014 atoms/cm2.

of IDSAT was done at VDS = VGS − VTSAT = −1.2 V. Theenhancement in IDSAT with Al implant is further illustrated byplotting IDSAT against DIBL in Fig. 7. Devices with LG from60 to 230 nm were plotted in Fig. 7, and these are essentiallythe same devices that were illustrated in Figs. 4 and 5. Again,as expected, FinFETs with a shorter LG have a higher IDSAT

and a poorer SCE control (or higher DIBL) and, hence, a higherIDSAT enhancement with Al implant.

C. Control of SCEs

We plot IOFF versus VTSAT in Fig. 8 to examine the match-ing of SCE in strained p-FinFETs with and without Al implant.The devices have LG in the range of 60–230 nm and are thesame set of devices as those plotted in Fig. 7. Note that, dueto the relatively large gate oxide thickness (∼3 nm) and finwidth (∼50 nm) used in these devices, SCE control is not fullyoptimized, and hence, IOFF and VTSAT have a relatively largespread. IOFF is extracted at VGS of 0 V and VDS of −1.2 V.It can clearly be seen that, at any fixed VTSAT, the IOFF

for the two splits are very similar, indicating similar SS. TheAl implant did not degrade the SS or IOFF. Thus, SCEs are


Fig. 9. Cumulative distributions of (a) VTSAT, (b) DIBL, and (c) SS in strained p-FinFETs with and without Al implant. Both device splits have comparableVTSAT, DIBL, and SS, suggesting that gate control of SCEs is unaffected by the Al implant and segregation process.

Fig. 10. Cumulative distributions of NiSiGe-contacted p+(SiGe/Si)/n(Si)diode junction leakage current, measured at a reverse bias voltage of −1.2 V.(Inset) Schematic of the fabricated diode used for this measurement. The resultssuggest that the Al implant and segregation process does not affect the drain-to-substrate junction leakage characteristics.

effectively matched for the devices with and without Al im-plant. Fig. 9 shows the cumulative probability distribution (inpercentage) of VTSAT [Fig. 9(a)], DIBL [Fig. 9(b)], and SS[Fig. 9(c)], for p-FinFETs with and without Al implant. Thesethree parameters are extracted for the same set of devices thatwere used in Fig. 8. We find that the spread of parametersand the cumulative probability coincide for devices with andwithout Al implant, showing no degradation of SCE due to theAl implant.

In Fig. 10, we compare the p+/n junction leakage current instrained p-FinFETs with and without Al implant. A schematicof the fabricated diode is shown as an inset in Fig. 10. It isessentially a NiSiGe-contacted p+-SiGe S/D junction on n-type Si, which emulates the drain-to-substrate p+/n junctionin FinFETs used in this paper. The junction leakage current isextracted at a fixed reverse voltage of −1.2 V. It can clearlybe observed that, for both sets of devices, with and without Alimplant, the junction leakage current is comparable.

IV. CONCLUSION

Segregation of Al introduced by ion implantation and ger-manosilicidation results in lowering of RC at the NiSiGe/p+-

SiGe interface. P-channel FinFETs with Al-segregated NiSiGe/p+-SiGe S/D junctions were fabricated and shown to have ap-proximately 25% lower RSD than devices without Al implant.Al implant and segregation enhances IDSAT by ∼29% for p-FinFETs with a gate length LG of 105 nm, without degradingthe NiSiGe film morphology or SCEs.

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Mantavya Sinha (S’09) received the B.Tech. degree(first-class honors) in electrical engineering from theInstitute of Technology, Banaras Hindu University,Varanasi, India, in 2003. He is currently working to-ward the Ph.D. degree in electrical engineering withthe National University of Singapore, Singapore.His thesis is based on interface engineering at themetal–semiconductor junction between silicide con-tacts and doped source/drain region of MOSFETsfor parasitic contact resistance reduction in multiple-gate FETs.

His research interests include device and material physics, and processtechnologies for sub-22-nm CMOS technology nodes.

Rinus Tek Po Lee (S’06) received the B.Eng.and M.Eng. degrees in electrical engineering andapplied physics from the National University ofSingapore (NUS), Singapore, where he is currentlyworking toward the Ph.D. degree in electrical engi-neering, with research focus on parasitic resistancescaling in multiple-gate transistors in NUS, underProf. Y.-C. Yeo and Dr. D. Z. Chi.

He was with the Agency of Science Technologyand Research, Institute of Materials Research andEngineering, Singapore, where he worked on the

development of advanced process technologies for contact metallization. Since2005, he has been with the Silicon Nano Device Laboratory, NUS. He hasauthored or coauthored 76 journals and conference papers. He is the holderof two U.S. patents. His current research interests include device physics andprocess technologies for the multiple-gate transistor architecture.

Mr. Lee was the recipient of the Marubun Research Promotion FoundationGrant at the 2006 Solid State Devices and Materials Conference, Yokohama,Japan; the Taiwan Semiconductor Manufacturing Company (TSMC) Outstand-ing Student Research Gold Award in 2007; the First Prize for OutstandingPerformance in the 2008 TSMC Internship Program; and the European Materi-als Research Society Graduate Student Award and the IEEE Electron DevicesSociety Ph.D. Student Fellowship Award in 2009.

Eng Fong Chor (S’79–M’90–SM’03) receivedthe B.Eng. degree (First-Class Honors) from theUniversity of Singapore, Singapore, in 1980, theM.Eng. degree from the National University ofSingapore (NUS), Singapore, in 1984, and thePh.D. degree from the University of Southampton,Southampton, U.K., in 1986. During her M.Eng.candidature, she was with the Fraunhofer Institut fürFestkörpertechnologie (Fraunhofer Institute forSolid-State Technologies), Munich, Germany,working on semiconductor device characterizations

and technologies, for a period of nine months.She is currently an Associate Professor with the Department of Electrical

and Computer Engineering, NUS. From 1989 to 1992, she was involved inthe ASEAN Australia Economic Development Project as the MicroelectronicProjects Coordinator for NUS. During her sabbatical leave from November1993 through June 1994, she was a Consultant with AT&T Bell Laboratories,Murray Hill, NJ, where she conducted work on the contact metallurgicalstability and reliability of heterojunction bipolar transistors. She is the author ora coauthor of more than 100 journal and conference papers. She is a coholderof five U.S. patents. Her current research interests are in the areas of metalcontact to semiconductors and carbon nanotubes and the design, fabrication,characterization, and modeling of semiconductor devices-heterojunction bipo-lar transistors and high-electron-mobility transistors.

Prof. Chor has served the IEEE in various capacities, including as the Secre-tary and Treasurer of the IEEE Singapore Section Executive Committee from1987 to 1994 and as the Secretary of IEEE Region 10 Executive Committeefrom 2001 to 2002.


Yee-Chia Yeo (S’98–M’02) received the B.Eng.(first-class honors) and M.Eng. degrees in electri-cal engineering from the National University ofSingapore (NUS), Singapore, and the M.S. and Ph.D.degrees in electrical engineering and computer sci-ences from the University of California, Berkeley.

He worked on optoelectronic devices at theBritish Telecommunications Laboratories, U.K., andon CMOS technology at Berkeley. In 2001–2003,he worked on exploratory transistor technologieswith Taiwan Semiconductor Manufacturing Com-

pany, Hsinchu, Taiwan. He is currently an Assistant Professor of electrical andcomputer engineering with NUS and a Research Program Manager with theAgency for Science, Technology, and Research (A*STAR), Singapore. He leads

a team working on strained-channel transistors, high-mobility devices, contactresistance reduction technologies, and devices with steep subthreshold swing atNUS. He has authored or coauthored 340 journal and conference papers, and abook chapter. He is the holder of 82 U.S. Patents.

Prof. Yeo served on the IEEE International Electron Devices MeetingSubcommittee on CMOS Devices in 2005–2006. He was the recipient of the1995 IEE Prize from the Institution of Electrical Engineers, U.K.; the 1996Lee Kuan Yew Gold Medal; the 1996 Institution of Engineers Singapore GoldMedal; the 1997–2001 NUS Overseas Graduate Scholarship Award; the 2001IEEE Electron Devices Society Graduate Student Fellowship Award; the 2002and 2008 IEEE Paul Rappaport Awards; the 2003 TSMC Invention Award; the2006 Singapore Young Scientist Award; the 2006 Singapore Youth Award inScience and Technology; the 2008 National Research Foundation Fellowship;and the 2008 NUS Young Researcher Award.

Contact Resistance Reduction Technology Using Aluminum Implant and Segregation for Strained...

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