Contact effects in pentacene field effect transistorsrx916061f/fulltext.pdfIn addition to the...

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Contact effects in Pentacene Field Effect Transistors

Dissertation written by Erfan Kheirkhahi as a partial requirement for degree

of:

Doctor of philosophy

in the field of

Electronic Circuits and Semiconductor Devices

Supervisor: Prof. Nicol McGruer

Department of Electrical and Computer Engineering

Northeastern University

August 2015

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I dedicate this dissertation to my parents, Mahmoud Kheirkhahi and Eghbaleh Separraz,

my brother, Alireza Kheirkhahi and my wife Nazanin Mokarram, without whom I would

have not been able to complete this work

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Abstract

Organic electronic devices have gotten more attention over the two past decades

due to low manufacturing cost and complexity. Besides these advantages, using organic

semiconductors to fabricate electronic devices opens the manufacturing branch of flexible

electronics. Having devices fabricated on the flexible substrates offers a wide variety of

devices such as implantable biosensors, wearable solar panels as well as flexible e-papers

and displays. We can divide organic devices into three main categories of Organic

Photovoltaic (OPVs), Organic Light Emitting Diodes (OLEDs) and Organic Field Effect

Transistors (OFETs). The focus of this dissertation is on OFETs and more specifically on

pentacene field effect transistors.

Pentacene is one of the widely investigated p-type organic semiconductors in the

literature. Carrier mobility is one of the important figures of merit of any organic

transistor and so far transistors fabricated using pentacene have shown higher carrier

mobilies (up to 10 cm2/Vs) compared to those of other p-type organic transistors. Besides

high carrier mobility, enhanced solubility of derivatives of pentacene further reduces the

manufacturing cost and complexity.

Although pentacene carrier mobilities are higher than those of many other p-type

organic compounds, the transistor itself may still limit the effective carrier mobility. The

effective carrier mobility refers to an extracted number from the experimental

characteristic of transistors fabricated using pentacene. One of the major contributors in

the reduction of effective carrier mobility is the effect of the contact. Two main

contributors of contact effect are 1) the energy barrier at semiconductor-metal junction

(more specifically at source-pentacene junction) and 2) the change of film morphology

(including formation of voids) at the interfaces.

This dissertation focuses on the effect of the energy barrier at the semiconductor-metal

junction in pentacene transistors.

To quantitatively extract and analyze the effect of the contact, a novel method of Kelvin

probing is introduced and investigated. This method, while involving simple fabrication

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and measurement procedures, offers the extraction of voltage drops at the drain and

source interfaces.

To demonstrate the validity of the method as well as the existence of an energy barrier at

the metal-pentacene interface, systematic measurements are done by modulating the

metal-pentacene barrier height in pentacene transistors. For this work IrO2, Au, RuO2

and Ti metals with respective reported work functions of 5.6 eV, 5.1 eV, 4.6 eV and 4.3

eV are used.

Furthermore to accurately extract the voltage drop at the contacts using the Kelvin

devices, 2D electrostatic simulation is done which includes the perturbation by the

intermediate pads of the electric field along the channel. Consequently, to extract the

voltage drops at the contacts, this simulation is used along with the experimental

observations. One may use similar approach to analyze the effect of contacts for other

organic/inorganic metal-semiconductor junctions as well.

The results not only demonstrate the validity of the method but also show the

existence of an energy barrier at the source-pentacene interface. In this work it is shown

that the barrier in the pentacene transistors exists only at the source-pentacene interface, it

is not just a resistance and it is the function of metal work function.

The Kelvin probing analysis done suggests that for an applied drain-source voltage, a

considerable voltage drop exists at the source-pentacene interface when RuO2 and Ti

metals are used. On the other hand, devices made using Au and IrO2 show small or no

voltage drop respectively. Furthermore according to this analysis, the reason for

observing a low effective carrier mobility of 0.006 cm2/Vs for transistors made using

RuO2 metal compared to the effective carrier mobility of 0.08 cm2/Vs and 0.1 cm

2/Vs for

Au and IrO2 can be explained.

In addition to the quantitative analysis of the voltage drops at the barriers, for the first

time the I-V behavior of a metal-pentacene barrier (reversed biased metal-pentacene

junction) in a pentacene field effect transistor is extracted. This I-V behavior shows a

linear dependency of the current on the voltage drop at the contact. Therefore as the

current density increases, the voltage drop at the contact increases as well. Hence one

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needs to address this effect for short channel devices in which higher current densities

exist for a given applied voltage compared to that of long channel devices.

Furthermore, the linear IV behavior of the barrier shows that the charge conduction

mechanism at the metal-pentacene junctions cannot be explained by an ideal Schottky

barrier model and it appears to be dominated by trap assisted tunneling.

In addition to the investigation of the contact barrier in the pentacane transistors,

field effect transistors are fabricated using a very thermally stable pentacene (TTPO).

This pentacene derivative is electrically stable up to 200 ºC. The devices fabricated using

TTPO show a transistor behavior similar to that of conventional FET. The effective

extracted carrier mobility of TTPO transistors is 10-9

cm2/Vs at room temperature. As

temperature increases, the effective carrier mobility of devices increases as well and

eventually at 200 ºC it reaches to 9×10-9

cm2/Vs. This implies that the TTPO transistors

not only are thermally stable but also that the conductivity of this material increases as

temperature increases.

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Table of Contents

1. Introduction ................................................................................................................... 13

2. General background on organic semiconductor devices .............................................. 15

2.1 Introduction to organic devices ............................................................................... 15

2.2 Organic versus inorganic electronics ...................................................................... 16

2.3 Organic thin film transistors .................................................................................... 17

2.4 Brief introduction to other organic devices ............................................................. 18

2.4.1 Photovoltaic ...................................................................................................... 18

2.4.2 Light emitting diodes ........................................................................................ 18

2.5 Degradation of performance in organic devices ..................................................... 19

2.6 Current market demand of organic devices............................................................. 20

2.7 Device theory for organic field effect transistors .................................................... 21

2.7.1 Field Effect Transistors – Principle of operation .............................................. 24

2.7.2 Device structures of organic field effect transistors ......................................... 29

2.8 Charge injection/transport in organic transistors .................................................... 31

2.8.1 Charge injection in pentacene transistors ......................................................... 32

2.8.2 Charge transport in pentacene transistors ......................................................... 35

2.8.3 Space charge limited (SCL) current in organic diode versus transistor

configuration .............................................................................................................. 37

2.9 Extraction of voltage drops at the contacts ............................................................. 39

2.10 Organic transistors – performance development ................................................... 41

2.10.1 Effect of coating methods of organic semiconductor on the electrical

performance ............................................................................................................... 43

2.10.2 Effect of gate dielectric material on effective carrier mobility ...................... 44

2.10.3 Effect of electrodes and surface treatments .................................................... 45

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3. Device fabrication ......................................................................................................... 49

3.1 Sputtering recipes .................................................................................................... 54

3.2 Oxidation step on Ru and Ir metals ......................................................................... 56

3.3 Coating method of pentacene layer – Evaporation and spin coating ...................... 56

3.4 Design criteria for the optical mask ........................................................................ 57

4. Measurement methods .................................................................................................. 61

4.1 Electrical measurement methods ............................................................................. 61

4.1.1 Standard transistor (three terminals) measurements ......................................... 61

4.1.2 Electrical parameter extraction ......................................................................... 63

4.1.3 Four terminals measurement – Kelvin probing ................................................ 66

4.1.4 Temperature measurements .............................................................................. 69

4.2 Non-electrical measurement methods ..................................................................... 69

5. Transistors fabricated using novel pentacene derivatives ............................................. 70

5.1 Water soluble pentacene.......................................................................................... 70

5.2 TTPO – thermally stable pentacene ........................................................................ 72

6. Effect of metal-organic semiconductor interface – Experimental and modeling ......... 75

6.1 Energy barrier versus film morphology at metal-semiconductor interface ............. 77

6.2 Investigation of metal-pentacene junction using Kelvin probe method .................. 78

6.3 Modeling of measurements using COMSOL FEA analysis ................................... 89

6.4 Extraction of voltage drops at metal-semiconductor junctions using COMOSL

model ............................................................................................................................. 93

6.5 Current-voltage behavior of barriers (metal-semiconductor) in pentacene transistors

..................................................................................................................................... 104

6.6 Transistor characteristics of fabricated devices using various electrodes ............. 111

7. Discussion ................................................................................................................... 114

8. Conclusion .................................................................................................................. 120

Appendix A: .................................................................................................................... 123

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References: ...................................................................................................................... 127

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Table of Figures

Figure 1. Schematic of bottom gate field effect transistor. ............................................... 17

Figure 2. Planar and bulk heterojunction solar cells. ........................................................ 18

Figure 3. NMOS and PMOS - Device structures[10]. ...................................................... 21

Figure 4. Leakage paths[15]. ............................................................................................ 24

Figure 5. Transistor in inversion mode. ............................................................................ 25

Figure 6. Mode of operation of a transistor. ..................................................................... 26

Figure 7. Structures of Organic transistors[21]................................................................. 30

Figure 8. Au-pentacene interface[27]. .............................................................................. 33

Figure 9. PFOT treated electrodes - pentacene interface[27]. .......................................... 33

Figure 10. Pentacene-Au junction - treated versus untreated junction[29]. ..................... 34

Figure 11. Energy level diagram - Au-pentacene and Graphene-pentacene junction[30].35

Figure 12. Total resistance as a function of channel length[42]. ...................................... 39

Figure 13. Contact resistance extraction using four-point probe method[43]. ................. 41

Figure 14. Comparison of carrier mobility of organic materials[44]. ............................... 41

Figure 15. Cross-section of fabrication steps using double layer lift off. ......................... 52

Figure 16. Sidewall effect of using single layer PR process............................................. 53

Figure 17. Patterned wafer fabricated with optical mask. ................................................ 57

Figure 18. Typical electrodes (source/drain) structure of organic transistors. ................. 57

Figure 19. Electric field distribution on a 2D plane. ......................................................... 58

Figure 20. IDS-VDS behavior of transistor with gate leakage current. ............................... 59

Figure 21. Enclosed devices. ............................................................................................ 60

Figure 22 – Designed Kelvin structures on the optical mask ........................................... 60

Figure 23. DC characteristics of a FET – Left: Output characteristic; Right- Transfer

characteristic. ............................................................................................................ 62

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Figure 24. (a) Transfer characteristic (b) Output characteristic[52]. ................................ 64

Figure 25. Effect of contact at low drain-source voltages. ............................................... 65

Figure 26. Carrier mobility extraction. ............................................................................. 66

Figure 27. 4 point probe Labview program. ..................................................................... 68

Figure 28. (a) thin film of WSP on Au electrodes and Silicon dioxide gate insulator, (a)

from water solution, (b,c) EtOH, (d) Electrical response of thin film WSP

transistors. ................................................................................................................. 71

Figure 29. Optical image of a coated device with TTPO. The yellow areas are Cr/Au

electrodes. ................................................................................................................. 72

Figure 30. Transistor behavior at Vgs= -50 V. ................................................................. 73

Figure 31. Carrier mobility versus temperature. ............................................................... 73

Figure 32. Device structure used for Kelvin measurement. .............................................. 79

Figure 33. Energy level of pentacene interfacing metals (a) Ti or RuO2 (b) Au or IrO2 .

................................................................................................................................... 80

Figure 34. Barrier expected based on the theoretical energy levels and applied bias (a) Ti

or RuO2 (b) Au or IrO2.............................................................................................. 82

Figure 35. 4-point probe measurement done in transistor fabricated using RuO2 metal. . 83

Figure 36. 4-point probe measurement done in transistor fabricated using Ti metal. ...... 84

Figure 37. 4-point probe measurement done in transistor fabricated using Au metal. ..... 85

Figure 38. 4-point probe measurement done in transistor fabricated using IrO2 metal. ... 86

Figure 39. Proposed metals that result in no-barrier at source-pentacene interface for

transistor application. ................................................................................................ 87

Figure 40 Experimental data of Kelvin probing of transistors fabricated using IrO2 metal,

blue arrows show the expected voltage drops........................................................... 88

Figure 41. Energy barriers in 4-point devices. .................................................................. 90

Figure 42. Electrostatic simulation considering the effect of measurement pads. ............ 92

Figure 43. Simulation of devices with resistive area added to the intermediate pads. ..... 93

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Figure 44. Measurement data of transistors with Kelvin probes that are fabricated using

RuO2 electrodes versus 2D simulation. .................................................................... 95

Figure 45. Extraction of voltage drops at contacts. ......................................................... 96

Figure 46. Extracted voltage drops for transistors made with RuO2. ............................... 97

Figure 47. (Left) Measured data of transistors fabricated using Ti, (Right) Extracted

voltage drops at interfaces. ....................................................................................... 98

Figure 48. Measurement data of Au electrodes versus 2D simulation. ............................ 99

Figure 49. Extracted voltage drops for transistor made with Au. ..................................... 99

Figure 50. Measurement data of IrO2 electrodes versus 2D simulation. ........................ 100

Figure 51. Extracted voltage drops for transistor made with IrO2. ................................. 101

Figure 52. Comparison of voltage drops at source/drain-pentacene interface using

different metals. ...................................................................................................... 102

Figure 53. Extracted voltage drops at metal-pentacene interfaces for transistors made

using RuO2. ............................................................................................................. 104

Figure 54. Metal-pentacene junction represented with forward and reversed biased

barriers. ................................................................................................................... 105

Figure 55. IV behaviors of current density using different conduction mechanism. ...... 107

Figure 56. Current-voltage behavior of source-pentacene barrier when RuO2 metal is

used. ........................................................................................................................ 108

Figure 57 – Expected reversed biases metal-semiconductor junction solely due to

thermionic emission of carriers versus extracted IV behavior of metal-pentacene

barrier ...................................................................................................................... 109

Figure 58. Current voltage behavior of reversed biased Au-pentacene barrier versus

RuO2-pentacene barrier. .......................................................................................... 110

Figure 59. Electrical characteristic of transistors fabricated using Au ........................... 111

Figure 60. Electrical characteristic of transistors fabricated using IrO2. ........................ 112

Figure 61. Three terminal behavior of devices fabricated using RuO2........................... 113

Figure 62. Three terminal behavior of devices fabricated using Ti. ............................... 113

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Figure 63. IDS-VDS behavior of transistors at low drain-source voltages for (a) transistors

made using Au (b) transistors made using IrO2, (c) transistors made using RuO2. 117

Figure 64 – IV behavior of reverse biased metal-pentacene junction in pentacene field

effect transistors ...................................................................................................... 118

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1. Introduction

The idea of incorporating organic oligomers and polymers for device applications

came from the fact that the manufacturing cost of these devices is lower than that of

inorganic devices. As an example, it’s been estimated by [1] that the manufacturing cost

of organic solar cell panels will be reduced from $400/ft2 in the case of silicon PV panels

to at most $150/ft2 for the organic PV panels. Moreover, the possibility of making these

devices on the flexible substrates is another motivation toward this branch of device

manufacturing. The flexibility of devices is an advantage where space saving, flexibility

or production constraints limit the usability of the rigid devices.

The three major applications of organic materials are Organic Light Emitting Diodes

(OLEDs), Organic Field Effect Transistors (OFETs) and Organic Photovoltaics (OPV).

From the manufacturing perspective, this branch introduces the novel idea of flexible and

printable electronics. From the device perspective each application in organic electronics

has its own pros and cons. The main motivation for development of organic electronic

devices is low manufacturing cost. Other advantages are:

Mechanical flexibility

Printability of organic layers; hence large scale manufacturing

The two main applications of OLEDs are in full color displays and lighting. Although

organic LEDs are somewhat industrialized nowadays, there are still challenges in this

field. Improving the performance stability, efficiency and generating white light are the

important ones.

Another application of organic materials is in the transistor domain so called OFETs.

Two potential applications of OFETs are in electronic tags (used in banks, telephone

cards, products) and flat panel displays.

Besides the advantages of using organic devices, still more work needs to be done to

resolve the challenges exist in this field. In organic photovoltaics as well as OFETs and

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OLEDs, the main challenges are low efficiency (low carrier mobility in OFETs) as well

as the performance stability of the devices over time.

The future of this branch of electronics and overcoming the challenges of this

field are tied to three domains: Materials, device theory/models, and experimental

observations.

From the material perspective there should be a track of making new materials.

One of the concerns that should be addressed in new materials is the performance

persistency of the materials over time and various environments (i.e. humid environment,

non-vacuum environment and heated/cold environment).

Meanwhile from the device theory perspective there should be an in-depth understanding

of the electrical behavior of devices. Clearly, for this new generation of electronic

devices there should be well-established concepts and models. This indeed helps the

engineers to incorporate these models to design applicable and reliable devices.

Understanding the behavior of devices is also tied to understanding the experimental

data. Therefore systematic experiments need to be done to get more insight about the

device behavior.

As will be explained later, one of the main factors influencing the electrical

performance of organic transistors is the effect of contacts. As will be explained in detail

later, effect of contact refers to phenomena happening when a metal interfaces with the

organic materials. This effect exists in all organic devices and affects the electrical

performance of the devices. The focus of this dissertation is to understand this effect for

pentacene field effect transistors by having systematic experiments as well as

simulations.

Moreover as a collaborative work with the chemistry department of University of New

Hampshire, for the first time two novel derivatives of pentacene are introduced.

Pentacene is a well-known p-type organic semiconductor that has been vastly

investigated in literature. One of the introduced novel materials is a thermally stable

pentacene derivative that does survive up to 200 °C and the other material is a water

soluble pentacene. The applicability of each of these compounds will be explained later.

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2. General background on organic semiconductor devices

2.1 Introduction to organic devices

For the past forty years, inorganic semiconductors such as silicon, insulators such

as silicon dioxide and different metals have been the backbone of the semiconductor

industry. So far inorganic technology has shown outstanding performance for various

industrial and consumer electronic applications. Inherently this technology has its own

limitations such as scaling issues, rigidity of the devices, cost and complexity of the

manufacturing. From the device perspective, engineers and scientists are investigating

other possible ways to make devices and circuits to solve these problems. One of the

alternative way introduced more than three decades ago is using organic materials to

make electronic devices.[2]

The idea of synthesizing organic semiconductors was first introduced in the 1940s.[3]

Later, during the 1980s, the novel concept of using organic semiconductors in electronic

devices was introduced. After developing the idea of using organic semiconductors in

electronics application, in the 1990s for the first time the Friend group at the Cambridge

University published the first polymer based organic LEDs. Following that in the 2000s

for the first time the conductive polymers were discovered and developed by Heeger et

al. which won the Noble prize.[4]

The earliest organic materials synthesized are Alq3 (8-hydroxyquinoline aluminum), PPV

(poly p-phenylenevinylene) and PT (polythiophene). These synthesized organic materials

later got attention to be used in OLEDs and field effect transistors.[5]

Unfortunately so far the electrical performance of all device types manufactured using

various organic materials are tied to their limitations. Some of these limitations are

addressed later in this chapter.

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2.2 Organic versus inorganic electronics

As already mentioned above, currently the electrical performance of inorganic

transistors and solar cells is substantially higher than that of organic transistors and solar

cells. This however is not true for OLEDs in which cost and performance of them are in

tight competition to that of inorganic LEDs.[6]

From the transistor perspective the electrical performance is referred to the carrier

mobility (hence the switching speed) of the transistor. Switching speed of a transistor

refers to the time that takes for the transistor to go from “fully OFF” state to “fully ON”

state. The former case is also called cut-off mode and the latter case called saturation

mode.[7] To be able to find the switching speed we need to know the time it takes for the

carrier to cross the channel. The following equation shows the time needed for a carrier to

move along a channel with length ‘L’ under the application of electric field ‘E’, is

inversely proportional to the carrier mobility ‘µ’. [8]

Equation 1

Higher carrier mobility results in a higher carrier velocity and hence higher switching

speed. However, so far all organic transistors suffer from the low carrier mobility. This is

the main reason that the organic transistors are not applicable where high switching speed

matters. Even incorporating the organic transistors in applications where lower switching

speed is needed, is undesirable due to performance degradation of transistors over time.

In summary although the field of organic electronics faces challenges that should

be addressed and resolved by the researchers, low manufacturing cost is still the main

motivation for research communities working in this field.

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2.3 Organic thin film transistors

The principle of operation of the transistors is discussed in section 2.7 of this

thesis in detail. Any transistor has three terminals so called gate, source and drain

electrodes. In short, if a sufficiently high voltage is applied to the gate of a transistor

(with respect to source electrode), a conducting channel along the source and drain region

will be formed.

Depending on the application, the conducting channel can be un-doped or doped (p-type

or n-type) semiconductor. In p-type semiconductors the majority carriers are holes while

in n-type materials the majority carriers are electrons. In the case of either n-type or p-

type materials, at equilibrium the lattice is not negatively/positively charged. The

difference between doped and un-doped semiconductor is the level of electrical

conductivity that the semiconductor has due to the number of quasi-free carriers.

So far out of all available organic semiconductors, the number of synthesized p-type

materials is higher than that of n-type materials.

The fabrication methods for organic transistors are investigated later in this chapter. It is

worth here to say that for using the organic material (either n-type or p-type) the channel

is formed in a thin layer of organic semiconductor coated on the gate dielectric as shown

in Figure 1. Depending on the material used, the organic transistor can act as a p-type or

n-type transistor.

Figure 1. Schematic of bottom gate field effect transistor.

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2.4 Brief introduction to other organic devices

2.4.1 Photovoltaic

A photovoltaic cell is a specialized semiconductor diode that converts light

into electricity. Upon absorption of a photon in a molecule, an excited state, called an

exciton, is formed. This excited state is regarded as the electron-hole pair. In the

photovoltaic cell this electron-hole pair is broken due to the effective electric field at the

interface. The effective electric field breaks the excitons by causing the electron to fall

from the conduction band of the absorber to the conduction band of the acceptor

molecule.

Organic thin-film solar cells have not yet been commercialized but they are being

intensively investigated in laboratories. As already mentioned the current challenges in

this field are the stability (lifetime) and limited efficiency of the cell. [9]

Figure 2. Planar and bulk heterojunction solar cells.

2.4.2 Light emitting diodes

Organic light emitting diodes (OLEDs) are electronic devices made by placing a

thin film of an electroluminescent organic material between two conductors of different

work functions. When an electrical voltage is applied, electrons and holes are injected

into the electroluminescent material. When these carriers recombine, light is emitted.

Additional thin film layers are usually added for different purposes such as electron and

hole transport. The stability issues of the cells are as challenging as that of other organic

devices. Typically encapsulation methods are used to prevent the diffusion of oxygen

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molecules and water vapors into the cell. In the next section various causes of

performance degradation of organic devices are explained.

2.5 Degradation of performance in organic devices

There are three major degradation reasons in the organic devices. One is the

diffusion of the oxygen and water molecules in the device. Another is the degradation of

the material due to UV light illumination. A third is the effect of the environmental

temperature on the devices. These three effects exist in any type of organic devices.

One way to increase the stability of the organic devices is to use a protective

encapsulation. Another way is to add Fullerene to the compound and due to its high

stability it enhances the lifetime of the material.

Even if the material itself is resistant to the oxidation phenomena, the oxygen molecules

can result in the surface oxidation of the electrodes. This interface oxide can hinder the

electric conduction and make the charge collection more difficult.

At the elevated temperature the degradation in the device can be caused by the

decomposition of the material. In the layered devices such as OPVs or OLEDs, higher

temperature results in the diffusion of the molecules of any layer into others. This change

in morphology is irreversible.

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2.6 Current market demand of organic devices

According to a market report published by Transparency Market Research the

global organic electronics market is expected to be worth $44.8 billion in 2018. The

market growth will include non-volatile memories, OLED devices and OPVs.[9]

Currently among all the applications of the organic devices, OLEDs accounts for the

greatest share of sales. Although currently the market of OLEDs is in displays,

Nanomarkets sees demand for OLED lighting market reaching $6.4 billion in 2016. Other

applications including transistors, sensors and photovoltaics will also make a growing

contribution to the market of organic electronics.

As already mentioned, low cost and printability of manufacturing are the motivations

toward using organic devices. Current electronic devices are produced by complex and

costly process that entails cycles of deposition, etching, and removal on rigid substrates.

In contrast organic electronics are based on small molecules and polymers. These

materials can be made as inks and printed on any substrate. Current electronic devices

available in the market such as OLEDs are produced by vapor deposition of the small

molecules. As stated by Nanomarkets “There is a need for new and better inks that will

support organic electronics within the context of functional printing, or at least for useful

coating processes such as spin coating.”

The leading players of the organic electronics market are BASF Future Organization,

GmBH, Ciba Specialty Chemicals Holding Inc., Corning Incorporated, Eastman Kodak

Firm, Merck KGaA, OSRAM GmbH and Samsung SDI Co.,TDK Corporation, Tohoku

Pioneer Corporation, AGC Seimi Chemical Co., Ltd, Aixtron AG, Cambridge Display

Technologies Ltd., E Ink Corporation, eMagin Corporation, H.C. Starck GmbH, Poly-

Optical Products, Inc., Plastic Logic, Seiko Epson Corp., and Univision Technology Inc.

[9]

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2.7 Device theory for organic field effect transistors

Structures of a top-gate PMOS and NMOS inorganic field effect transistors are

shown in Figure 3.[10] The structures consist of a substrate/channel material (in this case

silicon), source and drain regions that are typically highly doped, the metallic contacts for

the source, drain and gate electrodes. In addition to these electrodes there is an insulating

layer that is often a silicon dioxide layer. The gate electrode is often silicon/poly-silicon

although metals can be used as well. Later on possible structures of organic field effect

transistors are shown. Since the electrical conduction is controlled using these four

electrodes (gate, source, drain and substrate terminals), the field effect transistor is a four

terminal device. Sometimes the field effect transistor is said to have only three terminals.

This refers to a condition when the source and substrate terminals are connected together,

or when there is no substrate connection.

Figure 3. NMOS and PMOS - Device structures[10].

One of the most important design parameters for circuit designers is the aspect ratio of

the transistors. The aspect ratio is the ratio of the width of the channel to the length of the

channel. The distance between the source and drain electrodes is called channel length

and the extension of these electrodes is called channel width.

Based on the channel type, field effect transistors can be divided into two groups of p-

channel and n-channel transistors. The n-channel FET is made on p-type substrate and the

p-channel FET is made on n-type substrate. The reason for this selection is that there

should be no channel formation when there isn’t any gate electrode. This means that for

the n-channel transistor the channel between source and drain electrode needs to be

formed in the p-type substrate upon the application of the gate voltage. In a p-doped

substrate the electrons (n- type carriers) are only minority carriers and before the

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application of the gate voltage there is no n-channel formed across the source-drain

electrodes. Similarly for the p-channel transistors the substrate should be an n-type. P-

type channel should be formed in the substrate upon the application of the gate voltage.

The source and drain regions are n-type in the case of n-channel FETs and p-type in the

case of p-channel FETs. These regions can be highly doped for efficient charge carrier

injection/collection.

Furthermore each of n/p-channel transistors can be enhancement-type or

depletion-type FETs. The enhancement-type field effect transistors are in the cut off

mode with no electrical conduction when the gate voltage is zero. As the proper gate

voltage is applied, the channel will be formed and the transistor turns on.

In contrast the depletion-type transistors are conducting at zero gate voltage and the

transistor is ON. Increasing the gate voltage decreases the channel conductivity and

eventually can turn off the transistor. The pentacene transistors which are the focus of

this thesis show enhancement p-type FET behavior. The electrical characteristic of the

pentacene transistors will be discussed later in detail.

Generally in an enhancement field effect transistors, the current flows between source

and drain electrodes when the magnitude of the gate-source voltage is higher than the

threshold voltage. In the case of enhancement n-channel FETs, the gate-source voltage

and the threshold voltage both have positive values. To turn on an enhancement p-

channel field effect transistor, the gate-source voltage and threshold voltages should have

negative values. For the p-channel FET to turn on, the gate-source voltage should be

smaller than the threshold voltage (absolute value of the gate-source voltage should be

higher than the threshold voltage). [11]

Ideally, when the transistor is in the off state, there is no current flowing through

the channel and therefore the power dissipation of the device in this state is zero.

However in reality this is not valid and the transistor suffers from various leakage paths.

The leakage currents and their effect on performance are important hence it is worth

talking about leakage paths here.

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One of the possible leakage paths exits in transistors is by tunneling of electrons through

the oxide layer. This tunneling effect increases as the oxide thickness decreases.

Especially this type of leakage is an important phenomenon in the small-scale devices in

which the oxide thickness scales down to nanometer. To overcome this oxide leakage,

researchers have introduced high-K dielectrics. These dielectrics should have large K

(dielectric constant) and be able to have a good electrical insulation. Typical high-K

dielectrics are HfO2 (K~25), ZrO2 (K~25), TiO2 (K~80). [12]

Another type of leakage current is subthreshold leakage current. This leakage is a current

passing through the channel when the magnitude of the gate-source voltage is less than

the magnitude of the threshold voltage. This means that the transistor should be in the off

state but still some current is sensed at drain-source electrodes. As the magnitude of the

threshold voltage shrinks the effect of the subthreshold current will be more apparent.

The other possible current leakage path is when the channel length reduces. This effect is

so called the short channel effect. The reduction in the channel results in high-induced

electric field. This high electric field can cause a physical damage at the interface of the

channel-electrodes. The damage results in mobility degradation and shift of the threshold

voltage.[13, 14]

In addition, this high electric field can cause hot carrier injection phenomena (HCI). This

effect happens when the carrier (holes or electrons) having sufficient energy to overcome

the silicon dioxide barrier and penetrate to this layer. The term ‘hot’ refers to the effective

temperature used to model the carrier density and not the temperature of the device. This

issue can shift the threshold voltage and sometime this shift can cause the device to never

go to the OFF state.

Now let’s consider a nano-scale transistor in the OFF-state and the ON-state as shown

below. In the OFF-state of the transistor, the main types of leakage currents are shown.

The GIDL (Gate Induced Drain Leakage) leakage is a current between drain and

substrate due to high electric field between gate and drain. When the FET is in the

standby mode the drain terminal is connected to the power supply while the gate is

24

grounded. This can induce a high electric field hence unwanted current conduction. Also

as we know there are p-n junctions between source/drain and substrate. In the case of the

reverse bias, this junction will conduct and results in a leakage current. This leakage

current is known as BTBT (Band to Band tunneling) current. [15]

Figure 4. Leakage paths[15].

These current leakages increase the power consumption of the transistor even in the OFF

state. Ideal FET should dissipate no power while it is in the OFF state. Figure 4(a) shows

that as the transistor scales down, the OFF state current increases. This is in contrast with

the required properties of a transistor.

Also as the transistor scales down the contact resistances become more significant and

they result in the reduction of the ON current. The contact resistance, as its name implies,

is a resistance at the interface of the metal and the semiconductor. In a conventional FET

the contact resistance has negligible effect on the channel resistance but as the device

scales down the effect of this resistance becomes more significant on the overall

electrical behavior.

2.7.1 Field Effect Transistors – Principle of operation

As already mentioned the transistor operation is based on the applied voltages at

the electrodes. In other words the operation is based on the voltage differences across the

electrodes. These voltages control the conductivity of the channel. These potential

differences are VDS (voltage difference between drain and source terminals) and VGS

(voltage difference between gate and source terminals).

25

To be more specific, let’s consider an n- type field effect transistor. As mentioned earlier

to have an n-type transistor operation, the channel formed across the source-drain

electrodes should be n-type (electron conduction). Initially if the positive voltage is

applied at the gate-source electrodes, this voltage repels the positive charges at the

interface of the insulator-semiconducting channel. This will happen at VGS<VT (VGS and

VT are both positive quantities). This results in the depletion of the channel from the

positive charges (holes). If VGS increases (VGS>VT) the channel becomes inverted

meaning that the electrons become induced at the interface of the insulator and the

semiconducting channel. A schematic of the inversion mode is shown below.[16]

Figure 5. Transistor in inversion mode.

In this case the channel is formed and also inverted. The transistor can start its operation.

The explanation mentioned above is also valid for p-channel transistors with the

difference that the p-channel should be formed in n-type substrate. Upon the application

of a negative gate voltage the channel will be depleted from the electrons (VGS>VT; VGS

and VT are negative quantities) and further decrement of the gate voltage (VGS<VT) will

invert the channel hence holes will be induced at the interface of the insulator and

semiconducting channel.

Any transistor (p-channel or n-channel) has three modes of operation. Charge

accumulation, depletion of the channel and channel inversion.

The accumulation mode is when the gate voltage attracts the charges from the substrate to

the insulator interface. In the case of the n-channel transistor, the negative gate voltage

attracts holes existing in the p-type substrate to the insulator interface. Similarly in the

case of the p- channel transistor the positive gate voltage attracts electrons to the insulator

interface. In the accumulation mode the transistor stays in the off state.

26

The depletion mode is when the gate voltage depletes the channel of carriers. Further

increment of the magnitude of the gate voltage induces minority carriers of the substrate

to the insulator interface. This mode is so called an inversion mode.

Now assume that the channel has been formed and the transistor is ready to operate

(transistor is ON). The transistor operates in different phases of electrical conduction.

These phases are so called as the sub-linear region and saturation region. The curvature

of the IDS-VDS characteristic is the reason that the first region is called sub-linear IV

behavior. Also at saturation region as its name implies the drain-source current is at its

maximum value and cannot be increased anymore unless the gate-source voltage

changes. Figure 6 shows the I-V characteristic of a typical transistor and its operating

regions. [17]

Figure 6. Mode of operation of a transistor.

Notice that the current and voltage axes are absolute values. This means that the behavior

of the n-channel and p-channel transistors is similar and the only difference is that the

current and voltage values in the p-channel transistors are negative. Therefore the I-V

characteristic of an n-channel transistor is in the first quadrant of the IDS-VDS coordinate

and for the p-channel transistor is in the third quadrant of the I-V coordinate.

27

For the transistor to operate in the sub-linear region the following should hold.

Equation 2

In this region for lower magnitude of the drain-source voltages the current varies linearly

with the drain voltage. It can be deduced from the above equation that for the transistor to

operate in the saturation region the following general expression should hold:

Equation 3

The conditions mentioned above are valid for both the n-channel and p-channel

transistors. To be able to drive the current-voltage equation we should start by finding all

the parameters influencing the current passing along the source and drain electrodes. In

simple terms the current across the channel is the number of charges passing a given area

per unit time. Mathematically the current would be ID= -W Qch(y) v(y) in which W is the

channel width, Qch is the charge across the channel as the function of the channel length

and v is the carrier velocity as the function of the channel length. The “y” in the equation

represents the current direction from the source electrode to the drain electrode. The

reason for the negative sign is that in the case of the p-channel transistor in which the Qch

is positive if we apply negative voltage to the drain electrode and ground the source

electrode, the direction of the current will be from source to drain. This means that the

drain to source current should have a negative sign implicating the reverse direction of

the current. Similarly in the case of the n-channel transistors, in which the Qch is negative,

if we apply positive voltage to the drain electrode and ground the source electrode the

direction of the current is from drain to source. Therefore in the case of the n-channel

transistor the negative sign in the equation should exist to have a positive drain-source

current. The drain current equation mentioned above is a general equation for any type of

FET.

As the pentacene field effect transistors show p-channel transistor behavior, rest of the

current equation derivation will be based on the p-channel FET. As already mentioned

the current equation for the transistor is: ID= -W Qch(y) v(y).

28

In this equation ‘v’ the carrier velocity is the product of the carrier mobility μ(y), and the

electric field along the channel εL(y). Substituting the equation for the carrier velocity

into the general current equation we find the channel current to be:

( ) ( ) ( ) Equation 4

To finalize the current equation we should find the equation for the charges along the

channel. As we may already know in a capacitor we have Q=CV in which ‘C’ is the

capacitance and the ‘V’ is the potential difference across the capacitor. Similarly the

charge in the channel is the product of the voltage difference across the channel and the

capacitance. The capacitance is the insulator capacitance and if the silicon dioxide is used

it is denoted as Cox. The voltage on the top electrode (gate electrode) is VSG-|VT| and on

the lower plate of electrode (channel) is VCH(y). The latter is the voltage between the

channel and ground. This voltage varies as the function of position ‘y’ along the channel.

Therefore the total voltage difference across the capacitor (COX) is (VSG-|VT|)-VCH(y).

Substituting in the general equation yields:

( ( )) ( ) ( ) Equation 5

The electric field ‘εL’ is the voltage difference over a distance

. The voltage

across the channel changes from VSD to zero. Also ‘y’ in the equation changes from 0 at

the source electrode to L (channel length) at the drain electrode. Therefore substituting

the formula for the electric field in the above equation and integrating the equation we get

the current-voltage equation for the p-channel field effect transistor as:

( )

Equation 6

This equation is known as the equation for the p-channel transistor in the sub-linear

region. To find the maximum possible value of the current (saturation region) presumably

all the VSG-|VT| voltage dropped along the channel. This means that VSD=VSG-|VT|.

Substituting this expression in the above equation results in the saturation region equation

as:

( )

Equation 7

29

All the mentioned equations assume gate independent field effect mobility and gradual

channel approximation. The carrier field effect mobility decreases as the magnitude of

the gate-source voltage increases. The reason for this decrement is that increasing the

magnitude of the gate-source voltage increases the transverse electric field into the

channel hence decreases the mobility of the carriers. [18] Also the gradual channel

approximation states that the rate of variation of the lateral field in the channel is much

smaller than that of the vertical field. In other words the channel potential varies slowly

along the channel. However as the channel length decreases the validity of this statement

is not often met.[19]

2.7.2 Device structures of organic field effect transistors

So far the conventional field effect transistor has been discussed. The remainder

of this section talks about the organic field effect transistors. Organic transistor refers to a

transistor that has an organic layer as the semiconducting channel. Figure 7 shows

possible configurations of organic transistors. The two configurations shown on top right

and bottom left of the figure are bottom gated structures and the other two structures are

top gated electrode. The ‘top’ refers to the position of the gate electrode with respect to

semiconductor layer. In general, the fabrication of the bottom-gate transistors is easier

than the top-gate transistors since a deposition step for another insulator is not needed.

In addition to that the placement of the source/drain electrodes with respect to the

semiconductor layer is also important. Structures such as the one on the top left of the

figure is a bottom electrode and the one on the top right is top electrode configuration. In

addition to these configurations top electrodes top gate structure can also be used

although it’s rarely reported in the literature. [20]

30

Figure 7. Structures of Organic transistors[21].

The principle of operation of the organic transistors is similar to the conventional

transistors although some aspects of the operation of the organic transistors such as the

contact effect and charge transport are not thoroughly investigated or understood.

31

2.8 Charge injection/transport in organic transistors

One of the concerns about any organic transistor is regarding its performance and

especially its carrier mobility. To analyze the carrier mobility we should think about the

effect of contacts as well as the amount of current flow in the semiconductor itself. The

concept of charge injection/transport is similar to what is happening in a water hose. In

this case the effect of valve is similar to the injection phenomenon happening at the

metal-semiconductor junction and the hose is the semiconductor channel. Hence the

name of current injection refers to how charge injection happens at the interface of the

metal-semiconductor and the name of charge transport refers on how the charges pass

through the semiconductor. [22]

In the case of inorganic semiconductors such as silicon, there is a strong coupling

between the atoms of the lattice. This leads to delocalization of the electrons. Free

carriers can be generated thermally or via excitation. However this is not the case in the

organic semiconductors due to the structural differences and defects. Although the charge

transport mechanism in the organic semiconductors is not well understood, it has been

narrowed down to a few possible transport mechanisms. One of these mechanisms is so

called phonon assisted hopping. In this mechanism the phonon helps the electrons to hop

the barrier and therefore current flows. Since the energy band of the organic layers can be

drastically change because of the molecular disorder, the concept of energy bands may

not be applicable anymore. That is the reason that to analyze the charge flow in an

organic layer, we need to rely on molecular interactions.[23] If the charge transport is due

to hopping method it is expected that the carrier mobility to decrease as the temperature

decrease.

Another charge transport mechanism is so called ‘band transport’. Band transport

mechanism considers a defect free crystal. In this case periodic potential waves cause the

loosely bounded electrons to move, similar to inorganic materials. In the case of band

transport it is expected that the carrier mobility to increase as the temperature decrease.

This effect is due to the fact that the scattering of electrons becomes less significant as the

temperature reduces.[24]

32

2.8.1 Charge injection in pentacene transistors

The charge injection mechanism in organic semiconductors can be divided into so

called the bulk-limited and space charge limited injections. The bulk-limited injection

happens when the contact resistance of the metal-semiconductor layer is negligible to

channel resistance (semiconductor layer). Hence the name bulk-limited implies the fact

that the current is limited by charge transport mechanism rather than the contact. This

injection mechanism happens when the contact between the electrode and semiconductor

is ohmic and the applied voltage across the semiconductor is low. In the case of

pentacene to minimize the effect of contact, gold materials as source/drain electrodes are

widely used. This is due to minimum energy difference between HOMO level of

pentacene (~5.0 ev) and the work function of Au (~5.1 ev). [25]

However at higher voltage drop across the organic semiconductor, this injection

mechanism is not true anymore. The electric field is high; the current density will be high

as well. However the electrons will get trapped as they conduct along the channel. This

effect is due to localized states such as traps and defects in organic semiconductors. Since

the organic materials have poor carrier mobility this effect will be more apparent. In this

case there is a significant charge concentration in the material and the name ‘space charge

-limited’ is given for this injection mechanism. As will be discussed in section 2.8.3, the

space charge limited current does not happen in organic field effect transistors and only

exist in stacked layer (diode like) structures.

The current-voltage behavior of a bulk-limited (ohmic) injection is linear. However in the

case of space charge limited, the current in the semiconductor increases non-linearly as

the voltage across the semiconductor increases.[26]

Optimization of charge injection in pentacene transistors relies in understanding

1) the effect of the semiconductor-metal energy barrier and 2) the morphology of the film

at the metal-semiconductor junction (including film discontinuities near the metal

interface).

33

As already mentioned above, one of the widely used materials as source/drain electrodes

is gold. If the gold electrode interfaces the pentacene layer without any intermediate

layer, that can cause formation of voids. The following image shows an example of film

morphology of a pentacene transistor and the voids at the interface. The structure of this

specific transistor is bottom-gate top-electrode. From the image it can be seen that at the

interface of Au-pentacene there are pentacene film discontinuities.

Figure 8. Au-pentacene interface[27].

As suggested by Asadi et al. treating the electrodes with self-assembled monolayer of

PFOT can increase the effective carrier mobility from 10-5

cm2/Vs for untreated

electrodes to 0.0015 cm2/Vs for treated electrodes. The following image shows the film

morphology of Au+SAM – pentacene interface.

Figure 9. PFOT treated electrodes - pentacene interface[27].

34

In this case the Au-pentacene interface has fewer voids. As suggested by [27] the

dominant role in the carrier mobility improvement is better coating at the interface rather

than the aligned energy levels at this interface. This means that the charge

injection/collection has been improved due to lack of voids.

Other thiol based self-assembled monolayers are also proven to reduce the voids at the

interface of Au electrodes. These thiol-based compounds such as PFBT and ODT

increase the uniformity of the pentacene layer along the electrodes as well. In the case of

ODT the carrier mobility is increased by 25% compared to the untreated electrodes. [28]

On the other hand, it is reported that the Au-penatcene interface can have an energy

difference even if there is a uniform coating without any voids at the interface. This

energy difference is shown below. Coating of an intermediate layer can change this

energy difference. As suggested by [29], coating a layer of 2-mercapto-5-

nitrobenzimidazole can reduce this energy barrier two times. This treatment can increase

the carrier mobility of 0.006 cm2/Vs for the untreated junction to 0.14 cm

2/Vs for the

treated junction.

Figure 10. Pentacene-Au junction - treated versus untreated junction[29].

Another case is that, rather than treating the Au electrodes for better coating at the

interface or reducing the energy barrier, we can also use other electrodes to improve the

contact resistance and hence better charge injection. One of these materials is Graphene.

35

The energy barrier between the Au electrodes and pentacene layer is in the range of a few

hundreds meVs (treated or untreated). Choosing Graphene electrode can reduce this

energy barrier ten times and increase the carrier mobility extracted from transistors at

least two times. In this case the carrier mobility is 0.16-0.28 cm2/V.s for the untreated

Au-pentacene junction and 0.4-1.01 cm2/V.s for the Graphene-pentacene interface. In this

case the contact resistance extracted from the I-V behavior of transistors was reduced

from 0.86 MΩ to 0.56 MΩ. [30] The methods for extraction of contact resistance from

the experimental data are discussed in section 2.9.1 in details.

Figure 11. Energy level diagram - Au-pentacene and Graphene-pentacene junction[30].

2.8.2 Charge transport in pentacene transistors

As already mentioned above one of the charge transport methods in the organic

semiconductor is band transport. As it’s been reported by [31] this charge transport

method results in carrier mobility of 40 cm2/V.s for pentacene transistors. Such high

carrier mobility is only possible in a single crystal layer of pentacene layer and it is due to

band-to-band transport. The single crystal layer results in ultra-pure and trap-free layer.

This is the reason of such high carrier mobility.

In the case of TIPS pentacene transistors substantial work has been done to understand

the charge injection and transport methods. One of the parameters that can affect the

carrier mobility is temperature. In silicon-based transistors as temperature increases the

carrier mobility decreases due to increase of electron scattering. However in the case of

36

TIPS pentacene transistors as temperature increases up to a transition point temperature

Ta=60 °C the carrier mobility increases. This is believed to be as a result of thermal

relaxation of the TIPS pentacene and causes four times increase in carrier mobility

compared to the one at room temperature. As the temperature passes the transition points

the carrier mobility decreases substantially. The reason for reduction of carrier mobility is

believed to be due to formation of cracks in the semiconducting layer. In this case the

effective carrier mobility is ten times less than that of at room temperature. [32]

37

2.8.3 Space charge limited (SCL) current in organic diode versus transistor configuration

Space charge limited current is a phenomena in which electrode will not inject

any more charges due to accumulation of charges in the channel (or near electrode

interfaces). This effect has been observed in the layered structures such as OLEDs, solar

cells and photo-detectors. [33-35]

Carrier mobility in organic materials is low in the order of 10-5

-10-3

cm2/Vs. If a strong

charge injection happens (i.e. in modern OLEDs, standard electroluminescent operation

requires current density injection of more than 3 mA/cm2), low carrier mobility of the

organic semiconductor results in the accumulation of charges within the semiconductor

layers. [36] This phenomenon causes non-uniform charge distribution in the organic layer

of stacked layered devices. Hence the efficiency of these device types will be limited.

[37] In the case of the space charge limited current in a single layer and trap free

semiconductor, the current-voltage behavior follows Mott-Curney relation also known as

Child’s law.

Equation 8

In the above equation μ is the carrier mobility of the organic semiconductor and L is the

length (thickness) of the organic layer.[38]

Although the SCL phenomena occurs in organic layered devices, in the case of organic

transistors this phenomena does not happen. Let’s consider an NMOS transistor in which

the channel is n-type. In this case, when the inversion layer forms in the channel,

electrons flow from drain to source electrodes. The inversion layer forms when

sufficiently high gate voltage (positive) is applied (Vgs>Vth). The number of charges that

forms in the inversion layer is proportional to the applied gate voltage.[39]

When a transistor operates in the triode region, as the voltage across drain-source

electrodes is applied, charges in the inversion layer flow from drain to source electrode.

As the drain-source voltage increases the voltage drop at oxide semiconductor interface

near the drain electrode reduces; hence the induced inversion charge density reduces near

38

the drain-channel interface.[40] This means that in the operation of the field effect

transistors the charge density in the channel is a function both Vgs and Vds. If the applied

drain-source voltage increases the charge density near drain electrode reduces. This

prevents the transistor (including organic field effect transistors) to have charge transport

limitation due to space charge limited current. [41]

39

2.9 Extraction of voltage drops at the contacts

Methods of extraction of the voltage drops at the contact can be divided into two

main categories. The first category is using the I-V characteristic of the transistors with

various channel lengths and the second method directly measures the channel potential to

accurately extract the voltage drops at the contacts. The rest of this section explains these

two methods in detail and talk about the advantages and drawbacks of each.

The first method mentioned above is so called Transfer Line Method (TLM). This

method is more popular in literature due to ease of extraction. In this method organic

transistors with various channel lengths should be DC characterized. This method uses

the linear region of operation in transistor and later in this section I will explain why we

should use the linear region. As it is demonstrated in detail in section 2.7, the drain-

source current is linearly proportional to drain-source voltage at small drain-source

voltages.

Let’s call the ratio of

the Rtotal of the transistor in linear region. Rtotal means that this

resistance is taking into account the channel resistance (Rch) and contact resistance (Rc).

If we plot the Rtotal for various gate-source voltages as well as various channel lengths we

get a plot similar to the following plot.

Figure 12. Total resistance as a function of channel length[42].

The next step is to extrapolate all the lines and find the intercept point. The meaning of

the intercept point is that at that point the Rtotal is no longer a function of gate-source

40

voltage. This means that Rch is no longer a part of Rtoal and Rtotal=Rc. [43] As this method

uses the dependency of the drain-source current to drain-source voltage, only linear

region of operation is appropriate for this extraction method. Although this method is

simple and does not require special device configuration it suffers from the following

drawbacks:

This measurement requires devices with various channel lengths. Meanwhile all

the other parameters such as carrier mobility should be unchanged from device to

device.

This method cannot distinguish the contact barrier/resistance at source and drain

electrode. [42]

To overcome the problems motioned above we can use another method so called Kelvin

probing method. Kelvin method is a probing technique that measures the potential along

the channel. In the literature, the AFM tip has been used to measure the voltages along

the channel. [43] However this technique is complex and requires costly equipment.

Another approach in using Kelvin probing technique is to use the intermediate pads to

measure the voltages along the channel. This approach involves simple fabrication and

measurement procedures. In this case inner electrodes with various channel lengths are

microfabricated along the channel (L1,L2,.. <L). During this measurement the voltage

applied at source and drain electrodes are VS (typically VS =0) and VD respectively. Upon

the application of Vs and VD, the voltage drop across the inner electrodes is sensed. To be

able to extrapolate a line we need to have at least a pair of intermediate electrodes. As

shown in the following figure at Length=L on the x-axis the voltage drop is less than VD

by ΔVD and at Length=0 the voltage is higher than zero by ΔVs. In this dissertation the

novel method of extraction of contact effect using intermediate Kelvin pads are

introduced and investigated.

41

Figure 13. Contact resistance extraction using four-point probe method[43].

2.10 Organic transistors – performance development

As already mentioned above one of the important parameter of any transistor that

shows its performance is its carrier mobility. The following figure shows specifically the

comparison of the carrier mobility of the organic materials (i.e. pentacene) to that of

silicon/poly-silicon. The figure shows that the carrier mobility of the pentacene transistor

is lower than that of si/poly-si and it is comparable to that of amorphous silicon.

Figure 14. Comparison of carrier mobility of organic materials[44].

This section reports some of the works published by researchers to improve the extracted

effective carrier mobility of the pentacene transistor and understand the factors affecting

this parameter. The effective carrier mobility refers to an extracted number from the I-V

behavior of transistors (in literature this often simply called carrier mobility).

The following table shows summary of some of the published work and the

corresponding electrical performance. This is the evidence of the diversity of work that

42

has been done to improve the effective carrier mobility. This table is sorted in ascending

order based on the reported effective carrier mobility and the rest of this section explains

these results and the differences between them.

Author Journal/Year Organic

compound

used

FET Structure Type of

insulator/thick

ness

Treatme

nt of

insulator

Type of

electrodes/thickness

Treatment

of

electrodes

Semiconductor

coating

method/thickness

Carrier

mobility

(cm2/Vs)

C.

Kim/D.

Jeon

Conference on

molecular

electronics and

devices/

Pentacene Bottom gate/

Bottom

electrodes

SiO2/300nm - Source is Au/50nm

and drain is Cr/10nm

- Thermal

evaporation

1.4x10-4

C.

Kim/D.

Jeon

Conference on

molecular

electronics and

devices/

Pentacene Top gate/

bottom

electrodes

SiO2/300nm - Source is Au/50nm

and drain is Cr/10nm

Gate is Al

- Thermal

evaporation

1.8x10-4

S. Shin Semiconductor

science and

technology

TIPS

pentacene

Bottom gate/top

electrodes

PVP - Au/200nm - Drop casting 0.00208

K.

Asadi

Advanced

materials/2009

Single

layer

pentacene

Bottom

gate/Bottom

electrodes

SiO2/250nm - Au PFOT Homoepitaxial-

like growth

0.02-

0.05

Y. J

Kim

Proc. Of

ASID/2006

TIPS

pentacene

Bottom

gate/bottom

electrodes

PVP HMDS Source and drain

electrodes are Cr/Au

and gate electrode is

Al-Si

- Ink-jet method 0.04

S.K

Park

Applied

physics

letters/2007

TIPS

pentacene

Bottom

gate/bottom

electrodes

SiO2 HMDS Au PFBT Spin coating

Dip coating

Drop casting

0.05-0.2

0.1-0.6

1.2

C.H

Kim

HAL archives-

ouvertes


bottom

electrodes

SU-8 - Source and drain

electrodes are Au and

gate electrode is Cr

- Evaporation 0.055

S.P

Tiwari

IEEE/2007 Pentacene Bottom gate/

top electrodes

PMMA/500nm - Au as source and

drain electrodes, Al

as bottom gate

- Thermal

evaporation/

45nm

0.07

J. Kim J. of

physics/2009

TIPS

pentacene

Bottom

gate/bottom

electrodes

PVP - Au - Spin coat 0.13

S.H.

Kim

Applied

physics letters

TIPS

pentacene

Bottom gate/top

electrodes

SiO2 HMDS Au/120nm - Drop casting 0.185

Y.

Kimura

Langmuir

letter/2009

TIPS

pentacene

Bottom

gate/bottom

electrodes

SiO2 - Ti/Pt/Au - Drop cast 0.3

H.

Klauk

J. of applied

materials

Pentacene Bottom gate/top

electrodes

SiO2 - Source and drain

electrodes are Au. Si

is gate electrode

- Thermal

evaporation

0.4

S.Y.

Yang

Applied

physics

letters/2006


top electrodes

PVP/10nm - Au - Thermal

evaporation/ 45

nm

0.5

Y.S

Yang

Macromolecula

r research/2002


top electrodes

SiO2 HMDS Source and drain

electrodes are Au/Cr

Gate electrode is Au

- Thermal

evaporation/(50-

400nm)

0.8

X.H

Zhang

Organic

Electronics/200

7


top electrodes

Al2O3/200nm OTS Ti/Au / 10nm/100nm - Evaporation/

60nm

1.5

43

S. Guha NSTI-

nanotech/2014


top electrodes

PVP(on Al

coated glass)

- Au - Solution process 2

H.

Klauk

J. of applied

materials


electrodes

SiO2 OTS Source and drain

electrodes are Au. Si

is gate electrode

- Thermal

evaporation

1

Y. Kato Applied

physics letters/

2004


electrodes

polymide - Au - Thermal

evaporation

1

Y. Jang Applied

physics

letters/2009


top electrodes

PVP+BST

NPs

- Au source and drain

electrodes, Si as gate

electrode

- Organic

molecular beam

deposition/50nm

1.2

F.

Jianfeng

J. of

semiconductors


electrodes

PMMA+ WO3 - Al - Thermal

evaporation

1.9

H.

Klauk

J. of applied

materials


electrodes

Cross-linked

Polyvinylphen

ol and its

copolymer/260

nm

Source and drain

electrodes are Au.

Si is gate electrode

- Thermal

evaporation

3

C.Y

Wei

IEEE electron

device

letters/2011

TIPS

pentacene

Bottom gate/top

electrodes

Ba1.2Ti0.8O3 - Source and drain

electrodes are Au and

gate electrode is Al

- Spin coat 8.85

O.D.Jur

chescu

Advanced

materials

Pentacene Single crystal

growth

Pentacenequin

-one

Single crystal

growth

15-40

Table 1. Literature review of pentacene transistors.

Fabrication methods including the choice of materials and deposition methods

have significant effect on the effective carrier mobility. So far in the case of pentacene

transistors, the reported effective carrier mobilities are from 10-5

– 40 cm2/Vs.

2.10.1 Effect of coating methods of organic semiconductor on the electrical performance

Majority reported works in literature to improve the effective carrier mobility are

done by using the appropriate electrodes, insulator and using an optimal semiconductor

coating method.

The high effective carrier mobility devices reported often needs time consuming method

of thermal evaporation of the organic materials. [45]

Other deposition methods that make the fabrication less costly and complex are the dip

coating, blade coating and spin casting. In the dip coating method, the substrate is

immersed in an organic semiconductor solution for a given time and then withdrawn at a

well-defined speed. During this process a thin layer of the organic film is formed on the

substrate. The thickness of this layer depends on the speed of immersion/pulling and the

44

semiconductor solution properties (viscosity, liquid-vapor surface tension and density of

the solution). Although this method gives macroscopically uniform film, the effective

carrier mobility of up to 0.1 cm2/Vs has been reported.

In the case of blade coating method, a moving surface to smooth the coating material is

used. Although the blade coating mechanism is not as well controlled as the spin and dip

coating methods, in many cases the effective carrier moblity is improved compared to

other methods. The disadvantage of the blade coating method is the non-uniform film

coating due to not well-controlled blade’s moving direction and pressure. In the case of

the organic thin film transistors the reported carrier mobilities are 0.001-1 cm2/Vs.

The most common method for depositing uniform films over a large area such as a wafer

is to use spin-casting method. This coating method gives the highest uniformity

compared with the blade coating and dip coating method.

2.10.2 Effect of gate dielectric material on effective carrier mobility

In addition to the deposition methods, the gate dielectric of devices is proven to

affect the effective carrier mobility. As reported by Zhang et al. transistors fabricated

using an Al2O3 dielectric shows effective carrier mobility of 1.5 cm2/Vs. In this particular

case the organic material is deposited by thermal evaporation. Also in this case the gate

dielectric deposition uses atomic layer deposition method that adds to the fabrication cost

and complexity. [46]

One of the gate dielectrics reported in literature numerous times is the PVP polymer. As

reported by Yang et al. reducing the thickness of this dielectric down to 10 nm still shows

good insulating properties. This ultra-thin polymer has shown high breakdown fields

(>2.5 MV/cm) with high capacitance of 250 nF/cm2.

The reported effective carrier mobility by using this ultra-thin layer of PVP is ~ 0.5

cm2/Vs. As reported by this group the cross-linkable PVP solution is composed of PVP

polymer, poly (melamine-co-formaldehyde) methylated as a cross linking agent and

propylene glycol monomethyl ether acetate as a solvent. This solution was spun coated at

45

7000 rpm and baked at 80 °C for 10 minutes. This coating of the insulator is desirable

since it is a low cost and simple. [47]

Being able to use polymer-based insulators with spin coating method makes the flexible

transistors fabrication possible. As reported by Tiwari et al. pentacene transistors

fabricated using polymethyl methacrylate (PMMA) as a gate dielectric on flexible

polymeric substrates like the Indium tin oxide coated polyethylene terephthalate (ITO

coated PET) show effective carrier mobility of 0.07 cm2/Vs.[48]

A few groups have investigated polymer-based gate insulators and different deposition

methods and thicknesses to improve the effective carrier mobility. As reported by Jang et

al., organic field effect transistors with nano-particle polymer composite/polymer bilayer

insulators using barium strontium titanate (BST) shows a carrier mobility of 1.2 cm2/Vs.

As reported by this group, this gate insulator exhibits higher field effect mobility and

field induced current than those in pure PVP insulators due to increase in the capacitance

of the dielectric layer. Since the NPs can increase the surface roughness, incorporating a

thin passivation layer significantly reduces the surface roughness hence the effective

carrier mobility of 1.2 cm2/Vs is achieved.[49]

2.10.3 Effect of electrodes and surface treatments

In the case of organic transistors, it is reported that the surface modification of the

gate dielectric as well as the contact area at the source and drain electrodes can affect the

effective carrier mobility. Rest of this section explains some of the proposed methods for

fabricating high carrier mobility transistors by adding an intermediate at the interface of

the electrode and the organic layer. All these reports are based on having the silicon

dioxide as the gate insulator.

As mentioned earlier, the simplest OFET structure consists of a substrate, which acts as

the gate electrode, as well as a pair of electrodes so called the source and drain electrodes.

Since silicon substrates are widely used for various device fabrication purposes, this type

of substrates is also common in OFETs. For this reason thermally grown silicon dioxide

46

has been widely used in literature. Let’s consider a simple fabrication case in which a

bottom contact transistor with silicon dioxide insulator has been used.

Let’s consider a transistor with Au contacts which is the most widely used material for

the source/drain electrodes. The reason of using Au contacts with pentacene

semiconductor is explained later. Also let’s consider a layer of silicon dioxide as the gate

insulator for this device. The next step prior deposition of the organic solution is to treat

the surfaces that will be in contact to the semiconducting layer. Typically for the

transistors fabricated with pentacene, a monolayer of pentafluorobenzenethiol (PFBT) as

an intermediate layer to Au contacts can be used. Also for treating the silicon dioxide a

monolayer of hexamethyldisilazane (HMDS) is coated. The Au treatment is done by

immersing the wafers in 10 mM PFBT-ethanol for two minutes. Following the Au

electrode treatment, HMDS was spun coated at 4000 rpm. After the surface treatments,

the organic solution should be deposited. It has been reported by [50] that these

treatments can results in an effective carrier mobility of 1 cm2/Vs.

In addition to HMDS, octadecyltrichlorosilane (OTS) treated silicon dioxide has been

investigated by [51]. According to their experiment, the effective carrier mobility of the

fabricated device with an untreated silicon dioxide is 0.4 cm2/Vs while the treated silicon

dioxide layer with OTS shows the effective carrier mobility of 1 cm2/Vs.

As mentioned earlier in chapter 2, the reason of treating the electrodes is to reduce the

voids at the interfaces. In general using a layer of thiol-based organic improves the

charge injection into the active layer. The thiol based layer bonds well to the gold

electrodes and behaves as an electron acceptor layer. The thiol surface has sulfur atoms

which bonds well to the noble metals. As a result it increases the charge density at the

proximity of the electrodes and the active layer hence reduces the width of the barrier

which improves the charge injection. Other electrode treatments reported are cyano,

aromatic nitro compounds.

The semiconductor-metal junction may form an energy barrier depending on the material

used for electrodes. Using different metals can modulate this barrier, hence affecting the

charge injection.

47

In addition to the choice of materials for electrodes, modifying those electrodes can also

affect the electrical performance. Using self-assembled monolayer (SAM) of modifying

agent affect the film morphology at contact interface. In this case the reason of higher

effective carrier mobility is due to improvement of film morphology rather than

alignment of energy levels at contacts. As reported by Asadi et al. after SAM treatment,

due to the absence of small crystallites, pentacene grain boundaries are eliminated and

charge trapping hardly occurs.

Besides using metals from the periodic table, other materials such as graphene, nanowires

and material composites as electrodes have been investigated.

As reported by [30] using the multi-layer of Graphene films as the source and drain

electrodes can improve the charge injection. Transistors fabricated with these electrodes

along with the surface treatments of the silicon dioxide layer show an effective carrier

mobility of 1.2 cm2/Vs. In this case OTS film is the treatment done on silicon dioxide.

The OTS forms a SAM on the insulator and is known to reduce the trapping interface

states and minimize the effect of dielectric polar functional groups.

As already mentioned, organic field effect transistors suffer from low effective

carrier mobility. One of the significant performance limitation factors is the issue of a

barrier existing at the metal-semiconductor interface. Two approaches to reduce the effect

of contact are the appropriate choice of metals (for electrodes) as a well as the treatment

of electrodes. This type of engineering of performance is so called contact engineering.

As an example, Chuan Liu et al. reported that for the pentacene transistors, using Au

electrodes reduces the contact resistance from a few mega-ohms down to ~ 1MΩ. Further

thiol treatment of these Au electrodes reduces the contact resistance down to ~300 KΩ.

[43]

The injection barriers as the main source of the performance degradation can be

characterized by the extraction of the barrier at contacts. The simplest method for contact

barrier characterization is by analytical extraction of the voltage drops at the contacts

using the characteristic of the transistor (Ids versus Vds). However the extracted voltage

drops rely on the assumption of equality of the barrier at the drain and source electrodes.

48

The more precise approach to measure the contact barrier is by incorporating a pair(s) of

intermediate electrodes along the channel of the transistor. In this dissertation 4-point

probes (also called Kelvin method) is used to characterize the barriers existing at contacts

for various metals in the pentacene transistors.

49

3. Device fabrication

Process run sheets for fabricating organic field effect transistors using pentacene

and its derivatives are attached as an appendix. This section explains the processes in

detail.

The fabrication of organic transistors starts with a 3-inch n-type silicon wafer, single side

polished, with a resistivity of 1-10 Ω-cm. Since a bottom gate structure is used in this

work, the unpolished side of the wafer is used as the gate electrode. In practice, this

means that the gate voltage is applied to the unpolished side using the wafer chuck during

testing. The reason the bottom gate structure is used is due to its ease of fabrication.

To prevent the short circuit connection of the devices and provide the gate insulator, we

need an insulator layer. The chosen insulator in this case is silicon dioxide that is grown

thermally on the silicon wafer.

A low defect density silicon dioxide layer is crucial for a high yield fabrication of

transistors. Having an oxide with pin-holes reduces the yield of the devices. Gate current

leakage could suppress the actual electrical behavior of the transistors. Therefore before

thermally growing a silicon dioxide layer we need to clean the wafer from residues and

contaminants. In this case a conventional pre-diffusion clean is used. As the first step a

Piranha clean which is a 2:1 ratio of the sulfuric acid and hydrogen peroxide in a glass

beaker is used. Upon mixing the hydrogen peroxide, the mixture will heat up to about

115 ºC. The wafers are dipped in this solution for 10 minutes. This step cleans the

organic contaminations from the wafer.

As the next step the wafers are dipped in 1:40 HF:DI water. This step removes the native

oxide formed on the wafer. The last step of the cleaning is to remove the metallic

residues. This step is done using 1:1:6 mixtures of DI water, hydrogen peroxide and

HCL. This mixture is heated up using hot plate to about 90 ºC. The cleaning time is 10

minutes and following that the wafers are rinsed and dried using nitrogen.

50

Immediately after the cleaning step is done, we need to load the wafers in the furnace and

oxidize them. The oxidation is done in a horizontal furnace and a dry oxidation is chosen.

Since dry oxidation method grows slightly better quality of silicon dioxide, dry oxidation

method is chosen for this work. The desired thickness of the oxide is 100 nm and

oxidation time is 42 minutes at 1100 ºC. The following table shows each step of

oxidation in more details.

Step Temperature - Time Gases

Boat push 1000 ºC - 5 minutes 1.5 slpm1 O2, 18 slpm N2

Temp. ramp up 1100 ºC - 10 minutes Dry O2, 0.9 slpm O2

Oxidation 1100 ºC – 42 minutes Dry O2, 9 slpm O2

Ramp down 1000 ºC – 10 minutes Dry O2, 0.9 slpm O2

Boat pull 1000 ºC – 5 minutes N2, 6 slpm

Table 2. Furnace steps for oxidizing 100 nm of SiO2.

As it will be discussed later in more detail, the back of the wafer is used as the gate

electrode. During the oxidation process silicon dioxide is formed on both sides of the

wafer. To have an electrical contact to the back of the wafer (the unpolished side) we

need to remove the oxide layer. Prior to removing the oxide on the unpolished side of the

wafer we need to protect the oxide formed on the polished side. Hence we coat the

polished side with a layer of photoresisit. In this case Shipley S1813 resist is coated at

4000 rpm and baked at 115 °C for 1 minute on the polished side. Following that the

wafers are dipped in a plastic beaker filled with (1:10 HF: DI water). The etch rate of

this mixture is 100 nm/min, therefore an etch time of 70 seconds is chosen to make sure

that the oxide on the unpolished side is removed completely. This etching step is done

before deposition of the metal electrodes since coating a layer of photo-resist on the metal

electrodes (especially Au electrodes) could cause a non-removable PR contamination.

The step after etching the non-polished side of the wafer is lithography. For this work

optical lithography with lift-off patterning of the metal electrodes is used. Since the

1 Standard Liters Per Minute

51

minimum feature size of the designed transistors is 10 µm, optical lithography can easily

achieve that.

For this work the lithography method using double layer photoresist is chosen. The

reason for using such a structure is that since the bottom photoresist has a slightly higher

development rate than the top photoresist, it forms an undercut in the bottom photoresist

layer. This undercut helps for a better lift-off since it prevents the continuous metal layer

across the channel region of the transistors. It is noteworthy that the bottom photoresist is

not a UV light sensitive layer.

The lithography step starts with spinning a layer of Microchem LOR2A photoresist. A

spin speed of 3000 rpm is chosen for 45 seconds and following that the wafer is baked at

175 ºC for 5 minutes. This results in a uniform layer of LOR2A with the thickness of 200

nm.

After that a layer of S1813 photoresist is coated at 4000 rpm and baked at 115 ºC for 1

minute. This would result in a uniform layer of S1813 that is ~1.3 μm thick.

Now that the two layers of photoresists are coated, the mask aligner is used to make the

pattern of the mask on the wafer. As S1813 is a positive photoresists the portion of the

mask which is clear (passes light) will make the photoresist soluble in the developer. The

required exposure time in this case has been found to be 7 seconds with a light intensity

of 12 mW/cm2.

The next step after exposure is development of the features. The developer Micoposit

MF319 is used and wafers are gently agitated in the developer for 50 seconds.

Immediately after the development, a 5 minutes rinse in water followed by dry using

nitrogen is done.

The step after patterning is to deposit the electrodes. In this case 1 nm of Chromium is

used to promote adhesion in metals where an intermediate layer is needed between SiO2

and metal. If the metal does not require any adhesion layer to attach to silicon dioxide,

100nm thick metal will be deposited on patterned wafers using sputtering method.

52

Section 3.1 explains the sputtering recipes used to deposit various metals. Following the

deposition of electrodes, to lift off the metals from the regions where photoresist is not

developed, wafers are soaked in acetone bath for 30 minutes. Figure 15 shows the cross

section of fabrication steps that are mentioned above in detail.

Figure 15. Cross-section of fabrication steps using double layer lift off.

The reasons of using double layer photoresists rather than the single layer for the

fabrication of organic transistors are, 1) it makes the lift off process easier and faster and

2) it significantly reduces the contact interface of the adhesion layer to the organic layer.

The photoresist layer after the exposure and development ideally would have the vertical

side walls. However in reality the photoresist has a certain slope after the exposure and

development as shown in figure 16. In this case if an organic layer is coated, this layer

would be mostly in contact to the adhesion layer rather than the metal. Figure 16 is the

graphical demonstration of this effect. However, using a proper thin layer of photoresist

underneath the top photoresist forms an undercut after development. This prevents the

continuity of the metals that are deposited at the side wall of photoresist. Hence, this

53

discontinuity of the deposited metal layers not only makes the lift off process easier but

also reduces the contact interface of the adhesion layer to the organic layer substantially.

Figure 16. Sidewall effect of using single layer PR process

54

3.1 Sputtering recipes

To deposit the metals, wafers with patterned photoresist are loaded in the MRC

sputtering machine. To be able to have a pure and uniform layer of metals, a chamber

with low pressure is necessary. The pressure that the chamber is pumped to prior to the

depositions is ~ 10-6

Torr. To be able to reach such a low pressure a pump down time of

approximately three hours is needed for the sputtering chamber used in this work. As the

chamber reaches this pressure, based on the required metal, the corresponding recipe is

loaded and deposition starts.

Following tables summarize the recipes used for various metals deposition.

Target RF/DC

power Power(W)

Substrate

rotation rate

(rpm)

Time of

rotation

(min:sec)

Gas flow Pressure

(mTorr)

Predep.- Cr DC 165 0 03:00 Argon 13

Cr DC 165 4 00:20 Argon 13

Predep.-Au RF 300 0 00:30 Argon 13

Au RF 500 4 03:00 Argon 13

Cool down - - - 10:00 - -

Table 3. Cr/Au deposition recipes.

Target RF/DC

power Power(W)

Substrate

rotation rate

(rpm)

Time of

rotation

(min:sec)

Gas flow Pressure

(mTorr)


Cr DC 165 4 00:20 Argon 13

Predep.-Ru DC 300 0 00:30 Argon 13

Ru DC 500 4 10:00 Argon 13

Cool down - - - 10:00 - -

Table 4. Cr/Ru deposition recipes.

55

Target RF/DC

power Power(W)

Substrate

rotation rate

(rpm)

Time of

rotation

(min:sec)

Gas flow Pressure

(mTorr)


Cr DC 165 4 00:20 Argon 13

Predep.-Ir RF 300 0 00:30 Argon 13

Ir RF 400 4 05:00 Argon 13

Cool down - - - 10:00 - -

Table 5. Cr/Ir deposition recipes.

Target RF/DC

power Power(W)

Substrate

rotation rate

(rpm)

Time of

rotation

(min:sec)

Gas flow Pressure

(mTorr)

Predep.-Ti DC 300 0 00:30 Argon 13

Ti DC 500 4 10:00 Argon 13

Cool down - - - 10:00 - -

Table 6. Ti deposition recipes.

56

3.2 Oxidation step on Ru and Ir metals

As will be explained later, to change the work function of a metal to the required

value, a further oxidation step may be required to form a conducting oxidized metal. In

this work two conducting oxidized metals, IrO2 and RuO2, are used.

To form an oxide layer of Ir or Ru, the coated wafers with metal are loaded into the

chamber of the Anatech plasma system. Prior to the O2 plasma treatment of wafers, the

chamber is pumped down to 0.1 Torr. O2 flow is preset to 10 SCCM, giving a chamber

pressure of approximately 0.2 Torr, and the RF power is 100 watts. Typically higher RF

powers with O2 plasma are used to etch organic materials such as photoresist. Since this

dissertation focuses on the interface of electrodes-organic semiconductor, formation of a

thin layer of oxide would be enough. Hence the O2 treatment time of 30 minutes is

chosen.

3.3 Coating method of pentacene layer – Evaporation and spin coating

Following the electrode patterning, the organic semiconductor should be

deposited. In this work for non-soluble pentacene derivatives, thermal evaporation and

for soluble pentacene compounds spin coating method of the pentacene solution is used.

To thermally evaporate pentacene, 150 mg powder of pentacene is loaded into the

tungsten boat of the thermal evaporator. Evaporation of 150 mg pentacene results in a ~

45 nm thick layer of pentacene. This evaporation was done in the thermal evaporator at a

pressure of 2-5 x 10-6

Torr. 300 Amperes of current is being applied to the Tungsten boat

for the evaporation of pentacene powder. Deposition rate was observed using the crystal

monitor until the evaporation is done.

The other coating method used in this work is spin coating. The soluble pentacene

derivatives reported in the literature are soluble in the non-polar solvents such as

Toluene. In one of the experiments done in this work the electrical behavior of the first

water soluble pentacene derivative is reported. This pentacene derivative is provided by

Dr. Glen Miller’s research group at the chemistry department of University of New

Hampshire. The solution preparation is done by dissolving 100 mg of pentacene in 10 mL

57

of DI water. After preparation of the solution, the patterned wafer is loaded on the chuck

of the Brewer spinner. Spin speed of 1500 rpm for one minute is used to coat the wafer.

Following that the wafer is annealed at 75 °C for 1 minute to remove the remaining

solvent.

Process details for fabrication of transistors using specific pentacene derivatives are

discussed later in chapters 5 and 6.

3.4 Design criteria for the optical mask

The following image shows a wafer fabricated with the optical mask used in this

work. The schematic of the mask is drawn using Coventorware with the minimum feature

size of 10µm.

Figure 17. Patterned wafer fabricated with optical mask.

The structure that is reported widely in the literature typically uses two parallel electrodes

as the source/drain electrodes with bottom gate configuration such as the one shown

below. This structure is most favorable among other structures due to its ease of

fabrication.

Figure 18. Typical electrodes (source/drain) structure of organic transistors.

58

The structure shown above which is widely used in the fabrication of organic transistors

has two main drawbacks as explained below.

This first issue of using this structure is the fringing electric field. In the above structure

the whole area of the chip (wafer) is coated by a layer of the semiconducting organic

material. Also pairs of electrodes are placed in the parallel plate configuration.

Conventionally the channel length (L) of the fabricated transistors is defined as the gap

between the two plates and the channel width (W) is defined as the interface length of the

channel with electrodes. Upon the application of the voltages at the electrodes, the

electric field forms in the channel of the transistors. In this case due to the fringing of the

electric field, channel length and width are not restricted to the area between source and

drain electrodes. Rather, there is an effective channel length and width that depends on

the applied electric field and other structures surrounding the device under test. The

following 2D simulation shows this effect. Unit size of this simulation is in micro-meter.

Although this structure is simple, it is undesirable since the above phenomenon affects

the transistor performance. In this case the device engineer should take all these factors

into consideration while analyzing the electrical behavior of transistors.

Figure 19. Electric field distribution on a 2D plane.

59

The second issue with using this configuration is the effect of a leakage current due to

imperfect insulator. As already mentioned, a thin layer of semiconducting layer coats the

whole area of the chip/wafer. Any gate leakage current on the chip/wafer (even located

outside of the device under test) can affect the electrical behavior of the transistors. Since

the gate leakage current is a function of VGS, as this voltage increases the effect of the

leakage current on the IDS -VDS behavior of transistors become more apparent. An

example of such a behavior is shown below.

Figure 20. IDS-VDS behavior of transistor with gate leakage current.

To be able to resolve these issues without adding complexities to the fabrication, a new

structure is used in this work. To prevent the effect of the fringing electric field we need

to use enclosed devices such as the one shown below. For this device types the channel

length and width are well defined and the electric field is restricted to the area between

source and drain electrodes.

60

Figure 21. Enclosed devices.

Typically to characterize a field effect transistor, the source electrode is grounded.

Similarly in the measurements done in this dissertation the source electrode is grounded

while drain electrode is used to apply voltage and sense the current. To prevent the

effect of insulator leakage current to be sensed by the drain electrode, the outer electrode

in the enclosed configuration should be used as the source electrode (outer electrode

should be grounded). This will prevent any gate leakage current to be sensed by the drain

electrode.

On the designed mask, in addition to the transistor structures, the 4-electrode structures (5

electrodes including the gate electrode) are also designed. The structure of this device

type is shown below.

Figure 22 – Designed Kelvin structures on the optical mask

61

4. Measurement methods

4.1 Electrical measurement methods

This section explains the electrical measurement methods used to characterize the

devices reported in this dissertation. Each pentacene coated wafer has several transistor

structures. For these devices, standard three terminal characterizations are used to

understand the device behavior as well as the extraction of the electrical performance

parameters (the effective device carrier mobility, threshold voltage, ON/OFF current

ratio). The term three terminal refers to gate, source and drain electrodes.

Besides these structures, there are several multiple electrode devices (Kelvin probes as

shown in figure 22) made for understanding the effect of metal-semiconductor junction

(energy barrier at contact). For these devices gate dependent four-point probe

characterization is done. The four-point probes refer to the source and drain electrodes

with the addition of two intermediate electrodes along the channel (note that the gate

electrode is also used).

4.1.1 Standard transistor (three terminals) measurements

To find the device performance of any given transistor, DC characterization

would be the first step. DC characterization can tell the device engineer about the

transistor type, device carrier mobility, threshold voltage, required operating power and

more. One of the main important figures of merit of any organic transistor is the

effective carrier mobility. It is worth to mention that the term effective carrier mobility

refers to the carrier mobility extracted from the DC behavior of the device and it is not

the carrier mobility of the material itself. The effective carrier mobility is influenced by

the device structure, energy barrier at metal-semiconductor junction, used material for

gate insulator, organic layer thickness and several other factors.

In this dissertation transistors fabricated with novel pentacene derivatives are

characterized and effective carrier mobility and threshold voltage have been extracted. As

already explained in the device fabrication section the fabricated devices are three

62

terminals devices. These terminals are so called gate, drain and source terminals. In

inorganic transistors in addition to these three electrodes there is a substrate (body)

electrode. Since in this work the substrate is used as the gate electrode the term three

terminal characterization suffices.

Since pentacene is a P-type semiconductor, the fabricated transistors are the P-channel

field effect transistors. Field effect transistors referred to devices in which the electric

field controls the channel formation and charge conduction. In case of the enhancement

mode transistors, the gate electrode has negative voltage with respect to source electrode

(in this dissertation source electrode is connected to ground). The negative gate bias is

required to invert the channel meaning the formation of channel at the insulator-

semiconductor interface. In this dissertation for simplicity the gate, source and drain

electrodes referred by G, S and D indices respectively.

There are two plots that explain the DC behavior of a transistor. Each one explains

certain aspect of the transistor’s electrical behavior. These two plots are Ids-Vds (transistor

output characteristic in saturation) and Ids-Vgs (transistor transfer characteristic). These

plots are typically look like the following figure.

Figure 23. DC characteristics of a FET – Left: Output characteristic; Right- Transfer characteristic.

The Ids-Vgs curve shows the minimum required gate-source voltage (so called threshold

voltage) to be able to sense current at drain-source electrodes. The slope of this curve is

also important since the effective carrier mobility can be extracted from it. From the

63

circuit point of view these curves are used to find the desired operating point of the

transistors hence developing the biasing circuit.

The current that passes along the channel is a function of Vgs as well as Vds. The curve

shown on the right hand side of the above figure shows that. Depending on the

application, the transistor can operate in triode or saturation mode. The triode region is

also called the linear region since the slope of the Ids-Vds is constant. Ideally in the

saturation region the Ids is constant and is not a function of Vds anymore. In reality due

channel length modulation this is not true anymore.

The conclusion from above is that to DC characterize a transistor, the gate, source and

drain voltages should be swept and the current passing from drain to source electrodes

should be measured.

Explanation of three terminal measurements:

To be able to measure the DC performance of the transistors, the aim is to sweep

the drain-source voltage at a given gate-source voltage and sense the drain-source

current. For this reason 3 SMUs (source-measurement units) of the 4155A

semiconductor parameter analyzer are used. In this case the gate and drain SMUs are

used for sweeping voltages while the source electrode is sourcing constant voltage (zero

volts). Since the gate and drain measurement are made in the source-measurement mode,

the SMUs can source voltage and sense current. Ideally the amount of current that is

sensed by the gate electrode should be zero. However in reality this current is not zero

due to instrument precision or gate insulator leakage. The drain SMU is used to sense the

current passing along the channel.

4.1.2 Electrical parameter extraction

The current passing through the channel is a function of both the gate-source

potential difference and drain-source potential difference. Hence the IV characteristic of

any transistor can be plotted as drain-source current being a function of the drain-source

voltage or the gate-source voltage. The ‘output characteristic’ refers to a plot in which the

drain-source current is plotted as a function of the drain-source voltage. On the other

64

hand the ‘transfer characteristic is when the drain-source current is plotted as a function

of gate-source voltage. In the latter case, the chosen drain-source voltage can be a low

value (transistor operating in the triode region) or high value (transistor operating in the

saturation region).

(a) (b)

Figure 24. (a) Transfer characteristic (b) Output characteristic[52].

In the linear region (low voltage part of the triode region) the charge distribution along

the channel is uniform but in the saturation region this uniformity is not present anymore.

Therefore the mobility calculation in the linear region is mostly preferred. This is the case

for the conventional transistors.

In the case of our measurements the linear region suffers from the effect of contact. This

effect can be noticed from a slope/curvature of Ids-Vds data at low drain-source voltages.

Following figure taken from one of the measurements done in this work demonstrate this

effect.

65

Figure 25. Effect of contact at low drain-source voltages.

This phenomenon is discussed in more details later. Due to this effect seen in our

measurements the mobility extraction is done using the saturation part of the IDS-VDS

curve. This results in more accurate parameter extraction.

To extract the mobility and threshold voltage from the experimental graph we need to use

the mathematical approximation to match the experimental data with the theoretical

formula. One of the problems of extracting the parameters in organic FETs is the lack of

a complete model. A complete model means that the model should be able to explain the

electrical behavior of the organic transistor thoroughly. Consequently most of the

calculation is based on the standard inorganic long channel FETs. The reason for

choosing the long channel model is that the minimum channel length fabricated in this

work is 10 μm. It should be considered that there are three two assumptions for the long

channel model, one is the gradual channel approximation, the other is gate-independent

carrier mobility and the third assumption is that there is no effect of contact in transistors.

It’s worth here to mention that according to literature, the extracted carrier mobility in

organic FETs depend on the gate voltage.[53]

In this thesis the parameters are extracted based on the long channel FET equations

assuming a gate voltage independent mobility. In this method the Ids versus Vgs is plotted

at high Vds (the drain-source voltage should be high enough for the transistor to operate in

the saturation region). The curvature at low Vds cannot be used to retrieve the carrier

mobility as this region is dominated by the contact conduction. Figure 26 shows a typical

66

√IDS-VG curve. The numbers on the axes of the figure have no significance and they are

for the demonstration of the concept.

To find the threshold voltage we need to extrapolate the highest slope of the curve to zero

drain- source current.[54]

Figure 26. Carrier mobility extraction.

Following that using the equation mentioned below the carrier mobility can be extracted

as:

√( )

√

Equation 9

This equation is derived from the MOSFET equation that is already proved in section 2.7

4.1.3 Four terminals measurement – Kelvin probing

As will be explained in more detail later, pentacene is used in this dissertation for

understanding the effect of metal-semiconductor interface. To be able to quantitatively

analyze the metal-semiconductor interface, four-point devices are located on the

fabricated wafers. The concept of these measurements is from the fact that if the metal-

semiconductor barrier affects the charge conduction, using the inner electrodes the

amount of voltage drop at source/drain interfaces can be extracted. If there is a substantial

voltage drop at outer electrodes, this means that there is a large barrier at the electrode(s).

This voltage drop can be due to: 1) the energy difference between the HOMO level of

pentacene and work function of metal electrodes and/or 2) the morphology of pentacene-

67

metal interface. For this reason choosing appropriate metal electrodes as well as coating

method is crucial for high electrical performance transistors.

Similar to the three terminal characterizations, for this experiment the three SMUs

are used for gate, source and drain electrodes. In addition 2 VMUs (voltage measurement

units) are used to measure the voltages at the inner electrodes. Since the VMUs input

resistance is 10 GΩ (based on the 4155A instrument manual and our measurements),

using the VMUs to read the voltage drop will be accurate enough in this work. The

following figure in the next page shows the written Labview program for this

measurement.

68

Figure 27. 4 point probe Labview program.

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4.1.4 Temperature measurements

Currently the field of organic transistors faces several challenges and there is still

a long trend for commercialization. One of the important factors of any electronic device

is their electrical behavior over temperature. Circuit and device engineers are interested

for a consistent trend of the electrical performance over temperature so that they address

these effects in their design. Typically the electronic devices need to be characterized

over the temperature range of -45 °C to 110 °C. The major problem in the field of

organic electronics is that these semiconductors cannot survive high temperature

environment. Extra caution should be taken even during the device fabrication cycle to

prevent these materials from the high temperature exposure. In this dissertation TTPO

which is a newly synthesized material has been electrically characterized over

temperature cycle. This material is very thermally stable and shows electrical behavior up

to 200 °C. Other organic materials such as TIPS pentacene cannot tolerate temperature

beyond 65 °C.

The setup used for the temperature runs uses a temperature controller in which can heat

up the chuck up to 200 °C. In this measurement while the temperature is stepping

up/down full transistor characterization is done. There is the possibility that during

temperature ramp up, film property changes. This change in film may be irreversible.

4.2 Non-electrical measurement methods

In addition to the electrical characterization, film morphology of the organic layer

could affect the electrical performance. For this reason, any experiment done in this

dissertation is followed by the optical imaging as well as thickness measurement of the

organic layer (thickness measurement is done using Dektak profilometer).

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5. Transistors fabricated using novel pentacene derivatives

Pentacene and its reported derivatives in the literature are either non-soluble

compounds or are soluble in non-polar solvents such as Toluene. For fabricating the

solution based devices where various layers of organic semiconductor coating are

required, coating of one layer could affect another layer. In this case having compounds

that have none (less) solubility in the non-polar solvents is an advantage. For this reason

one of the materials investigated in this dissertation is the first water soluble pentacene.

Dr. Glen Miller’s research group at chemistry department of University of New

Hampshire provided all pentacene derivatives used in this dissertation.

Another drawback of pentacene derivatives is the stability of the material over

temperature. Typically the pentacene derivatives are stable up to 65 °C after which the

molecules decompose. In this transition temperature the material will irreversibly

decompose and will not be electrically conducting. In this dissertation first thermally

stable pentacene derivative is characterized. This compound will be stable up to 200 °C

and as temperature increases from room temperature the device carrier mobility

increases. After 200 °C, thin-layer of TTPO starts to crystallize and will lose its electrical

conduction

The rest of this section explains the electrical behavior of these two compounds.

5.1 Water soluble pentacene

The first pentacene derivative explained in this section is the first pentacene

derivative that is soluble in water. From a device fabrication point of view in some cases

an organic solvent cannot be used. As an example if one needs to coat a layer of TIPS

pentacene on a plastic substrate, using organic solvents such as Toluene that can damage

or change the properties of the substrate. In such a case being able to fabricate a transistor

using water soluble pentacene is preferred. Fabricated devices using water soluble

pentacene are sensitive to moisture. Therefore having a protective layer (such as

parylene) on the organic semiconductor layer is advantageous.

71

The general fabrication flow for all penatcene transistors is explained in chapter 3. For

this specific material, Cr/Au (1nm/150nm) electrodes are used for the evaluation of the

electrical performance of the transistors. To deposit the pentacene thin film, a solution of

WSP in water (Figure 28(a)) or EtOH (Figure 28 (b, c)) (12 mg/mL) was spun coated at

1000 rpm for one minute. To evaporate the residual solvent, the resulting film was baked

at 60 °C for one minute on a hot plate in air.

From the electrical perspective, these devices do not show conventional transistor

behavior. However, the results show the current conduction along the bulk upon the

application of the drain-source voltage (Figure 28(d)). The existence of the electrical

conduction opens the possibility for the fabrication of various organic devices.

There is a hypothesis that not observing transistor behavior can be due to effect of

contact. For this reason later in this dissertation the importance of the contact effect is

addressed and analyzed.

Figure 28. (a) thin film of WSP on Au electrodes and Silicon dioxide gate insulator, (a) from water solution, (b,c)

EtOH, (d) Electrical response of thin film WSP transistors.

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5.2 TTPO – thermally stable pentacene

Another novel material that was first evaluated in our group was a thermally

stable derivative of pentacene so called 5,6,7-trithiapentacene-13-one pentacene (TTPO) .

Fabricated transistors made from this compound can survive up to 200 °C.

Similar to water soluble pentacene transistors, these devices are made using Cr/Au

(1nm/150nm) electrodes. After the cleaning step, the wafer was loaded in the thermal

evaporator. The details of the cleaning steps prior to organic coating are explained in

chapter 3 in detail.

40 mg of solid TTPO compound was loaded in the tungsten boat of the thermal

evaporator. Before the coating process started, the thermal evaporator was pumped down

to the pressure of 1 torr. To start the evaporation, 300 A current is passing

through the tungsten boat. The evaporation continued until the loaded TTPO evaporated

and the thickness monitor showed no evaporation rate. Dektak measurements indicate

that the final thickness of the deposited pentacene layer is 50 nm. The thickness of the

film is uniform and the maximum deviation of only +/- 2 nm was observed. Figure 29

shows the optical image of a device coated with TTPO.

Figure 29. Optical image of a coated device with TTPO. The yellow areas are Cr/Au electrodes.

Figure 29 was taken after the thermal evaporation and prior testing. The evaporated film

is uniform without any obvious crystals.

Electrical characterization fo TTPO:

The aim of this characterization is to understand the electrical behavior of TTPO at room

temperature and also as a function of the temperature. During this test, the temperature of

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the chuck holding the wafer was swept from room temperature to 200 °C. The chuck

itself is also acting as the gate electrode. Therefore to make a good contact between the

chuck and wafer, the chuck pump was running during the measurement. Figure 30 shows

the transistor behaviors of a device fabricated with TTPO as a function of temperature.

All curves correspond to Vgs= -50 V.

Figure 30. Transistor behavior at Vgs= -50 V.

As it was expected this compound does not conduct well at room temperature unless a

high gate voltage is applied. As the annealing temperature increases so does the

conductivity of the device (extracted effective carrier mobility). Figure 31 shows the

extracted effective carrier mobility as a function of temperature.

Figure 31. Carrier mobility versus temperature.

74

As it is shown in figure 31 the effective carrier mobility increases by an order of

magnitude to 9×10-9

cm2/Vs at 200 °C.

The explanations of the low effective carrier mobility of the TTPO transistors are 1) the

material itself has low carrier mobility and 2) the contact affect the I-V behavior of the

transistors hence the extracted effective carrier mobility. The latter case might be due to

an energy barrier at metal-TTPO junction and/or lack of existence of traps at the

interface.

75

6. Effect of metal-organic semiconductor interface – Experimental and modeling

In organic transistors, threshold voltage and carrier mobility of transistors can be

affected by the phenomena happening at the contact. Contact refers to a junction where

the organic layer (in this dissertation pentacene film) interfaces the metal electrodes.

Effect of contact can cause voltage drop at the metal interfaces, therefore the effective

voltage across the channel may be substantially lower than the applied voltage. In this

case the extracted effective carrier mobility from the transistor characteristic result in a

number that is lower than expected. Since contact directly affects the electrical

performance, including the effective carrier mobility, this chapter thoroughly investigates

the effect of metal-organic semiconductor junction in pentacene field effect transistors.

Following the fabrication of any organic transistor, to evaluate its electrical

behavior, a number corresponding to the effective carrier mobility is extracted from the

experimental data using the conventional MOSFET model. So far various methods of

device fabrication have been investigated in the literature. These methods use the

extracted effective carrier mobility as a figure of merit to evaluate their effect. These

methods include, experimentally trying various electrodes, insulator layers, coating

methods for the pentacene layer, improvement of film morphology at the contacts and

several other factors. Most of these reports use qualitative hypothesis as a way to explain

the observed results.

However using this model and method for evaluating the electrical performance of

organic transistors do not include all the parameters affecting the electrical behavior. The

carrier mobility of any material is a constant value at a given temperature. Therefore any

observed electrical behavior should have an explanation in the model representing these

types of transistors and not to a change in the carrier mobility. As an example, consider

the case where two transistors are fabricated with the same device structure. While all

parameters are same in these two transistors, two different metals are chosen for the

electrodes. In this case any difference observed in the electrical behavior between these

two transistors is only due to the effect of these metals (their interface to organic

semiconductor) and not to a change in the carrier mobility. Of course using the method

76

mentioned above, one may conclude that fabrication of transistors using these two metals

result in different carrier mobility.

In summary, using the MOSFET model is not adequate to explain the electrical behavior

of organic transistors. Moreover relating any change of device structure to the carrier

mobility results in misleading conclusions. Following sections in this chapter explain the

effect of metal-semiconductor interface on the electrical behavior for pentacene

transistors. Albeit in this dissertation pentacene is used, one may use the same

investigation method to understand the metal-semiconductor contact for other organic

materials.

This chapter starts with critically reviewing the possible effects of the contact in a

transistor’s electrical behavior. Later, to understand the effect of the metal-organic

semiconductor energy barrier, systematic experimental measurements using a Kelvin

probing method are done to quantitatively analyze this effect. In this case, 2D

electrostatic simulation is done to model the measurements, hence accurately extract the

voltage drops at source and drain electrodes. This chapter concludes with the explanation

and discussion of the current-voltage behavior of the barrier and will shed some light on

the metal-organic semiconductor energy barrier.

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6.1 Energy barrier versus film morphology at metal-semiconductor interface

As already mentioned in section 2.10.3 of this dissertation, the reduction of

transistor current by the metal-semiconductor junction can be caused by 1) the energy

barrier between the metal work function and HOMO level of pentacene, 2) change of

film morphology at this interface.

The change in film morphology sometimes is optically apparent due to lack of film

continuity at this boundary. Lack of film continuity or change of crystalline structure at

metal-semiconductor interface causes regions with no or low electrical conductivity. If

there are voids at the contacts, these voids should be considered to evaluate the effective

channel width. Other effects such as change of conductivity due to crystalline structure at

the boundaries should be addressed to evaluate their effects. As mentioned in the

background section of this dissertation, typically an intermediate layer is coated to

improve the pentacene adhesion to the metal electrodes. As being reported numerously

in literature this improvement of the film coating may result in higher effective carrier

mobility than that of with no intermediate layer.

The energy difference between metal work function and HOMO level of

pentacene is another parameter in the effect of contact. For this reason one of the design

criteria for organic transistors is the proper choice of metal for the source and drain

electrodes. Typically to minimize the effect of this barrier for charge injection/collection,

as a rule of thumb, a metal electrode that has a work function close to the HOMO level of

pentacene (or other p-type organic semiconductor) is used. As it will be explained in this

chapter, as this energy difference increases the effect of contact become more apparent.

This can be observed as a substantial voltage drop that happens at the metal-

semiconductor interface. In addition to voltage drop, reverse biased metal-semiconductor

junction (reverse Schottky diode) allows less number of carriers to flow from the source

to drain electrode. In this case the low current level results in reduction of effective

(extracted) carrier mobility.

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6.2 Investigation of metal-pentacene junction using Kelvin probe method

Effect of metal-semiconductor junction is well-established in inorganic field

effect transistors such as silicon. However in case of the organic field effect transistors,

the effect of this junction is not investigated thoroughly. In this work, systematic

measurements are done to be able to 1) observe the effect of this junction, 2) quantify this

effect and 3) to understand the electrical behavior of the metal-semiconductor junction

from the device physics point of view.

For the measurements planned in this work, pentacene is used as the organic layer to

investigate the metal-semiconductor junction in organic field effect transistors. Pentacene

transistors are p-channel transistors with hole conduction in the channel. The energy level

of the Highest Occupied Molecular Orbital (HOMO) of pentacene is 5 ev and the energy

level of its Lowest Unoccupied Molecular Orbital (LUMO) is 2.8 ev [55]. It is expected

that an energy forms at the metal-pentacene junction. This energy barrier is the energy

difference between the metal work function and the HOMO level of pentacene. To

investigate the effect of the energy difference at the metal-pentacene junction, different

metals with higher and lower work function levels than 5 ev (HOMO level of pentacene)

are chosen. The chosen metals are Au and IrO2 with the reported work functions slightly

higher than 5 ev [56, 57] as well as Ti and RuO2 with work functions substantially lower

than 5 ev [58].

Metal Work functions

(ev)

IrO2 5.1-5.6

Au 4.9-5.1

RuO2 4.6

Ti 4.3

Table 7. Metal work functions.

Device fabrication using the electrodes mentioned above is explained in chapter 3 of this

dissertation.

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In this dissertation, for the investigation of the contact effect, a four-point probing

method (also known as Kelvin probing) is used. The Kelvin probing method compares

the expected voltage profile along the channel (based on the applied biases) to the

measured voltage profile along the channel. This comparison shows the effect of the

contact as will be explained in detail later.

In this work to measure the voltages in the channel, intermediate electrodes are used. The

top view of these devices and their geometries are shown below. Two intermediate pairs

within the channel of the transistor are used to have more data points for the extraction of

the voltage drops at contacts.

Figure 32. Device structure used for Kelvin measurement.

Based on the metals’ work functions and HOMO level of pentacene, using

different metals mentioned above, the following energy band level for transistors

(|VGS|>0 and |VDS|>0) are expected.

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(a) (b)

Figure 33. Energy level of pentacene interfacing metals (a) Ti or RuO2 (b) Au or IrO2 .

Since pentacene transistors are p-channel devices, holes are the majority carriers

conducting in the channel. In this case if these carriers move from the lower to higher

energy levels, they face an energy barrier. In contrast, they do not face any barrier

moving from higher to lower energy levels.

In figure 33, let’s assume the direction of applied electric field is from source to drain

electrode. In this case, positive charges flow from source to drain electrode. If the work

function of the used metal is lower (i.e. 4.3 ev) than the HOMO level of pentacene (5 ev),

then there is an energy barrier at source-pentacene interface. However when the carrier

reach the drain interface, they need to go from the higher energy level (HOMO of

pentacene) to lower energy level of metal (4.3 ev). In this case it is expected the energy

barrier to form at source-pentacene interface and not at the drain-pentacene interface.

This energy barrier may be small or large depending on the used metal.

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6.2.1 Kelvin probing – Experimental observations

The idea of Kelvin probing method (4-point probing method) is to measure the

voltage profile along the channel and compare that to the expected voltage profile based

on the applied voltages. This comparison helps in understanding the effect of contact,

including the electrical model that explains the metal-organic semiconductor barrier. The

goal of this chapter is to extract the electrical behavior of this barrier and shed light on

the possible nature of this barrier.

The rest of this section reports the experimental observation of Kelvin probing

measurements when the transistors are fabricated using different metal electrodes.

Following that, in section 6.4, using the numerical modeling, an accurate method of

extraction of voltage drops is reported. One may use the same modeling approach for

other materials and device structures to model the expected voltage profile. Using the

modeling and observed experimental observations, voltage drops at the metal-pentacene

interfaces are calculated. Later in this section using the extracted voltage drops at the

contacts, the current-voltage characteristics of the contacts are plotted. This electrical

behavior is the first experimental demonstration of metal-organic semiconductor contact

characteristics in the organic field effect transistors.

For the Kelvin probe measurements (5 probes including the gate electrode) used

in this work, the source electrode is always grounded (biased at 0 volt). This is done by

setting the source-measurement unit (SMU) of the 4155A parameter analyzer connected

to source a constant 0 V. The drain electrode sweeps from 0 to -40 V that is done by

setting the SMU of the parameter analyzer to a variable voltage sweep mode. These

sweeps are done at different gate voltages. Typically the gate voltage is also sweeps from

0 to -60 V. In the case of the Kelvin probe measurements, in addition to the voltage

sweeps mentioned above, the voltages at two intermediate electrodes are measured using

high input resistance VMUs (voltage measurement units). The intermediate electrodes

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measure the voltages along the channel. Having numerous electrodes with small pad size

is preferred to measure the voltage along the channel precisely.

If the transistor operates in the linear region, the profile of electric field along the channel

will be linear. In case of Kelvin probing technique, if the transistor operates in the linear

region, having two intermediate electrodes would suffice to extract the voltage profile

along the channel.

When the source electrode is biased at higher potential compared to the drain

electrode, holes flow from the source to the drain electrode. For the metals used in this

work, it is expected that the transistors fabricated using Ti or RuO2 have higher energy

barriers at the source-pentacene interface than that of Au or IrO2 metals. The schematic

of the expected barrier at source-pentacene barrier is shown below.

(a) (b)

Figure 34. Barrier expected based on the theoretical energy levels and applied bias (a) Ti or RuO2 (b) Au or

IrO2.

As already mentioned above, the structure used for Kelvin probing in this dissertation has

two intermediate pairs of electrodes along the channel. To simplify the analysis, the

transistors are biased in the linear region of operation (|VDS|<<|VGS|). This biasing assures

a linear voltage profile along the channel and having only two voltage nodes would be

needed to extrapolate this line along the channel. To have the transistor operate in the

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linear region (|VDS|<<|VGS|), a high gate-source voltage of -60 V and a drain-voltage of -5

V is chosen. This means that the drain electrode is biased at -5 V while the source

electrode has 0 volt. This voltage profile is shown as a black dotted line on figures

through this chapter.

Since in this case the direction of the electric field is from the source to drain electrode,

for all analysis it is assumed that the source electrode is at L=0 µm while the drain

electrode is at L=500 µm.

The following plot shows the measured voltages at four pads that were designated along

the channel for a transistor fabricated using RuO2 metal. To plot these voltages, the center

points of each pad are used. To illustrate the concept of the existence of a barrier at the

source-pentacene interface, one of the measured samples (red dashed line) was

extrapolated to L= 0 (source electrode). This qualitative observation suggests that a

substantial voltage drop exists at the source electrode-pentacene interface. This agrees

with the theoretical expectation of a barrier shown in Figure 34.

Figure 35. 4-point probe measurement done in transistor fabricated using RuO2 metal.

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As mentioned earlier, the work function of Ti (4.3 ev) is also less than the HOMO level

of pentacene. Therefore a similar measurement and study using Ti metals is done to

prove the validity of the existence of a barrier at the source-pentacene interface. Figure

36 shows the data collected for a 4-point probe transistor fabricated using Ti metal. Due

to oxide imperfection, only one sample was functional and that is plotted below.

Figure 36. 4-point probe measurement done in transistor fabricated using Ti metal.

The extrapolated red line in the above figure suggests that a voltage drop exists at L=0

µm (source electrode-pentacene interface). This conclusion made since the applied

voltage at the source electrode is zero volts but the extrapolated voltage profile implies

that at the source electrode-pentacene interface, a lower voltage exists. This implies that a

portion of the applied voltage is dropped at this metal-semiconductor interface. As

already mentioned, the aim of this section is to qualitatively report the observations and

later in section 6.4, quantitative analysis of these measurements is done.

So far the two metals investigated (RuO2 and Ti) have lower work function than the

HOMO level of pentacene. In these cases, as expected, the Kelvin probing suggests a

large voltage drop existing at source electrode-semiconductor interface. To go a level

deeper in understanding the metal-organic semiconductor it is worth to investigate the

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case where the work function of the metal is higher than the HOMO energy level of

pentacene. The most widely used metal in fabrication of organic (especially pentacene)

field effect transistors is Au. Gold has a work function that is slightly higher than the

HOMO level of pentacene. Therefore it is expected the energy difference at source-

pentacene junction be smaller than that of RuO2 and Ti (metals with W << 5 ev). For the

study of metals with work function higher than the pentacene’s HOMO level, two metals

of Au and IrO2 are chosen. Based on the reported work functions of these two metals the

work function of IrO2 (5.1- 5.6 ev) is higher than that of Au (4.9 - 5.1 ev).

Figure 37 and 38 shows the result of 4-point measurements on transistors fabricated with

Au and IrO2 respectively.

Figure 37. 4-point probe measurement done in transistor fabricated using Au metal.

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Figure 38. 4-point probe measurement done in transistor fabricated using IrO2 metal.

Throughout this chapter the pair of electrode located at L= (95 µm, 155 µm) is referred as

the top pair and the pair located at L= (185 µm, 275 µm) is referred as the bottom pair.

The extrapolated lines to L=0 µm in figures 37 and 38 suggest a voltage drop that is

substantially lower than that of Ti and RuO2. In the next section the COMSOL simulation

explains the slopes observed at the top and bottom intermediated pairs.

Considering the observations so far, to eliminate the effect of the energy barrier at the

source-pentacene interface in OFETs, one may use a metal with a work function

substantially higher than the HOMO level of pentacene. Higher work function is

preferred since the exact work functions and HOMO levels depend on the impurities and

processing of the materials. Figure 39 shows the expected energy band diagram when

there is no barrier at the source-pentacene interface. As will be shown later, in this work,

transistors fabricated using IrO2 electrodes result in higher effective (extracted) carrier

mobility than those made using other electrodes.

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Figure 39. Proposed metals that result in no-barrier at source-pentacene interface for transistor application.

As mentioned earlier in this chapter to evaluate the voltage drops (effect of

contact) from the experiments, the effect of intermediate Kelvin pads should be

considered. These pads perturb the electric field along the channel since they have finite

sizes. The metal-semiconductor barrier not only exists at the source interface but also at

the intermediate pads. As an example in the case of top intermediate pair, the electrodes

are close to each other. Therefore if one ignores the effect of these Kelvin pads, it is

expected that the voltages read at each electrode to be close to each other. However

experimental data suggests that even though the Kelvin pads are close to each other the

voltages read at each one may be considerably different.

Let’s consider the case of Kelvin probing measurement that is done on transistors

fabricated using IrO2. The measurements are already shown in figure 38. Let’s consider

one of the measured samples as shown below. If one ignore the effect of the intermediate

electrodes, the extrapolated dotted red line to L=0 µm and L=500 µm shows substantial

voltage drop at drain-interface and small voltage drop at source interface for top

intermediate pairs. On the other hand if we use the bottom intermediate pair for this

analysis there is a small voltage drop both at source and drain interfaces. This

discrepancy in the analysis can be explained by adding the effect of the junction barriers

at the intermediate Kelvin pads.

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Figure 40 Experimental data of Kelvin probing of transistors fabricated using IrO2 metal, blue arrows show the

expected voltage drops.

Interestingly the 2D simulation of the intermediate Kelvin pads with no barrier at the

vicinity explains the slopes observed in Figure 40. Therefore the conclusion made above

which implies the existence of a considerable voltage drops at the interfaces is wrong.

The Kelvin probes perturb the voltage profile since they have finite size and they form a

barrier when they interface the organic layer.

89

6.3 Modeling of measurements using COMSOL FEA analysis

The idea of Kelvin probing is to measure the voltage profile along the channel.

On the other hand the expected voltage profile based on the applied voltages and with the

assumption of no barrier at the contacts is known. Comparing this profile to the measured

Kelvin probe voltages allows the extraction of the voltage drops at the contacts. In real

case measurements, probe pads (or even probe tips) affect the electric field along the

channel. Therefore to interpret the data accurately, the effect of these measurement pads

must be taken into consideration.

In transistors with 4-point probes used in this work, the size of the intermediate pads is 50

µm x 50 µm. Obviously these pads contact the pentacene layer, therefore the energy

barrier at the metal-semiconductor interface exists for these pads as well. The effect of

the measurement pads is crucial to determine the actual profile of the electric field.

The conclusion made in section 6.2 was that if the work function of the source electrode

is lower (i.e. 4.3 ev) than the HOMO level of pentacene (5 ev), a barrier forms at the

source-pentacene interface when holes flow from the source to the drain electrode. As the

work function of metal is getting close to the HOMO level of pentacene, this energy

barrier reduces as well.

The above conclusion is also helpful in determining the possible energy barriers that may

exist at the intermediate electrodes. Figure 41 shows the interfaces that the metal-

semiconductor barriers exist in Kelvin probe devices used in this work. These barriers are

based on the direction of the electric field being from the source to the drain electrode.

The effect of these pads in modifying the electric field along the channel will become

more apparent as the gap between intermediate electrodes reduces. Therefore to

understand the effect of the intermediate pads, device simulation with DC analysis is

needed.

90

Figure 41. Energy barriers in 4-point devices.

This simulation helps to find the expected value of the voltages at the Kelvin probing

pads, given the finite size of the pads and given the existence of the energy barriers at the

pads. These voltages will generally be different than expected for ideal probing pads.

Ideal infinitely small Kelvin probing pads would accurately measure the voltages/electric

field along the channel without perturbing it, while the real pads will modify the electric

field in the channel. Comparison of the expected and measured voltages can be used to

extract the unperturbed voltage in the channel and therefore an accurate contact voltage.

The detailed explanation of this calculation is done in section 6.4 of this dissertation.

To simulate the effective electric field along the channel, 2D electrostatic analysis is done

with COMSOL multiphysics. Since the goal of this analysis is to interpret the

experimental data, the scenario that is shown in Figure 41 is simulated. The model used

91

in this analysis is shown in Figure 42 for the case where the barrier is at the right hand

side of the intermediate pads.

For the pentacene layer, a semiconducting layer with the sheet resistivity of 10-3

Ω is

used in the model. The value of 10-3

Ω is chosen based on the sheet resistivity of lightly

doped silicon however using other sheet resistivity for the semiconductor does not alter

the voltages at the intermediate pads.

To simulate the effect of barriers at interfaces of the intermediate pads, a resistive border

with 5 µm length is used. This border was added around the entire pad except for the left

hand side of each pad as shown in figure 42. The resistivity of this layer was swept in the

simulation to match the measured voltages of the experimental data.

The effect of this resistive border on the voltage profile is more apparent for top pair of

electrodes in which the gap between pads is smaller than that of bottom pair. If there is no

border at metal-semiconductor interface, the voltages measured at each pad for top pair

would be close together (since the pads are close together). However in real

measurements these two voltages are considerably different. Therefore the measured

voltage slope at top intermediate pair is higher than that of with no resistivity border

(barrier). In the next section the simulation result of voltage profiles as a function of

boundary resistivity is shown and analyzed.

The effect of this interface resistivity on the voltage profile is more apparent for the top

pair of electrodes in which the gap between the pads is smaller than the bottom pair. If

there is no resistivity at the metal-semiconductor interface, the voltages measured at each

pad for the top pair would be close together (since the pads are close together). However

in real measurements these two voltages are considerably different. Therefore the

measured voltage slope at top intermediate pair is higher than that of with no resistivity

(barrier). In the next section the simulation result of the voltage profiles as a function of

boundary resistivity is shown and analyzed.

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(a) Meshed model (b) COMSOL simulation, electrostatic physics, dc analysis result

Figure 42. Electrostatic simulation considering the effect of measurement pads.

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6.4 Extraction of voltage drops at metal-semiconductor junctions using COMOSL model

So far in the previous sections of this chapter, experimental observations of 4-

point probing of transistors as a function of metal work function are reported. These

observations are based on incorporation of intermediate measuring electrodes along the

channel of the transistors. Later, as the first step in analyzing the experimental data, 2D

electrostatic simulations are done. These simulations are needed to include the effect of

measurement pads on the electric field. In this simulation to replicate the effect of the

barriers at the intermediate electrodes, a layer with higher resistivity than channel

(pentacene) layer at the metal interfaces is used. If this interface resistivity increases, the

difference between voltages at each pad for a given pair of electrodes increases. This

results in higher voltage slope at the intermediate pads. Figure 43 shows the result of this

simulation for various ratios of boundary resistances.

Figure 43. Simulation of devices with resistive area added to the intermediate pads.

As shown above, as the resistivity at the metal boundary for intermediate electrodes

increases, the voltage slope increases. This increment in slopes is more noticeable in the

top intermediate pair than the bottom pair. In this section to analyze each experiment,

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proper simulation from the above figure is used. The simulation that is used in the case of

each set of samples is the one that can explain the voltage drops at the source-pentacene

interface for all the samples. This means that the voltage drops extracted at each specific

metal-pentacene junction should result in approximately same range of numbers and

there should not be substantial discrepancy between the extracted voltage drops between

samples of a specific metal-pentacene junction.

This simulation along with the experimental data helps the extraction of the voltage drops

at contacts.

To extract the voltage drops at contacts (hence the IV behavior of contacts), let’s consider

and analyze the experimental observations of devices fabricated using each metal (energy

barrier) separately.

As already mentioned, in pentacene field effect transistors, the energy barrier exists at the

source-pentacene interface. Let’s first consider all the experimental observations of

Kelvin probing of transistors fabricated with RuO2 metals as shown in figure 44.

If one uses the voltage profile not considering the effect of intermediate pads, the

extracted voltage drop at contacts for most of measurements would suggests the existence

of a negative barrier(s). Obviously such a barrier is not practically realizable.

Figure 44 shows the experimental data collected using 4-point probing for RuO2

electrodes versus the simulation data. This simulation is based on having the resistive

barrier on the right hand side of intermediate pads. As mentioned before to explain the

voltage profile (voltage slopes) at each intermediate pair, a resistive layer with proper

resistivity should be used.

The simulated data is based on biasing the source electrode at zero volt and drain

electrode at –5 V. The interface resistivity that can explain the experimental data is a

boundary resistivity that has 200 times more resistance than the pentacene layer. As

shown in figure 44, the slopes of the simulation are -0.0133 and -0.0115 for top and

bottom intermediate pairs respectively. These slopes are calculated based on the voltages

read at each pad from the COMSOL simulation.

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Figure 44. Measurement data of transistors with Kelvin probes that are fabricated using RuO2 electrodes versus

2D simulation.

The first step in extraction of voltage drops at the source and drain interfaces is to find

the electric field along the channel unperturbed by the contacts for each device under test

(V=Ex where x is the position along the channel). So far it is known that if the voltages

applied at the source and drain electrodes are 0 and -5 V respectively, then the ideal

expected voltage profile without the contact barriers or Kelvin probe pads is -0.01x where

x is the position along the channel. This slope can be achieved only if there are no

barrier(s) at metal-semiconductor junctions.

To find the actual voltage profiles along the channel, we need to compare the

measurements and simulated data (which include the effect of Kelvin pads). The

following table shows the procedure to find the voltage profile.

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Table 8 – extraction of voltage profile using by matching the simulated data to experimental observation,

applied electric field is -0.01 since -5 volts is applied across the channel with 500 µm length

As shown above the actual voltage profile along the channel is:

( )

To find C in above equation we need to find the voltage difference between measured

voltages and simulated voltages at pair of electrodes. As an example consider the data for

the first sample which is plotted as a red line in figure 44. For simplicity let’s use only the

top pair of intermediate pairs for analysis. Using the analysis done in table 8 we can find

the actual voltage profile in the absence of Kelvin probe pads along the channel as shown

with dotted green line in figure 45. It is assumed that the voltage barrier at source and

drain is independent of the presence of the Kelvin probe pads.

The voltage drop at source and drain electrodes is the difference between the extracted

and the applied voltage profile. In this example the voltage drop at the source electrode-

pentacene interface is 1.83 V and the voltage drop at the drain electrode-pentacene

interface is 0.98 V.

Figure 45. Extraction of voltage drops at contacts.

Top pair Bottom pair

Slope of simulation applied voltage profile

-0.0133 (-5V/500µm)= -0.01

Slope of measurement actual voltage profile

S measurement (S measurement/0.0133)×(-0.01)+C

Slope of simulation applied voltage profile

-0.0115 (-5V/500µm)= -0.01

Slope of measurement actual voltage profile

S measurement ( S measurement /0.0115)×(-0.01)+C

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Figure 46 shows the extracted voltage drops at source-pentacene and drain-pentacene

interfaces for all the samples prepared with RuO2. For all these voltage drops extraction,

same method mentioned above is used. Since the extraction method uses mathematical

calucaulation for some samples the extrcated voltage drop at drain-pentacene interface

have negative values. The negative voltages in reality implies the existance of no barrier

at the interface.

Figure 46. Extracted voltage drops for transistors made with RuO2.

As shown in figure 46, substantial voltage drop exists at the source-pentacene interface.

To confirm the validity of the existence of a barrier, Titanium metal (with work function

lower than HOMO of pentacene) is also used as the electrodes in fabrication of transistors

with the intermediate pads. Figure 47 shows the measured data with respect to the

simulation and the extracted voltage drops at Ti-pentacene interfaces. As it is apparent in

the figure, similar to the devices fabricated using RuO2, the barrier exists at source-

pentacene interface.

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Figure 47. (Left) Measured data of transistors fabricated using Ti, (Right) Extracted voltage drops at interfaces.

Rest of this section explains the experimental observations for transistors fabricated using

metal electrode with work function higher than 5 ev. For these experiments Au and IrO2

with higher but close work function to 5 ev is used. Same method of analysis is used in

interpreting the experimental data and extracting the voltage drops at contacts.

Figure 48 shows the experimental data collected using Kelvin probing for transistors

fabricated using Au metal for the source and drain electrodes. This plot also includes the

simulation data. To explain the experimental observations for the Kelvin probing done

with Au electrodes, similar simulation as before is used. The difference between the

former simulation to that of used for Au is that the boundary resistivity at the

intermediate pads is substantially smaller. In this case the border resistivity of 10 times

higher than the semiconductor layer is used.

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Figure 48. Measurement data of Au electrodes versus 2D simulation.

The result of extraction of voltage drops at metal-pentacene junctions for all samples are

shown in Figure 49. As it is shown the voltage drops for transistors fabricated using Gold

electrodes are substantially lower than that of made using Ti and RuO2. This implies that

the energy barrier formed at metal-pentacene interface has been considerably reduced as

the metal work function goes higher in energy.

Figure 49. Extracted voltage drops for transistor made with Au.

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To confirm the above observation another metal, IrO2, with even higher work function

than Au is used. Figure 50 shows the experimental data of transistors fabricated using

IrO2 metal as the source and drain electrodes. The simulation plot in figure 50 (yellow

lines) is the 2D model when there is no barrier at contacts. As shown in the plot, the

simulations that include the barriers at the intermediate pads cannot explain the

experimental observations, although the simulation with the no barrier at contacts is in

approximate agreement with the experimental data.

Figure 50. Measurement data of IrO2 electrodes versus 2D simulation.

To be able to extract the voltage drops at the source interface and the drain interface from

the above experimental observation, since there is no energy barrier exists at IrO2-

pentacene contacts, the small difference between the measurements and the model with

perfect contacts is due to a resistance that exists at all sides of the pads. This resistance

forms when the pentacene interfaces a metal electrode. This small resistance may exist

for the other measurements as well but since the barrier is the main non-ideal contact

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effect at the intermediate pads, the effect of the resistance was not included in the

previous analysis.

To mode this resistance, a COMSOL simulation with the model having a resistive

boundary around the intermediate pads is used. In this case, the 1µm width of the

resistive border which has twice larger resistance than the pentacene layer is used. The

simulated voltage at the intermediate pads along with the experimental data is shown in

figure 51 (a). The extracted voltage drops at the source and the drain interfaces using this

model are shown in figure 51 (b). The extracted voltages drop shows negligible voltage

drops both at the source and the drain interfaces.

Figure 51. Extracted voltage drops for transistor made with IrO2.

So far all the voltage drops at the metal-pentacene interfaces are extracted using

transistors fabricated with different metal work function. Figure 52 shows the quantitative

comparison of these voltage drops on the same scale. As we know having negative

voltage drops would imply that no energy barrier exists. Therefore comparing the

positive voltage drops in figure 52 shows that at the source-pentacene interface (where

the energy barrier exists), metals with lower work functions (such as RuO2 and Ti) result

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in higher voltage drop than that of made using Au and IrO2. Comparing the voltage drops

for transistors fabricated using IrO2 shows even lower voltage drop than that of made

using Au electrodes. Therefore, using metal with even higher work function than Au is

preferred. As it is shown in next section, the transistor behavior of devices made using

IrO2 results in higher effective carrier mobility than that of Au.

Figure 52. Comparison of voltage drops at source/drain-pentacene interface using different metals.

In summary, in this section the experimental observation of the transistors fabricated with

metal electrodes having work function of higher and lower than pentacene HOMO energy

levels are quantitatively analyzed. For the analysis and extraction of the voltage drops at

contacts, 2D COMSOL simulation is done. This simulation includes the effect of barriers

at the metal-pentacene junction for the intermediate pads. The conclusion of this analysis

is that the choice of electrodes affects the voltage drop at the source-pentacene interface.

In the case of measurements done in this work, the lower the work function gets (< 5 ev),

the effect of the energy barrier become more noticeable. The analysis shows that the

existence of a significant voltage drop at the source-pentacene interface when metals with

lower work function (i.e. 4.3 ev) is used. These metals include RuO2 and Ti. On the other

103

hand the metals with higher work function such as Au and IrO2 show small or no voltage

drop at the metal-semiconductor junction.

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6.5 Current-voltage behavior of barriers (metal-semiconductor) in pentacene transistors

In the previous section, the method of extraction of voltage drops at the metal-

pentacene interface was investigated. For simplicity and for the proof of concept, only the

case in which the drain electrode had -5 V with respect to source electrode (0 V) was

considered. In this case the gate-source was biased at -60 V.

The conclusion made so far is that there is a voltage drop at source-pentacene interface

and this voltage drop is a function of metal’s work function. This voltage drop is due to

an energy barrier that exists at the source-pentacene interface.

To prove the validity of this comment, Figure 53 shows the extracted voltage drops at the

source-pentacene and drain-pentacene interface. If the voltage drops were due to a higher

resistivity material at the interfaces, then there should be voltage drops at both interfaces

(source/drain pentacene interfaces). However the figure shows that the voltage drops

happens at the source-pentacene interface and not at the drain-pentacene. This implies the

validity of the existence of an energy barrier at this interface.

Figure 53. Extracted voltage drops at metal-pentacene interfaces for transistors made using RuO2.

If we use a diode symbol (metal-semiconductor Schottky diode) representing the energy

barrier, the equivalent model will be the one shown below.

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Figure 54. Metal-pentacene junction represented with forward and reversed biased barriers.

In the above figure, at the metal-semiconductor junction there is a reversed biased diode.

To understand the effect of this reverse biased junction, let’s investigate the possible

current conduction mechanisms at the metal-semiconductor interfaces. These

mechanisms try to explain the conduction of majority carriers. These charge conduction

mechanisms include diffusion, thermionic emission, tunneling through the barrier, and

generation/recombination of carriers in traps or tunneling through traps. In a given metal-

semiconductor junction a combination of the mentioned mechanisms could exist but

often one is the dominant mechanism in the current conduction.

Thermionic emission happens when the carriers have enough energy to surpass the

energy barrier. [59] The tunneling is a phenomenon due to the quantum mechanical

tunneling of carriers through the energy barrier. [60] Diffusion current happens when

there is a change in concentration of carriers at metal-semiconductor interface. In this

case the carriers want to flow from higher concentration to lower concentration. The

generation conduction expected to happen at the metal-organic interfaces due to existence

of traps. When an electron/hole goes in to the trap state they leave a hole/electron behind.

This generated charge may tunnel through the barrier or if the number of them builds up

they may diffuse.

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Let’s continue this section with the analysis of each mechanism further in detail. The

Current density in the case of diffusion and thermionic emission follows the equation

below.

(

) ( (

) )) Equation 10 [59]

In the above equation q is the electron charge, T is temperature in Kelvin, Nc is the

effective density of states located in the semiconductor near the metal interface, ɸ is the

energy barrier, Va is the bias voltage and Vt is thermal voltage. In case of thermionic

emission, ‘ʋ’ in the above equation is the Richardson constant (A*) and in case of charge

diffusion mechanism is the mobility (µ) multiplied by the electric field at the interface

(Ɛ).

(

) ( (

) ) ; Thermionic emission; A* is Richardson constant, A is area

(

) ( (

) )) ; Diffusion; (

( )

) [60]

In the above equation ND is the charge density in the semiconductor. All the above

equations are for the metal-n-type semiconductor junction and to change them for metal-

p-type semiconductor ND should with replaced by NA and Nc should be replaced with

Nv.[61]

In the case of quantum tunneling mechanism of charges, the current density is the product

of charge density at the interface and the probability of tunneling.

(

) Where k is:

√

In the above equation ‘n’ is the density of charge at the metal-semiconductor interface,

VR is the reversed biased voltage and ɸ is the probability of tunneling. [61]

The qualitative comparison of the dependency of the current density on the applied

voltage for the three mechanisms is shown below (arbitrary numbers on axes).

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Figure 55. IV behaviors of current density using different conduction mechanism.

The above figure suggests that for the reverse biased metal-semiconductor junction, the

current has a constant value at saturation (Isat) if the conduction mechanism is thermionic

emission or diffusion. On the other hand if the current increases as the voltage increases

in the reverse biased case, the current conduction may be due to tunneling of carriers

through the barrier and/or trap assisted tunneling. In the case of trap assisted tunneling,

the IV behavior of the reverse biased metal-semiconductor Schottky barrier is expected to

be a linear function. [62]

Although all the mentioned charge conduction mechanisms are for the metal-inorganic

semiconductors they are still valid for the metal-organic semiconductor. The detail

analysis of charge conduction in the metal-organic semiconductor is beyond the scope of

this dissertation. Rest of this section explains the extracted IV behaviors of contact and

possible phenomenon that can explain such a behavior.

Now that possible current conduction mechanisms for metal-organic semiconductor are

reviewed, let’s consider the measurements done in this work.

To extract the IV behavior of barriers, the electrical current that is passing across the

channel as a function of the voltage drops is needed. Therefore same method of analysis

done in section 6.4 is needed for other drain-source voltages. For the analysis done

earlier, the drain-source voltage with respect to gate-source voltage is chosen in a way

that the transistor operates in the linear region. In this case the voltage profile along the

channel is a linear line. To make sure that for the rest of analysis the transistor still

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operates in the linear region, the drain-source voltages of up to -20 V is used for the

extraction of voltage drops, while the gate-source voltage is biased at -60 V (|VDS|<V|GS|).

Figure 56 shows the current-voltage behavior of the source-pentacene barrier when the

transistors are fabricated using RuO2 metal for electrodes. As it is shown in this plot, the

current that passes along the channel has a linear dependency on voltage drops at contact.

Figure 56. Current-voltage behavior of source-pentacene barrier when RuO2 metal is used.

As already mentioned earlier the work function of RuO2 is approximately 4.6 ev and

HOMO level of pentacene is -5 ev. Therefore the expected barrier height is ~ 0.4 ev. In

this case if the charge conduction happens solely due to thermionic emission the

following table shows the theoretical expected reverse saturation current for different

barrier heights in the proximity of 0.4 ev. For this calculation the thickness of the

inversion layer is assumed to be 5 nm.

Barrier height Reverse saturation current

0.3 9.6 µA

0.35 1.4 µA

0.4 0.2 µA

0.45 28 nA

Table 9. Reverse saturation current of RuO2-pentacene due to thermionic emission.

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Figure 57 shows the plots of the extracted contact IV behavior of the transistors

fabricated using RuO2 metals versus the reversed biased Shcottky diode when the

thermionic emission is the only charge conduction mechanism. The discrepancy between

the theoretical contact behavior due to thermionic emission to that of measured suggests

that the dominant charge conduction at this interface is proportional to the reverse biased

voltage. With this observation the dominant charge conduction in reverse biases metal-

pentacene junction is likely due to tunneling of carrier through the barrier and/or trap

assisted tunneling due to existence of defects at the interface.

Figure 57 – Expected reversed biases metal-semiconductor junction solely due to thermionic emission of carriers

versus extracted IV behavior of metal-pentacene barrier

Figure 58 shows similar plot for reverse biased junction at Au-pentacene interface as well

as that of RuO2-pentacene interface. Similar as the previous IV extraction, the drain-

source voltages of up to -20 V is used in the extraction of voltage drops due to the barrier

for both cases. As shown in the figure, the one to one comparison of voltage drops at the

contact for Au to that of RuO2, suggests more voltage drops at RuO2-pentacene than that

of Au-pentacene. The inverse slope of the lines (ΔV/ΔI) which shows the resistivity of

the barrier, suggest substantially higher barrier for RuO2 contacts to that of Au. Later in

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chapter 7 these IV behaviors used to analyze the effect of contact as the transistor’s size

shrinks.

Figure 58. Current voltage behavior of reversed biased Au-pentacene barrier versus RuO2-pentacene barrier.

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6.6 Transistor characteristics of fabricated devices using various electrodes

So far in sections 6.1 - 6.5 of this chapter, metal-pentacene junction interfaces are

investigated. This investigation is done by modulating the energy barrier at this junction

and measuring the voltage drop that happens at the contact. It is concluded that the

reverse biased barrier at this junction results in the higher voltage drops at the contacts

when the difference between pentacene’s HOMO level and work function of metal

increases. Obviously the effect of metal-semiconductor junction in organic transistors is

directly related to transistor characteristic.

In addition to discussions made so far, it is worth in here to talk about the

electrical characteristic of transistors fabricated using different metal electrodes. Let’s

start this discussion with transistors fabricated using Au and IrO2 metals. According to

the previous section the metal-pentacene interface will have small (no) barrier when

metals with work function equal or higher than 5 ev are used. This may be the reason that

Au metal is widely used in fabrication of pentacene (p-type organic) transistors. Figure -

59 and 60 show the transistor characteristic of devices fabricated using Au and IrO2 metal

respectively.

Figure 59. Electrical characteristic of transistors fabricated using Au

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Figure 60. Electrical characteristic of transistors fabricated using IrO2.

The above characteristics show that the three terminal devices fabricated using Au and

IrO2 show transistor behavior. The transistor behavior can be observed since 1) gate

dependent conduction happens, 2) the transistor has two regions of linear and saturation

and 3) at some gate-source voltage the transistor turns off.

Chapter 4 of this dissertation explains the method of extraction of carrier mobility and

threshold voltage based on the observed experimental data. Using the method mentioned

earlier, the transistors fabricated using the IrO2 metal result in effective extracted carrier

mobility and threshold voltage of 0.1 cm2/Vs and -16 V respectively. In the case of

transistors fabricated using Au metal, the extracted carrier mobility is also 0.085 cm2/Vs

with threshold voltage of -16 V.

Figure 61 and 62 show the electrical behavior of devices fabricated RuO2 and Ti

respectively. As it is apparent in the figure, as the gate source voltage increases, at a

given drain-source voltage the drain-source current increases. However the device is

conducting even at no gate-source voltage (VGS=0 V) and also the drain-source current

does not follow the square dependency on the gate voltage in the saturation region.

However if a transistor equation (conventional MOSFET equation) is used in the

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extraction of effective carrier mobility, this device shows effective mobility of 0.006

cm2/Vs.

Threshold voltage in organic transistor is a function of several parameters. These

parameters include the film properties of the organic layer, traps in the organic layer and

the charge accumulation at the metal-semiconductor interface. The latter can be due to

traps near the interfaces hence band bending at the metal-semiconductor junction.[63, 64]

This may be the reason that the transistors fabricated using RuO2 and Ti metals do not

have complete off-state.

Figure 61. Three terminal behavior of devices fabricated using RuO2.

Figure 62. Three terminal behavior of devices fabricated using Ti.

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7. Discussion

As reviewed in the background chapter of this dissertation, contact effects in

pentacene (organic) transistors might be due to changes of film morphology near the

interface and/or the energy barrier at the metal-semiconductor interface. In the case of

organic field effect transistors, the effect of the contact can be observed when a portion of

the applied voltage is dropped at the contacts.

To quantitatively analyze the effect of the contact, three main methods can be used. One

method is to use the electrical characteristic of transistors to extract the contact resistance.

This method presumes that the contact has a resistive nature.[65-67] This method is

explained in detail in the background section of this dissertation. Using this method as a

way to analyze the contact effect has two drawbacks. One drawback is the assumption of

the resistive nature of the I-V characteristic. The other drawback is, this method does not

distinguish the effects of contacts at the source and drain electrodes.

In some cases the barrier may have a resistive behavior and in others it may not, therefore

in this method to begin the contact analysis with the assumption of the contact having a

resistive behavior may be misleading.

The second method that has been reported a few times in the literature (for organic

transistors) is the so called Kelvin probing method which measures the voltages along the

channel. [9, 68, 69] This potentiometry method uses the AFM tip to scan the voltages

along the channel; hence it can accurately extract the voltage drop that happens at the

contacts. In this method the voltage drop that happens at the source and drain interfaces

can be measured respectively; meaning this method distinguishes the contact effect at

source and drain interfaces. The drawback of this method is its complexity and the

requirement of costly equipment.

A third method that is introduced (for organic FETs) and thoroughly investigated in this

dissertation is using Kelvin pads for measuring the voltages along the channel. In this

case rather than the AFM tip, intermediate microfabricated contact pads are used to

measure the voltages along the channel. The advantage of the method introduced in this

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dissertation, is its simple fabrication and measurement procedure. Moreover, this method

can distinguish the voltage drops that happen at source and drain electrodes. One may use

a similar approach to that explained in this dissertation for other transistors with different

device structures and materials.

As already mentioned, one of the factors causes voltage drops at the contacts is

the existence of an energy barrier at the metal-semiconductor junction. In the case of the

electrode-pentacene interface, the choice of metal or intermediate layer at the metal

interface could affect the I-V behavior of transistors. In this case if the carrier mobility is

extracted from the I-V behavior without considering the effect of contact, that is an

effective carrier mobility which includes the behavior of the channel as well as the

contact. Since in the literature the effect of contact is not considered, the extracted

effective carrier mobility is often simply called the carrier mobility.

The choice of electrode material can affect the energy barrier at metal-semiconductor

interface. As shown in this dissertation in detail, modulating the barrier height at the

metal-pentacene interface affects the transistor behavior because the contact

characteristics change as a function of the size of the energy barrier. These effects can be

observed indirectly in the transistor characteristic and extracted device carrier mobility,

or directly, as has been done here, by probing the voltage in the channel.

In the experiments done in this work, transistors with different metal work functions were

fabricated. These metals are Au, IrO2, RuO2 and Ti. The published work functions of Au

and IrO2 are 5.1 eV and 5.6 eV respectively. Moreover the reported work functions of

RuO2 and Ti are 4.6 eV and 4.3 eV respectively.[58]

As shown in detail earlier, Au metal can cause a barrier at the source-pentacene interface.

This is despite the fact that gold has a published work function close to or slightly higher

than the published HOMO value of pentacene (-5 eV). However this barrier is much

smaller than that of when metals with lower work functions (i.e. 4.3 eV) are used. In the

case of experiments done in this work, IrO2, with a work function higher than the HOMO

level of pentacene results in a negligible barrier and this may be one of the best metals

that can be used in the fabrication of pentacene field effect transistors. Note that a small

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resistance (in contrast to a barrier) at the semiconductor-metal interface gave the best fit

to the data for IrO2, as described in Chapter 6. The transistors fabricated using IrO2 show

effective carrier mobility of 0.1 cm2/Vs versus 0.08 cm

2/Vs for gold contacts and 0.006

cm2/Vs for RuO2 contacts.

The exact energy levels (metal work functions and HOMO level of pentacene) depend on

the material properties and may vary depending on the fabrication processes. For this

reason choosing metal with substantially higher work function is preferred to begin with.

In this case it is expected that no energy barrier to exist at metal-pentacene junction. As

an example, IrO2 in this work which has a reported work function of -5.6 ev is a good

candidate to be used in the fabrication of pentacene transistors. Another metal that also

has higher work function is WO3 and similar to IrO2, the transistors fabricated using WO3

is expected to have no energy barrier at metal-pentacene junction. [70]

The effect of contact can be observed on the transistor characteristic as well. [71] As will

be shown later, this effect on the IV behavior of transistors can affect the extracted

effective carrier mobility. As reported by Kawasaki et al. [72], the change in the barrier

height (at the metal-pentacene junction) directly affect the JDS-VDS behavior of

transistors.

As it is shown in figure 63, for a given biasing criterion (drain-source voltage and gate-

source voltage), the current level of transistors made using Au and IrO2 are at least five

times higher than that of made using RuO2 metal. As it was shown quantitatively, the

voltage drops that happen at the source-pentacene junction in the case of transistors made

using RuO2 are considerably higher than those in transistors made using Au or IrO2. In

the case of transistors made using RuO2, it is expected that a portion of the applied

voltage will be dropped at source-pentacene junction (due to the energy barrier at this

junction), therefore the actual voltage drop that exists across the channel is lower than

that of applied at the electrodes. In this case, since the voltage that exists across the

channel is smaller than that of applied, lower current is expected compared to the case

where there is no voltage drops at contacts. Therefore in transistors made using RuO2

metal, lower effective carrier mobility of 0.006 cm2/Vs is extracted from the IV behavior

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of transistors compared to the effective carrier mobility of ~0.1 cm2/Vs for Au and IrO2

where there is negligible or no barrier.

The effect of the contact sometimes can also be seen qualitatively on the IV behavior of

the transistors, typically as a concave curvature at low drain-source voltages. Therefore in

the linear region of operation, the transistor rather than having a linear IDS-VDS slope has

a curvature. As an example let’s compare the transistor characteristic of devices made

using Au, IrO2 and RuO2 metals. Figure 63 shows the IDS-VDS behavior of transistors at

low drain-source voltage when Au, IrO2 and RuO2 are used. As can be seen there is a

slight concave down curvature for transistors made using Au and RuO2 metals. On the

other hand for transistors made using IrO2 metal, the transistor characteristic show linear

dependency of IDS on VDS in the linear region of operation. The concave curvature

(compared to a linear behavior) consequently causes lower current level for a given

biasing criteria.

(a) (b)

(c)

Figure 63. IDS-VDS behavior of transistors at low drain-source voltages for (a) transistors made using Au (b)

transistors made using IrO2, (c) transistors made using RuO2.

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To understand the effect of contact in more detail, let’s analyze the IV behavior of the

barrier (reverse biased metal-pentacene junction) and its consequent effect in the

fabricated devices. As is shown in figure 64, the extracted current-voltage behavior of the

barrier (reversed biased metal-pentacene junction), shows the voltage dependency of the

current. This clearly implies that the charge conduction mechanism cannot be explained

by thermionic emission. In case of thermionic emission it is expected, in the reverse

biased junction, the current would have a constant value and will not depend on the

reverse biased voltage.

Figure 64 – IV behavior of reverse biased metal-pentacene junction in pentacene field effect transistors

In the reverse biased Schottky junction the voltage dependency of the current can be

explained by tunneling of carriers through the energy barrier and/or trap assisted

tunneling. However in the case of the tunneling through the energy barrier, as the applied

voltage increases (drain-source voltage increase) the barrier width reduces. Therefore the

reverse current will exponentially increase as the reverse voltage increases.[73] In the

case of the extracted IV behavior of the reverse biased metal-pentacene junction, the

current has a linear dependency on the applied voltage as shown above. This linear

dependency can be explained by trap assisted tunneling.[62, 74]

It has been reported that at a metal-pentacene junction a high density of traps exists.

Density of traps at the metal-pentacene junction for the pentacene field effect transistors

has been investigated in the literature [75-78]. One of the parameters that affect the

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density of traps is the choice of metal electrodes. As reported by [79], when pentacene

interfaces a metal, localized states form at the interface. In the case of trap assisted

tunneling, the charge conduction occurs by tunneling between multiple traps. [80]

Another important conclusion that can be made from figure 64 is that, as the

current density increases, the voltage drop at the contact increases as well. For a given

drain-source voltage, the current density for short channel devices is higher than that of

long channel devices. This means that the expected voltage drop at the contact for short

channel devices is higher than that for long channel devices for a given drain-source

voltage.

As the current density increases, it is expected that the role of contact (voltage drop at

contact) becomes more dominant. In this case the voltage that exists across the channel is

lower than that applied, causing less drain-source current compared to the case where

there is no voltage drop at contacts. Therefore the effective carrier mobility will be

smaller compared to the case where the contact does not cause a voltage drop.

As is found by [81], pentacene transistors made using long channel structures (L > 5µm)

show effective carrier mobilities of 0.1-1 cm2/Vs. However keeping all parameters same,

using the short channel device structures (5 µm), the effective carrier mobility of only

0.01 cm2/Vs can be achieved. As mentioned above, as the channel length reduces the

effect of contact (voltage drop at contact) increases for a given applied voltage. This

voltage drop directly affects the IDS-VDS behavior of transistors, meaning lower current is

measured for a given drain-source voltage compared to the measured current when there

is no contact barrier. This will result in reduction of the effective carrier mobility.

120

8. Conclusion

The focuses of this dissertation have been on 1) fabrication and characterization

of field effect transistors using novel pentacene derivatives, and 2) investigation,

extraction and understanding of the metal-pentacene contacts in the pentacene field effect

transistors.

In the former work mentioned above, the two novel pentacene derivatives

investigated are the first water soluble pentacene and a very thermally stable pentacene.

Devices made using a very thermally stable pentacene (TTPO) show transistor behavior

similar to that of conventional field effect transistors. Study of temperature sweeps on

these transistors shows that as the temperature goes up to 200 ºC, not only do the devices

survive but also the electrical conduction of the transistors increases at a given bias. This

results in a higher extracted effective carrier mobility from the fabricated transistors at

higher temperatures. The effective extracted carrier mobility of transistors increases from

10-9

cm2/Vs at room temperature to 9×10

-9 cm

2/Vs at 200 ºC. The reason behind the low

carrier mobility for TTPO transistors requires further investigation but it can be related to

the material properties of TTPO and/or the effect of contact.

In the latter work done in this dissertation, a novel potentiometery method is

introduced and investigated. This method is a Kelvin probing method that uses

microfabricated contacts along the channel of transistors to measure the voltages in the

channel. Consequently the measured voltages can be used to extract the voltage drops at

the contacts.

One important factor that is thoroughly investigated in this dissertation is the perturbation

effect of Kelvin pads on the electric field along the channel. For this reason, 2D

electrostatic simulation is done which includes the effect of intermediate Kelvin pads on

the voltage profile. Hence to accurately extract the voltage drops at source and drain

electrodes, the measured voltages along with the simulated voltage profile are used to

extract the voltage drops at the contacts.

121

This potentiometery method can measure the voltage drops that happen both at the drain

and source contacts. The advantages of the method used in this dissertation are while

yielding important information, the cost and complexity are substantially lower than the

AFM methods.

Moreover, using the method developed, it is concluded that a barrier exists at the source-

pentacene interface in the pentacene field effect transistors. This barrier is a function of

metal work function and only exists at source-pentacene interface and not at drain-

pentacene interface. The extracted voltage drops both at the drain and source interfaces

show that the nature of the contact is not just a resistance since the voltage drops are

different at source and drain interfaces. More specifically the voltage drop at source-

pentacene interface increases as the barrier height between metal work function and

HOMO level of pentacene increases.

The voltage drop that exists at source-pentacene junction is due to an energy barrier.

This energy barrier (for hole conduction) exits between the metal work function and

HOMO level of pentacene. Since the reported HOMO level of pentacene is -5 eV, to

reduce the barrier height, metals with higher work functions than 5 eV (i.e. 5.1 eV)

should be used. As is mentioned in the discussion section, since the exact HOMO energy

level and metal work function may vary depending on the fabrication procedures,

preferably a metal with substantially higher work function than 5 eV should be used (i.e.

IrO2 with work function of 5.6 eV). This assures that a change in the HOMO level of

pentacene and metal work function would be less likely to cause an energy barrier.

The contact affects the IV behavior of transistors as well. It is shown in this dissertation

that the RuO2-pentacene barrier causes larger voltage drop at contact compared to

Au/IrO2-pentacene barrier. Therefore for a given applied VDS, transistors made using

RuO2 have more voltage drop at the contact, causing a lower voltage to exist along the

channel than that applied at the drain-source electrodes. In this case lower drain-source

current will be sensed compared to that of when no barrier exists. This lower drain-source

current will result in lower effective carrier mobility compared to the case when contact

does not cause a voltage drop.

122

The extracted current-voltage behavior of the contact shows that as the current density

increases the voltage drop at contact increases. As is expected, as the channel length of

the transistors shrinks, the current density increases, therefore for short channel

transistors it is expected that the voltage drop is higher than that of long channel

transistors for a given applied voltage. This effect should be addressed in the design of

transistors with high effective carrier mobility by either completely eliminating the effect

of contact or use the long channel device structures.

Furthermore the extracted IV behavior of the metal-pentacene barriers shows a

linear dependency of the current on the applied voltage. This dependency shows that the

charge conduction mechanism in the reverse biased metal-pentacene junction (barrier) is

not dominated by thermionic emission. Moreover if the charge conduction mechanism

was due to tunneling through the barrier it is expected that the current would increase

exponentially as the barrier width reduces (applied voltage increases). As mentioned in

the discussion section, the linear dependency of the current on the applied voltage can be

explained by trap assisted tunneling of carriers.

123

Appendix A:

Process run sheet for organic transistors

Fabrication of patterned devices

Date: #wafers:

1. Piranha etch (glass beaker)

Sulfuric: peroxide 2:1

Temp. 115 °C

Time 10 min.

DI overflow rinse 5 min.

2. HF etch (plastic beaker)

DI water: HF 50:1

Time 15 secs.

Temp. RT


3. HCL etch (glass beaker)

DI water: peroxide: HCL 6:1:1

Temp. 95 °C

Time 10 min.


Dry, nitrogen gun

4. Dry Oxidation(100nm oxide)

Temp. 1100 °C

Total time 60 min.

Thickness 100 nm

Comments:

Date: #wafers:

5. Backside 1813 PR coat

4000 rpm 1 min

Bake temp. 115 °C

Time 1 min

124

BOE etch (plastic beaker)

700 ml BOE

Time 3 min.

Temp. RT

Rinse 5 min.

Dry

Comment:

Remove resist

6. Liftoff patterning of electrodes

LOR-2A coat

Spin speed 3000 rpm

Spin time 45 s

Bake temp 175°C

Bake time 5 min.

Shipley 1813 coat

Spin speed 4000 rpm

Spin time 45 s

Bake temp 115°C

Bake time 1 min.

Edge bead removal – removing the photoresist at the edge of wafer/chip by acetone

Expose

Expose time 7 seconds

Expose intensity 12mW/cm2

Develop

700 ml MF319

Temp. RT

Develop time 50 seconds

Rinse

Inspection

125

Comment:

Electrode deposition and liftoff

Date: #wafers:

7. Electrode deposition (thermal evaporation)

Deposit 10 A° – Cr

Evap. rate

Deposit 1000 A° – Au

Evap. rate

8. Lift off process

700 ml Acetone

Time 30 min

Rinse and dry

Organic coating

Date: #wafers:

1. Piranha etch (glass container)

Sulfuric: peroxide 2:1

Temp 115 °C

Time 10 min.

Rinse 5 min.

Dry, N2 gun

Comment

2. Optional Treatments (WSP only)

Au treatment

10µl of thiol in 10 ml ethanol

Time 1 hr

Ethanol rinse

IPA rinse

DI water rinse

SiO2 treatment

126

10 ml HMDS-immersion

Time 1 hr

3. Organic layer coating

Solution process thermal evaporation

mg pentacene mg pentacene

Solvent: volume AC power:

Spin speed: rpm thickness:

Bake Temp.: Evap. Rate:

Thickness:

127

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