Conformal Ref

Encounter® Conformal®

Equivalence Checking Reference Manual

Conformal ASIC, Conformal Ultra, and Conformal Custom

Product Version 7.2May 2008

1997– 2008 Cadence Design Systems, Inc. All rights reserved.Printed in the United States of America.

Cadence Design Systems, Inc., 2655 Seely Avenue, San Jose, CA 95134, USA

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discontinued immediately upon written notice from Cadence.

Patents: Cadence Product Encounter™ Equivalency Checker described in this document, is protected byU.S. Patent [6,842,884]

Disclaimer: Information in this publication is subject to change without notice and does not represent acommitment on the part of Cadence. The information contained herein is the proprietary and confidentialinformation of Cadence or its licensors, and is supplied subject to, and may be used only by Cadence’scustomer in accordance with, a written agreement between Cadence and its customer. Except as may beexplicitly set forth in such agreement, Cadence does not make, and expressly disclaims, anyrepresentations or warranties as to the completeness, accuracy or usefulness of the information containedin this document. Cadence does not warrant that use of such information will not infringe any third partyrights, nor does Cadence assume any liability for damages or costs of any kind that may result from use ofsuch information.

Restricted Rights: Use, duplication, or disclosure by the Government is subject to restrictions as set forthin FAR52.227-14 and DFAR252.227-7013 et seq. or its successor.

Encounter Conformal Equivalence Checking Reference Manual

Contents

About This Manual. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2Command Reference. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Command Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Wildcards . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28Using UNIX Commands with Conformal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30ABSTRACT LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32ADD ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35ADD BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37ADD CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39ADD COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41ADD CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43ADD DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44ADD ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46ADD ECO LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47ADD ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48ADD ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50ADD IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52ADD IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53ADD IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55ADD INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57ADD INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59ADD INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61ADD LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63ADD MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65ADD MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68ADD MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

May 2008 3 Product Version 7.2


ADD NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72ADD NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74ADD NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75ADD NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76ADD NOTRANSLATE LINES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78ADD NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80ADD OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82ADD OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84ADD PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86ADD PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88ADD PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93ADD PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95ADD PRIMARY INPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97ADD PRIMARY OUTPUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98ADD RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99ADD RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105ADD SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108ADD SUPPLY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110ADD TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112ANALYZE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114ANALYZE DATAPATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116ANALYZE ECO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119ANALYZE IMPLICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121ANALYZE MULTIPLIER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123ANALYZE NONEQUIVALENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124ANALYZE POWER ASSOCIATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126ANALYZE RETIMING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128ANALYZE SETUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132APPLY PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133ASSIGN PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135BACKWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137BREAK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138CHANGE GATE TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139CHANGE NAME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141CHECK LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143CHANGE NET TYPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146



CLOSE SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147COMMIT CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150CONTINUE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154COPY MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155DELETE ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157DELETE BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158DELETE CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159DELETE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161DELETE CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163DELETE DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164DELETE ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166DELETE ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167DELETE ECO PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168DELETE IGNORE RTLCHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169DELETE IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170DELETE IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171DELETE INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172DELETE INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173DELETE INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174DELETE LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175DELETE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176DELETE MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178DELETE MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179DELETE NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181DELETE NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183DELETE NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184DELETE NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185DELETE NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186DELETE OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187DELETE OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 188DELETE PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 189DELETE PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190DELETE PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 192DELETE PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 193DELETE PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194



DELETE PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195DELETE RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196DELETE RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198DELETE SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199DELETE TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 200DIAGNOSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204ELABORATE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205EXIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208FLATTEN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209FORWARD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210GENERATE ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213HELP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 214INVERT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216LICENSE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 218MAP ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 219MAP KEY POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 220MOS2BUFIF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221MOVE INSTANCE DOWN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223OPEN SCHEMATICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224OPTIMIZE PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225PIN GROUP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 228PRINTENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 230PROVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231READ CPF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233READ DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234READ FSM ENCODING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247READ LEF FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 249READ LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250READ MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 257READ MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259READ ROM PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260READ RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261READ PATTERN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263REDUCE MOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 266



REMODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 268REMOVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 272REPORT ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274REPORT ALIAS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275REPORT BLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 276REPORT CLOCK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278REPORT COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280REPORT COMPARE DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 281REPORT COMPARE TIME . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284REPORT COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287REPORT CPF LOGIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 288REPORT CUT POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289REPORT DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290REPORT DATAPATH RESOURCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291REPORT DESIGN DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 292REPORT DESIGN SIMILARITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295REPORT DYNAMIC CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 296REPORT ECO CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 297REPORT ECO CHANGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298REPORT ECO PATCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 299REPORT ENVIRONMENT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 300REPORT FLOATING SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303REPORT GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305REPORT HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 309REPORT IGNORED INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 311REPORT IGNORED OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312REPORT INSTANCE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313REPORT INSTANCE CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314REPORT INSTANCE EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315REPORT KEY POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 316REPORT LIBRARY DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 318REPORT LOWPOWER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 320REPORT LOWPOWER DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 321REPORT MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 324REPORT MESSAGES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328REPORT MODULE ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330



REPORT MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331REPORT MOS DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334REPORT MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 336REPORT NET ATTRIBUTE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 337REPORT NET CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 339REPORT NOBLACK BOX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 340REPORT NOTRANSLATE FILEPATHNAMES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 341REPORT NOTRANSLATE MODULES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 342REPORT OUTPUT EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 343REPORT OUTPUT STUCK_AT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 344REPORT PARTITION KEY_POINT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 345REPORT PARTITION POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 346REPORT PARTITION RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 347REPORT PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 348REPORT PIN CONSTRAINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 350REPORT PIN DIRECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351REPORT PIN EQUIVALENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353REPORT PRIMARY INPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354REPORT PRIMARY OUTPUTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355REPORT PULSE GENERATOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 356REPORT REMOVED INSTANCE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 357REPORT RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 358REPORT RETENTION MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 359REPORT RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 360REPORT SEARCH PATH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 362REPORT STATISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363REPORT TESTCASE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364REPORT TEST VECTOR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366REPORT TIED SIGNALS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 368REPORT UNMAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 370REPORT VERIFICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375RESET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376RESET HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377RESOLVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 378RESTORE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 380



RUN HIER_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 381RUN PARALLEL COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 385RUN PARTITION_COMPARE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387SAVE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388SAVE HIER_COMPARE RESULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389SAVE SESSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390SEARCH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391SET ABSTRACT MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 392SET ANALYZE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 397SET_ATTR INPUT_PRAGMA_KEYWORD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 398SET CASE SENSITIVITY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 399SET COMMAND PROFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400SET COMPARE EFFORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 401SET COMPARE OPTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402SET CPU LIMIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 404SET DATAPATH OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 406SET DIRECTIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 408SET DOFILE ABORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 415SET EXIT CODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 416SET FLATTEN MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417SET FPGA TECHNOLOGY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 422SET GATE REPORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 423SET GUI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 425SET HDL DIAGNOSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 426SET HDL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 427SET IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 431SET LOG FILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 435SET LOWPOWER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 437SET MAPPING METHOD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 440SET MOS MODEL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 443SET MULTIPLIER IMPLEMENTATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 444SET MULTIPLIER OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 447SET NAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 448SET PARALLEL OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 454SET RETIMING OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 456SET ROOT MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 457



SET RULE FILTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 458SET RULE HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 459SET SCREEN DISPLAY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 461SET SPICE OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 462SET STATETABLE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 464SET SYNTHESIS_OFF_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 465SET SYNTHESIS_ON_COMMAND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 466SET SYSTEM MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467SET UDP PIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 468SET UNDEFINED CELL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 469SET UNDEFINED PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 471SET UNDRIVEN SIGNAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472SET WIRE RESOLUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 473SET X CONVERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 474SET XC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 476SETENV . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 477SUBSTITUTE BLACKBOX MODELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 478SUBSTITUTE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 479SYSTEM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 481TCLMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 482TEST RENAMING RULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483UNIQUIFY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 487USAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 489VALIDATE CIRCUIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 490VALIDATE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 494VERSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 497VPXMODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 498WRITE BLACKBOX WRAPPER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 499WRITE COMPARED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 501WRITE DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 503WRITE ECO DESIGN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 505WRITE HIER_COMPARE DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507WRITE LIBRARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 512WRITE MAPPED POINTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 513WRITE MEMORY PRIMITIVE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 515WRITE PARTITION DOFILE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 517



WRITE RULE CHECK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 519

3HDL Rule Check Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 521

Directive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 522DIR1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 523DIR1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 524DIR1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 525DIR2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 526DIR2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527DIR3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 528DIR3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529DIR4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530DIR4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531DIR4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 532DIR4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 533DIR5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 534DIR5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 535DIR5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 536DIR5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 537DIR6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 538DIR6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540DIR7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 541DIR7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 542DIR8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543DIR9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 544DIR9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 545DIR9.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 547File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549FIL1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 551HRC1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553HRC1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 554HRC1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 555HRC1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556



HRC1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 557HRC2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 558HRC2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 559HRC2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 560HRC2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 561HRC2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 562HRC3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 563HRC3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 564HRC3.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 565HRC3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 566HRC3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 567HRC3.4a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 568HRC3.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 569HRC3.5b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 570HRC3.5c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 571HRC3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572HRC3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 573HRC3.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 574HRC3.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 575HRC3.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 576HRC3.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 577HRC3.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 578HRC3.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 579HRC4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580HRC5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 581HRC6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582HRC7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 583Ignored . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 584IGN1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585IGN1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 586IGN2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 587IGN2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 588IGN2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 589IGN3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 590IGN3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591IGN3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 592



IGN3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 593IGN3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 594IGN3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 595IGN4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596IGN5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597IGN5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598IGN5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 599IGN6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 600IGN6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 601IGN7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 602Register Transfer Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 603RTL1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 608RTL1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 609RTL1.2a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610RTL1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 611RTL1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 612RTL1.5a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 613RTL1.5b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 614RTL1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 615RTL1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 616RTL1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617RTL1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 618RTL1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 619RTL1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 620RTL1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 621RTL1.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 622RTL2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 623RTL2.1a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624RTL2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625RTL2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626RTL2.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627RTL2.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628RTL2.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629RTL2.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 630RTL2.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 631RTL2.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 632



RTL2.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 633RTL2.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 634RTL2.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 635RTL2.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 636RTL3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 637RTL3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 638RTL3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 639RTL3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 640RTL3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 641RTL4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 642RTL4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 643RTL4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 644RTL4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 645RTL5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 646RTL5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 647RTL5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 648RTL5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 649RTL6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 650RTL6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 651RTL6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 652RTL6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 653RTL6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 654RTL6.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 655RTL7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 656RTL7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 657RTL7.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 658RTL7.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 659RTL7.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 660RTL7.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 661RTL7.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 662RTL7.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 663RTL7.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 664RTL7.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 665RTL7.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 666RTL7.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 667RTL7.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668



RTL7.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 669RTL7.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670RTL7.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 671RTL7.17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 672RTL7.18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 673RTL7.19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 674RTL7.20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 675RTL7.21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 676RTL8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 677RTL8.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 678RTL8.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 679RTL8.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 680RTL8.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 681RTL9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 682RTL9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 683RTL9.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 684RTL9.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 685RTL9.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 686RTL9.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 687RTL9.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 688RTL9.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 689RTL9.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 690RTL9.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 691RTL9.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 692RTL9.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 693RTL9.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 694RTL10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 695RTL11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 696RTL12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 698RTL12.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 699RTL13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 700RTL13.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 701RTL13.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 702RTL14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 703RTL14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 704RTL15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 705



RTL15.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 706RTL15.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 707RTL16.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 708RTL16.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 709RTL17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 710RTL17.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 711RTL18.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 712RTL18.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 713RTL18.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 714RTL18.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 715RTL19.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 716RTL20.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 717RTL20.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 718RTL20.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 719SPICE Netlist Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 720SPI1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 721SPI1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 722SPI1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 723SPI1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 724SPI3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 725SPI4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 726SPI4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 727SPI5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 728SPI5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 729SPI7.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 730SPI7.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 731SPI8.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 732System Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 733SV1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 734SV1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 735SV1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 736SV1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 737SV1.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 738SV1.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 739SV1.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 740SV1.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 741



SV1.9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 742SV1.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 743SV1.11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 744SV1.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 745SV1.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 746SV1.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747SV1.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748SV2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 749SV2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750SV3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 751User-Defined Primitive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 752UDP1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 753UDP1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 754UDP1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 755UDP2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 757UDP2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758UDP3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759UDP3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 760UDP3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 761UDP4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 762UDP4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 763Verilog . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 764VLG1.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 767VLG1.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 768VLG1.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 769VLG1.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 770VLG2.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 771VLG2.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 772VLG2.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 773VLG3.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 774VLG3.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 775VLG3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 776VLG3.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 777VLG3.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 778VLG3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 779VLG3.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 780



VLG4.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 781VLG4.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 782VLG4.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 783VLG4.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 784VLG5.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 785VLG5.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 786VLG5.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 787VLG5.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 788VLG5.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 789VLG5.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 790VLG6.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 791VLG6.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 792VLG6.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 793VLG6.3a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 794VLG6.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 795VLG6.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 796VLG6.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 797VLG6.7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 798VLG6.8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 799VLG6.10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800VLG6.12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 801VLG6.13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 802VLG6.14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 803VLG6.15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 804VLG6.16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 805VLG7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 806VLG8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 807VLG9 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808VLG9.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 809VLG9.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 810VLG9.4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 811VLG10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 812VLG10.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 813VLG10.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 814VLG10.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 815VLG11.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 816



VLG11.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 817VLG12.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 818VLG13.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 819VLG13.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 820VLG13.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 821VLG14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 822VLG15.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 823VLG16.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 824

4Modeling Messages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 825

F1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 826F2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 827F3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 828F5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 829F6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 830F7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 831F8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 832F10 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 833F11 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 834F12 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 835F13 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 836F14 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 837F14.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 838F16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 840F17 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 841F18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 842F19 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 843F20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 844F21 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 845F23 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 846F25 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 847F26 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 849F27 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 850F28 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 851



F30 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 852F32 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 853F34 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 854F34.1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 855F34.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 856F34.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 857F36 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 858F39 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 859F41 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 860F42 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 861F43 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 862

5Tcl Command Entry Mode Support . . . . . . . . . . . . . . . . . . . . . . . . . . . 863

find . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 865get_compare_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866get_compare_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 866get_exit_code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 867get_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868get_fanins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868get_fanouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868get_gate_count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868get_gate_id . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868get_gate_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 868get_handle_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869get_instances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 869get_keypoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 870get_map_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871get_module_definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 871get_names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872get_nets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 872get_parent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 873get_pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 874get_ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 875get_primitive_type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 876



get_property . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 877get_root_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878get_unmap_points . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 878set_current_module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879echo_result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879get_license_mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879get_version_info . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 879help . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880objtype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880usage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 880

Index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 881



About This Manual

This manual documents commands, HDL rule checking messages, and modeling messagesfor the following Encounter® Conformal® Equivalence Checking solutions:

■ Conformal Extended Checks

Conformal Extended Checks has equivalency checking capabilities with functionalchecks for ASIC design flows.

■ Conformal Ultra

Conformal Ultra includes Extended Checks and extends equivalency checkingcapabilities to datapath synthesis and layout.

■ Conformal Custom

Conformal Custom includes Conformal Ultra and extends equivalency checkingcapabilities to digital custom logic and custom memories.

■ Conformal LowPower

Conformal LowPower enables low power equivalence and functional checks for isolationcells, level-shifter cells, and retention-register cells.

Audience

This manual is written for experienced designers of digital integrated circuits who must befamiliar with RTL, synthesis, and design verification; as well as having a solid understandingof UNIX and Tcl/Tk programming.

Related Documents

For more information about the Conformal family of products, see the following documents.You can access these and other Cadence documents with the CDSDoc online documentationsystem. For a complete list of documents provided with this release, see the CDSDoc library.


Encounter Conformal Equivalence Checking Reference ManualAbout This Manual

■ Encounter Conformal Equivalence Checking User Guide

Describes how to install, configure, and use Conformal to verify RTL, gate, or transistor-level designs.

Conventions

Convention Definition

Bold Case Indicates the command name.

UPPERCASE Indicates the required minimum character entry.

< > Indicates required arguments. Do not type the angle brackets.

[ ] Indicates optional arguments. Do not type the square brackets.

| Indicates a choice among alternatives. Do not type the verticalbar.

\ The backslash character (\) at the end of a line indicates that thecommand you are typing continues on the next line.

… Indicates multiple entries of an argument.

* Indicates that LEC lets the wildcard (*) represent zero or morecharacters.



2Command Reference

This chapter describes the Encounter® Conformal® commands. The commands arepresented in alphabetical order.

This chapter also includes the following sections:

■ Command Syntax on page 26

■ Wildcards on page 28

■ Using UNIX Commands with Conformal on page 30


Encounter Conformal Equivalence Checking Reference ManualCommand Reference

Command Syntax

■ Conformal commands are not case sensitive.

■ For every Conformal ADD command, there are corresponding DELETE and REPORTcommands. For example:

ADD OUTPUT EQUIVALENCES

DELETE OUTPUT EQUIVALENCES

REPORT OUTPUT EQUIVALENCES

■ Conformal commands adhere to the “3-2-1” rule, which reduces the number ofcharacters you must type.

❑ 3: Type the leading three characters of the first term.

❑ 2: Then type the leading two characters of the second term.

❑ 1: End with the leading character of the third term.

In some cases, you must use more characters to resolve ambiguity. In this manual, theminimal sets of characters you must type are shown as uppercase letters in the syntax.

When you use the 3-2-1 rule in conjunction with the syntax guide to resolve any possibleambiguity, you reduce the number of characters in a command, as the following exampleshows:

ADD OUtput Equivalences

becomes

add ou e

■ Reduce the number of characters you type for command options to the characters shownin uppercase in the syntax, as the following example shows:

add output equivalences out10 out20 -module sub_mod1 -revised

becomes

add ou e out10 out20 -m sub_mod1 -r



Searching the Help Database for Specified Strings

Use the SEARCH command to search s the Help database of commands and options formatches to strings you specify.

Viewing TCLmode Help Information

The HELP command also displays a list of Conformal TCLmode commands. While inTCLmode, use the following syntax:

HELp

To view command usage for a specific command, use the HELP command followed by thecommand name.

HELp [command_name]

System prompt and command example:

TCL_SETUP> help set_current_module

Viewing Conformal UNIX-Style Man Pages

Conformal includes a man directory housed in: <install_dir>/doc/mann/.

Important

Observe the following requirements for viewing UNIX-style man pages:

❑ You must type the entire command name.

❑ Do not apply the 3-2-1 rule (described below).

❑ Do replace each space in the command name with an underscore ( _ ).

1. To access this resource from your UNIX shell, add the following variable:

% setenv MANPATH “<install_dir>/doc:$MANPATH”

2. Type the following:

man command_name

For example:

man read_designman set_system_mode



Wildcards

On an as-needed basis, Cadence adds wildcard pattern-matching support to Conformalcommands. The syntax convention that alerts you to wildcard support is the asterisk (*).

If you use a pattern where a filename or design object is expected, Conformal EquivalenceChecker expands the pattern using the same conventions as in the UNIX shell.

■ Triggering pattern matching for filenames

To trigger pattern matching for filenames, a string must include at least one asterisk (*),question mark (?), or a pair of square brackets ( [ ] ).

■ Triggering pattern matching for design objects

To trigger pattern matching for design objects, a string must include at least one asterisk(*) or question mark (?).

In arguments that are considered patterns, the following characters have special meaning: ^,{, }, [, ], ?, *. The dash (-) also has special meaning when it falls between square brackets.

Note: When you use wildcards for design objects, a wildcard can match a string that includesthe hierarchical delimiter (/). For example, the pattern *[10] matches the design objecta/b/c[10].

When you use wildcards for filenames, every wildcard applies to part of a single directory orfilename (this convention is the normal UNIX convention). For example, the pattern *.v doesnot match the filename a/b/c.v.

Special Characters for Filename and Design Object Pattern-Matching

WildcardCharacter Definition Example

? Match any single character. a?c matches:

aac, abc, a4c, a?c

* Match any (possibly empty) string. a*c matches the following:

ac, abc, a*c



[ ]

That is, “[”followed bycharacters and“]”

Match any single character listedbetween the square brackets: “[”and “]”.

If the first character is “^”,Conformal Equivalence Checkermatches any single character notlisted between the brackets.

If the list shown between thebrackets includes x-y, ConformalEquivalence Checker matches allcharacters in the range x–y.

To match square brackets, you mustinclude the escape characterimmediately preceding the squarebracket.

To be matched, the characters “-”and “]” must appear first in the list(possibly after ^).

Note: For design objects, recall thata string triggers pattern matchingwith an asterisk or question mark. Inthose cases, this convention applies.

For filenames:

a[145] matches the following:

a1a4a5

For design objects:

a*[145] matches the following:

ab1a34at5

a*\[145\] matches the following:

ab[145]a3[145]at[145]

^ At the beginning of the pattern, thecharacter “^” negates the result ofthe match:

^a* matches any name that doesnot begin with a.

\ Matches only the character thatfollows the “\” character.

a\[10] matches the following:

a[10]

But it does not match:

a1a0





Using UNIX Commands with Conformal

To execute a UNIX command from within LEC or an LEC command script, start the line withan exclamation point “!” or with the SYSTEM command. When you execute commands in thisway, they display to the standard output, and LEC records them in a log file, if one is active.

Using the -all Option

This option applies within the given defaults. For example, the syntax for the ADD OUTPUTEQUIVALENCES command is as follows:

ADD OUtput Equivalences<primary_pin primary_pin*...>[-Invert <primary_pin*...>][-ROot | -Module <name*> | -All][-Golden | -Revised | -Both]

In the above syntax, -golden is a default. Therefore, if you type the command with primarypin names and the -all option, but no other option, this command specifies output pinequivalences on all output boundary module pins in the Golden design.

{p1,p2,…} Matches any string matched by anyof the sub-patterns listed.

design/{top,sub{5,11}}/*.vmatches the following:

design/top/a.vdesign/sub5/b.vdesign/sub11/c.v

Braces can nest.a/{d{e,f},g{h,i}}_0 matchesthe following:

a/de_0a/df_0a/gh_0a/gi_0





Using the -both Option

When you use this option in conjunction with a specific name (for example, a pin name), thatname must appear in both designs. Otherwise, LEC returns an error message. For example,the syntax for the ADD PIN EQUIVALENCES command is as follows:

ADD PIn Equivalences<primary_pin primary_pin*...>[-Invert <primary_pin*...>][-ROot | -Module <name*> |-All][-User | -Hier][-Golden | -REvised | -Both]

Notice -both in the above syntax. If you specify three primary pins (for example, a1, a2, anda) and the -both option; all three pin names must exist in both the Golden and Reviseddesigns. If they do not, LEC returns an error message.

If you specify a1, a2, a and include the -revised option; LEC applies equivalence to thepins in the Revised design only (even if these three pins also exist in the Golden design).

Saving the Command’s Output to a File

To save the command’s output to a file, Cadence recommends using the command line >operator. This works for all Conformal commands.

For example, to save the default output of the REPORT GATE command to a file namedgate.out, you would run the following:

report gate > gate.out

You can also use the >> operator to append output text to an existing file.

Note: Although some commands include a -file <filename> type option to save thecommand’s output to a file, Cadence recommends using the command line > operator.



ABSTRACT LOGICABSTract LOGic

[-MODule <name>][-All][-PURE][-AUTO | -NOAUTO][-Golden | -Revised][-ASM | -NOASM][-TEST_VIEW](Setup Mode)

Note: This is a Conformal Custom command. Use this instead of the pre-5.0 EXTRACTcommand.

Performs functional analysis on circuit netlists, which can contain different devices, includingtransistors, gates, and state elements. The analysis abstracts a logically-correct gate and astate primitive model. Use the logic model and compare it to the RTL model for completefunctional verification. You can also write out the logic model and use it duringhigh-performance simulation or fault grading.

Note: If neither the -all nor -module option is specified, Conformal abstracts the currentroot module and any modules that are instantiated under it.

Parameters

-MODule name Abstracts logic information from the specified module and itshierarchy.

-All Abstracts logic information from all cells in the database,including cells that are not used by the current root module.

-Pure Performs basic gate abstraction, which is useful fordebugging.

-AUTO Enables propagation of constants, pin constraints,non-inverted and inverted pin relationships across moduleboundaries. This is the default.

-NOAUTO Does not invoke hierarchical analysis.

-Golden Abstracts logic from the Golden design. This is thedefault.

-Revised Abstracts logic from the Revised design.



Related Commands

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE

ASSIGN PIN DIRECTION

DELETE CLOCK

DELETE MOS DIRECTION

DELETE NET ATTRIBUTE

MOS2BUFIF

READ PATTERN

REPORT ABSTRACT MODEL

REPORT CLOCK

REPORT MOS DIRECTION

-ASM Enables the Advanced State-element Modeling (ASM)algorithm. This helps to analyze loop structure to producebetter modeling of state elements, such as D-Latch, DFF,and bus-keeping I/O logic. This is the default.

-NOASM Disables the Advanced State-element Modeling (ASM)algorithm.

Tip

If there are any unexpected results, you can use thisoption to revert back to the functionality of the 6.2release and earlier.

-TEST_VIEW Performs structurally accurate abstraction. With this option,only limited boolean simplification is done for abstraction. Asa result, the gate-level structure of the original logic ispreserved as much as possible after abstraction.



REPORT NET ATTRIBUTE

REPORT PIN DIRECTION

RESET ABSTRACT MODEL

RESOLVE

SET ABSTRACT MODEL



ADD ALIASADD ALias

<name> <string>(Setup / LEC Mode)

Adds alias names for quick command entry. Assign an alias to long command names andarguments to minimize typing and character entry.

If you add an alias with an alias name that already exists, Conformal accepts the new aliasand returns a warning as shown in the following example:

//Warning: Alias ‘myread’ is already defined, will be replaced by the new definition

For the greatest benefit, create aliases at the start of a Conformal session. Also, add aliasesto an initial command file: .conformal_lec.

The CONFORMAL_RC Environment Variable

Conformal checks for the CONFORMAL_RC environment variable. If this variable is set,Conformal uses the file this variable refers to and does not search for other files.

If the CONFORMAL_RC variable is not set, Conformal continues the search as follows:

■ First, the installation directory:

<install_dir>/share/cfm/lec/.conformal_lec

■ Second, the user’s home directory: ~/.conformal_lec

■ Third, the current working directory: ./.conformal_lec

If one or more of these initial command files exist, Conformal runs them in the order notedabove. This process offers flexibility in the way you choose to use the initial command file. Youcan set up initial command files for any or all of the following purposes:

■ A global initial command file for all users

■ A global initial command file for an individual user

■ An initial command file for a test case

Parameters

name Specifies the name of the alias.



Related Commands

DELETE ALIAS

REPORT ALIAS

string Specifies the command that the alias represents.



ADD BLACK BOXADD BLack Box

[<[-Module | -Instance] [name*…] [-File <filename>]> | -All][ | -Design | -Library]>[-Golden | -Revised | -Both](Setup Mode)

Specifies modules or instances that will be defined as blackboxes. These newly definedblackboxes are classified in the User class of blackboxes. Blackboxes already contained inthe original design are classified in the System class of blackboxes.

Note: The wildcard (*) represents any zero or more characters in blackbox names.

Parameters

-Module Defines this list of module names as blackboxes. This is thedefault.

-Instance Defines this list of instance names as blackboxes.

name ... Defines the list of names of modules or instances.

Note: Wildcard names are only supported for the modulenames. The wildcard (*) represents any zero or more charactersin the blackbox module names.

-File <filename> Specifies the name of the blackbox file. This file must containonly names of modules or instances, it is not a Verilog file. Thenames in the file are added to the [name...] list.

-All Blackboxes all modules except the top module. -All applieswithin the given defaults.

-Design (Used with the -all option only) Blackboxes all modules in thedesign.

If you do not specify either -design or -library, blackboxingapplies to both the library and the design.

-Library (Used with the -all option only) Blackboxes all modules in thelibrary.

If you do not specify either -design or -library, blackboxingapplies to both the library and the design.

-Golden Blackboxing applies to the Golden design only. This is thedefault.



Related Commands

DELETE BLACK BOX

REPORT BLACK BOX

-Revised Blackboxing applies to the Revised design only.

-Both Blackboxing applies to both the Golden and Revised designs.



ADD CLOCKADD CLock

<0 | 1><primary_pin…> [-Module <name>][-Golden | -Revised](Setup Mode)

Defines a clock state where data can change. You can use this command to define:

■ Pre-charge clock states for domino style circuits

■ Stable nets for clock-gating modeling

Caution

When using the ADD CLOCK command with set flatten model-gated_clock, there is an assumption that the ENABLE signal going intothe AND gate of the clock cone is stable. Use with caution.

Parameters

Related Commands

ABSTRACT LOGIC

ADD MOS DIRECTION

ADD NET ATTRIBUTE

0 Specifies that the off-state of the clock pin is 0. This means thatwhen the pin is low, pre-charge occurs.

1 Specifies that the off-state of the clock pin is 1.

primary_pin… Defines the listed primary input pins as clocks in pre-chargedtransistor-MOS.

-Module name Specifies that the defined clock pin is located in this module.

-Golden Specifies that the clock is in the Golden design. This is thedefault.

-Revised Specifies that the clock is in the Revised design.




DELETE CLOCK



READ PATTERN

REPORT CLOCK




RESOLVE

SET ABSTRACT MODEL



ADD COMPARED POINTSADD COmpared Points

<-All |<gate_id ... | instance_pathname* ... | pin_pathname* ...[-FRONTier]

[-Golden | -Revised]>

>(LEC Mode)

Adds mapped points to the compare list. You can add compare points for all mapped points,or for a list of the gate ID numbers, instance paths, or pin paths.

If you add a compare point to the Golden design, the Conformal software also adds itsmapped compare point from the Revised design. Alternately, if you add a compare point tothe Revised design, the software also adds its mapped compare point in the Golden design.

Wildcard: The wildcard (*) represents any zero or more characters in instance or pin paths.

Parameters

-All Adds “all” mapped points, excluding primary inputs, as comparepoints. -All applies within the given defaults.

gate_id Adds the specified gate ID numbers as compare points.

Note: ID numbers can differ from one version of Conformal toanother. Always use the full path in dofiles and any time yourerun a design with a different Conformal version.

instance_pathname* Adds the specified instance paths as compare points.

pin_pathname* Adds the specified pin paths as compare points.

-FRONTier Adds the specified key points and its frontier to the compare list.If no key points are specified, the frontier is computed from theexisting compare points, and added to the compare list. No keypoints are added to the compare list if the frontier contains anyunmapped key points.

-Golden The gate ID numbers, instance paths, or pin paths are in theGolden design. This is the default.

-Revised The gate ID numbers, instance paths, or pin paths are in theRevised design.



Examples

For a set of sample commands that shows this and related commands in context, see theexample for the COMPARE command.

Related Commands

DELETE COMPARED POINTS

REPORT COMPARED POINTS



ADD CUT POINTADD CUt Point

<pathname>[-Net | -Pin][-Golden | -Revised | -Both](Setup Mode)

Adds a cut point to the specified net or pin path. This overrides automatic feedback loop cuts,which Conformal otherwise establishes on entering the LEC mode.

Parameters

Related Commands

DELETE CUT POINT

REPORT CUT POINT

REPORT PATH

pathname Specifies the path that is the cut point of the feedback loop.

-Net Specifies that the path is a net. This is the default.

-Pin Specifies that the path is a pin.

-Golden Applies the cut point to the Golden design. This is the default.

-Revised Applies the cut point to the Revised design.

-Both Applies the cut point to both the Golden and Revised designs.



ADD DYNAMIC CONSTRAINTSADD DYnamic Constraints

<0 | 1><identifier…>[-INStance | -Pin | -Net | -ID][-Golden | -Revised | -Both](LEC Mode)

Adds dynamic constraints for use with the PROVE command. Place constraints on thefollowing:

■ Hierarchical instance paths

■ Hierarchical pin paths

■ Hierarchical net paths

■ Gate identification numbers

These constraints are either a 0-state or 1-state. Use this command as you diagnose anddebug logic cones to help prove gate equivalence.

Parameters

0 Constrains the identifier to a 0-state.

1 Constrains the identifier to a 1-state.

identifier… If you do not specify one of the following options, Conformalautomatically determines if the identifier is a number or a path.In the case of a number, Conformal uses the -id option;otherwise, Conformal searches for the gate with the-instance, -pin, or -net option; in this respective order.

-INStance Hierarchical instance pathThis is the default.

-Pin Pin path, which is the module instance nameconcatenated with the pin name.

-Net Net path, which is the instance nameconcatenated with the net name.



Examples


Related Commands

DELETE DYNAMIC CONSTRAINTS

PROVE

REPORT DYNAMIC CONSTRAINTS

-ID Identification number (ID) of a gate.

The identification number is an integerassigned automatically by Conformal.

Note: ID numbers can differ from one versionof Conformal to another. Always use the fullpath in dofiles and any time you rerun adesign with a different Conformal version.

-Golden Adds the dynamic constraints to the Golden design only. Thisis the default.

-Revised Adds the dynamic constraints to the Revised design only.

-Both Adds the dynamic constraints to both the Golden and Reviseddesigns.



ADD ECO CELLADD ECo Cell

[-DEFfile <filename>][-FReedcell][-SParecell <cell_name*>](Setup Mode)

Adds the spare cells or freed cells as the available cells for the MAP ECO PATCH command.

Parameters

Related Commands

DELETE ECO CELL

MAP ECO PATCH

REPORT ECO CELL

-DEFfile <filename> Specifies the DEF file name. If specified, the spare cell will besearched in DEF file. Otherwise, the spare cell will be searchedin current hierarchy.

-FReedcell Specifies that freed cells will be used for mapping.

-SParecell Specifies the spare cells to be added.



ADD ECO LIBRARYADD ECo Library

[<library_name> | -ALL][-Golden | -Revised](Setup Mode)

Adds the library to the library list used by the by the MAP ECO PATCH command.

Parameters

Related Commands

MAP ECO PATCH

<library_name> Specifies the name of the library.

-ALL Adds all the libraries in Golden or Revised.

-Golden Specifies that the library is in the Golden library. This is thedefault.

-Revised Specifies that the library is in the Revised library.



ADD ECO PATCHADD ECo PAtch

<module_under_ECO_name><patch_module_name>[-PATH <hierarchy-path>](Setup Mode)

Specifies the ECO patch and adds the patch module to be mapped by the MAP ECO PATCHcommand.

Parameters

Examples

In the following command sequence, the ECOs defined in the G1_eco and G2_eco patchmodules will be applied to the design and mapped to the spare cells and freed cells, and willwrite out the new mapped patch modules to the map.v file.

add eco patch G1 G1_eco -path /U1/U1

add eco patch G2 G2_eco -path /U1/U2

add eco library typical

add eco cell -def layout.def -freed -spare *spare*

map eco patch map.v -replace

Related Commands

ADD ECO CELL

ADD ECO LIBRARY

<module_under_ECO_name>

Specifies the name of the module being changed for ECO.

<patch_module_name> Specifies the name of the patch module that contains the ECOchanges.

[-PATH <hierarchy-path>]

Specifies the hierarchy path to the module under ECO. This isfor the ADD ECO CELL command to locate the freed celllocations in DEF file.



DELETE ECO PATCH

MAP ECO PATCH

REPORT ECO PATCH



ADD ECO PINADD ECo PIn

<module_name><pin_name> | <bus_name <size>> ...[-INput | -OUTput | -IO][-FORce][-Golden | -Revised](Setup Mode)

Adds a pin to a module. If the Revised module has extra ports, you can use this command toadd new pins to the Golden module. Cadence recommends that you add the extra pins beforerunning the WRITE HIER_COMPARE DOFILE command.

Parameters

Examples

■ The following command adds wr_req input port and data[15:0] input bus to modulemod_A

add eco pin mod_A wr_req data[15:0] -input -golden

■ This example shows how the command’s -force option affects the following design:

module top(x,y);

<module_name> Specifies the name of the module.

<pin_name> Specifies the name of the pin(s).

<bus_name <size>> Specifies the name of the bus(es), where <size> is[msb:lsb], for example, [16:0].

You must include the braces in the command. See theExamples section.

-INput Specifies that the pin is an input pin. This is the default.

-OUTput Specifies that the pin is a output pin.

-IO Specifies that the pin is an input/output pin.

-FORce Renames the signal if it conflicts with the port name. See theExamples section.

-Golden Applies to the Golden design. This is the default.

-Revised Applies to the Revised design.



wire z;

endmodule

❑ The following command will error out because there is a conflict between the net zand the new port z:

add eco pin -output top z

❑ The following command will not error out and net z will be renamed z_1:

add eco pin -output top z -FORce

Related Commands

ANALYZE ECO

DELETE ECO PIN

WRITE HIER_COMPARE DOFILE



ADD IGNORE RTLCHECKADD IGnore Rtlcheck

<-All | -Module <name*…>>(Setup Mode)

Ignores RTL (HDL) rule checking for all or specified modules. Run this command before theREAD LIBRARY and READ DESIGN commands.

Refer to the Encounter Conformal Equivalence Checking User Guide for additionalinformation about specific rules.

Tip

When using the -module option, ensure that you have entered the module namecorrectly. If you enter a nonexistent module name, Conformal conducts the checksand issues messages as usual.

Note: If you enter multiple IGNORE RTLCHECK commands, later commands replaceprevious commands. In the following example, Conformal ultimately enables RTL rulechecking for all modules, including module abc.

add ignore rtlcheck -module abc

delete ignore rtlcheck -all

Wildcard: The wildcard (*) represent any zero or more characters in module names.

Parameters

Related Commands

DELETE IGNORE RTLCHECK

REPORT RULE CHECK

-All Ignores RTL rule checking for all modules.

-Module name*… Ignores RTL rule checking for the specified modules.



ADD IGNORED INPUTSADD IGnored Inputs

<primary_pin*…>[-ROot | -Module <name*> | -All][-Golden | -REvised | -Both](Setup Mode)

Specifies which input pins Conformal ignores during comparison. You can use this commandwhen the input pins are part of a blackboxed module.

Note: Specified pins must be boundary module pins. Although boundary module pins aregenerally not compared points, they are compared points when the corresponding modulebecomes a blackbox.

For example, when Conformal compares two blackboxes and one of them has extra inputpins, such as scan in and scan enable pins, use this command to tell Conformal to ignorethese extra input pins during comparison.

Wildcard: The wildcard (*) represent any zero or more characters in ignored inputs andmodule names.

Parameters

primary_pin*… Ignores this list of primary input pins (associated with the rootmodule or the specified submodule).

-ROot Ignores the specified input pins in the root module. This is thedefault.

-Module name* Ignores the specified input pins in this module.

-All Ignores the specified input pins in “all” the modules, includingthe root module. -All applies within the given defaults.

-Golden Ignores the specified input pins in the Golden design. This isthe default.

-REvised Ignores the specified input pins in the Revised design.

-Both Ignores the specified input pins in both the Golden and Reviseddesigns.



Related Commands

DELETE IGNORED INPUTS

REPORT IGNORED INPUTS



ADD IGNORED OUTPUTSADD IGnored Outputs

<primary_pin*…>[-Module <name*> |-All][-Golden |-REvised |-Both][-EQuivalences](Setup Mode)

Specifies which output pins Conformal ignores during comparison.

Note: Specified pins are boundary module pins. For example, when Conformal comparestwo modules and one of them has extra outputs, such as scan out pins, use this command totell Conformal to ignore these extra output pins during comparison.

Wildcard: The wildcard (*) represents any zero or more characters in ignored outputs andmodule names.

Parameters

Related Commands


primary_pin*… Ignores this list of primary output pins (associated with the rootmodule or the specified submodule).

-Module name* Ignores the output pins in the specified module. The default isthe root module.

-All Ignores the specified output pins in “all” the modules, includingthe root module. -All applies within the given defaults.

-Golden Ignores the specified output pins in the Golden design. This isthe default.

-REvised Ignores the specified output pins in the Revised design.

-Both Ignores the specified output pins in both the Golden andRevised designs.

-EQuivalences Ignores the specified output pins and their equivalences. Theequivalences of a pin must be specified by the ADD OUTPUTEQUIVALENCES command prior to using this option.Equivalences created after using this option will not be ignored.



DELETE IGNORED OUTPUTS

REPORT IGNORED OUTPUTS



ADD INSTANCE ATTRIBUTEADD INstance Attribute

<module_name> <instance_name>[<WEAK> | <DELETE>][-Golden | -Revised](Setup Mode)

Specifies how to treat an attribute for a gate or transistor primitive. Attributes can either beWEAK or deleted from the database for the purposes of a complete abstraction andcomparison. However, newer abstraction capabilities can make the WEAK featureunnecessary.

Parameters

module_name Applies the instance attribute to the specified module, whichcontains the instance.

instance_name Applies the instance attribute to the specified instance.

WEAK Note: This option applies to Conformal Custom.

Specifies drive strength of WEAK on an attribute.

In the case of multiple drivers,

■ First, the state of the node is determined by devices that arenot WEAK (STRONG).

■ Then, if there are none, or if all of the STRONG devices aredisabled, the WEAK devices impact the net’s function.

This option affects extraction behavior and loop handling.

DELETE Removes the specified device from the circuit.

Note: This option applies to Conformal Custom.

Tip

The preferred method is to use the REMOVE command.

-Golden Applies the instance attribute to the Golden design. This is thedefault.

-Revised Applies the instance attribute to the Revised design.



Related Commands

DELETE INSTANCE ATTRIBUTE

REMOVE

REPORT INSTANCE ATTRIBUTE



ADD INSTANCE CONSTRAINTSADD INstance Constraints

<0 | 1><instance_pathname*… | name… -Module name*>[-REPlace][-Golden |-Revised |-Both](Setup Mode)

Places constraints on specified instance paths in either the Golden or Revised design. Youcan only place 0-state or 1-state constraints on the outputs of instances. You can only applyinstance constraints to D flip-flops and D-latches inside the specified instance paths.

Wildcard: The wildcard (*) represents any zero or more characters in instance and modulenames.

Parameters

Examplesadd instance constraints 0 /U1/U2/U3 -revised

add instance constraints 1 /U6/U5 /U7/U8 -golden

add instance constraints 0 /U6/U5 /U7/U8 -replace -golden

0 Constrains the specified instance paths to a 0-state.

1 Constrains the specified instance paths to a 1-state

instance_pathname*… Places the constraints on these instance paths.

Note: The instances are either DFFs or D-latches.

name… -Module name*

Applies the constraint to the specified module(s).

-REPlace Changes the previously specified instance constraint.

-Golden Applies the instance constraints to the Golden design. This isthe default.

-Revised Applies the instance constraints to the Revised design.

-Both Applies the instance constraints to both the Golden andRevised designs.



Related Commands

DELETE INSTANCE CONSTRAINTS

REPORT INSTANCE CONSTRAINTS



ADD INSTANCE EQUIVALENCESADD INstance Equivalences

<instance_pathname*…>[-Invert <instance_pathname*…>][-Golden | -Revised | -Both](Setup Mode)

Defines D-latches and D flip-flops as equivalent or inverted equivalences. This command isuseful in mapping and its output is verified during the comparison. Use this command whenyou have one state element in a design that corresponds to two or more state elements inanother design.

Note: Only apply instance equivalences to D flip-flops and D-latches.

Effects on Comparison

This command affects comparisons when you use add compared points -all. In thatsituation, Conformal merges the instances specified with the ADD INSTANCEEQUIVALENCES command and then verifies them at the end of the comparison.

Wildcard: The wildcard (*) represents any zero or more characters in instance names.

Parameters

instance_pathname*… Defines the group of instances that are equivalent. The firstinstance is the representative instance. The following instancesare equivalent to the representative instance.


The wildcard (*) is supported.

-Invert instance_pathname*…

Defines a group of instances that is an inverted equivalence ofthe group that is equivalent.


-Golden Applies instance equivalences to the Golden design. This isthe default.

-Revised Applies instance equivalences to the Revised design.



Related Commands

ADD COMPARED POINTS

DELETE INSTANCE EQUIVALENCES

REPORT INSTANCE EQUIVALENCES

SET FLATTEN MODEL

-Both Applies instance equivalences to both the Golden and Reviseddesigns.



ADD LOWPOWER CELLSADD LOwpower Cells

<module_name*>[-isolation | -level_shifter| [-retention -attribute <attribute_name>] ]

[-Both | -Golden| -Revised](Setup Mode)

Note: This is a Conformal Low Power command.

Defines the low power attribute for specified modules.

Parameters

Examples

■ The following command assigns cell fdf1a1 as a state retention cell with a CLK_LOWattribute:

add lowpower cells fdf1a1 -retention -attribute CLK_LOW -revised

module_name Applies the low power cell attribute to the specifiedmodule(s). Wildcards are accepted.

-isolation Specifies the module as isolation cell. This is equivalent tothe attribute is_isolation_cell : true in the libertylibrary.

-level_shifter Specifies the module as level shifter cell. This is equivalentto the attribute is_level_shifter : true in the libertylibrary.

-retention -attribute <attribute_name>

Specifies the module as a state retention cell with itsassociated power gate cell attribute. This is equivalent to theattribute power_gating_cell : ATTRIBUTE in theliberty library.

-Both Applies the low power cell attribute to both the Golden andRevised designs. This is the default.

-Golden Applies the low power cell attribute to the Golden design.

-Revised Applies the low power cell attribute to the Revised design.



■ The following command assigns cell and2b1 as an isolation cell:

add lowpower cells and2b1 -iso -revised

Related Commands

CHECK LOWPOWER CELLS

DELETE LOWPOWER CELLS

REPORT LOWPOWER CELLS

REPORT LOWPOWER DATA

SET LOWPOWER OPTION



ADD MAPPED POINTSADD MApped Points

<<<gate_id | instance_pathname | pin_pathname><gate_id | instance_pathname | pin_pathname>>|<-NET <net> <net>>|<-RULE <pattern> <substitution>>>

[-INSTance | -NET][-OUTput_pin <Golden_pin> <Revised_pin>]…[-INPut_pin <Golden_pin> <Revised_pin>]…[-GOLden | -REVised][-NOINVert | -INVert](LEC Mode)

When Conformal moves from Setup to LEC system mode, it automatically maps key pointsand places them in the System class of mapped points. If any additional mapped points arenecessary, use this command, and Conformal will place them in the User class of mappedpoints.

Note: If you attempt to add mapped points that were already mapped, Conformal returns awarning message.

In the syntax shown below, the first gate_id, instance_pathname, or pin_pathnamerefers to the Golden design; the second argument refers to the Revised design.

The -invert option makes one mapped point inverted with respect to the other mappedpoint. The (-) sign represents an inverted-mapped point. The (+) sign represents anon-inverted mapped point.

Parameters

gate_id Adds this gate (identified by number) as a mapped point.


instance_pathname Adds this instance path as a mapped point.

pin_pathname Adds this pin path as a mapped point.

-NET net net Uses the specified Golden and Revised net names to map keypoints together.

-RULE pattern substitution



Examples

In the following two commands, A1 is the instance path of a blackbox:

add mapped points A1 A1 -input_pin in1[0] inA[0] -input_pin in1[1] inA[1]

add mapped points A1 A1 -output_pin out1[0] outA[0] -output_pin out1[1] outA[1]

Related Commands

DELETE MAPPED POINTS

Uses the instance or net renaming rule with the specifiedoriginal pattern and substitution pattern to map key pointstogether.

-INSTance Specifies that the rule is an instance renaming rule. This is thedefault.

-NET Specifies that the rule is a net renaming rule.

-OUTput_pin Golden_pin Revised_pin…

Maps the specified Golden and Revised blackboxed outputpins. Multiples are permitted. However, you must list Goldenand Revised pins in pairs and you must precede each pair withthe -output_pin option. (See the example below. For eachpair that is listed, the first output pin is from the Golden designand the second output pin is from the Revised design.)

-INPut_pin Golden_pin Revised_pin…

Maps the specified Golden and Revised blackboxed input pins.Multiples are permitted. However, you must list Golden andRevised pins in pairs and you must precede each pair with the-input_pin option. (See the example below. For each pairthat is listed, the first input pin is from the Golden design andthe second input pin is from the Revised design.)

-GOLden Applies this rule pattern substitution to the Golden design. Thisis the default.

-REVised Applies this rule pattern substitution to the Revised design.

-NOINVert Does not invert the two mapped points with respect to oneanother. This is the default.

-INVert Inverts the two mapped points with respect to one another.



INVERT MAPPED POINTS

MAP KEY POINTS

READ MAPPED POINTS

REPORT MAPPED POINTS

REPORT UNMAPPED POINTS

SET MAPPING METHOD

SET NAMING RULE



ADD MODULE ATTRIBUTEADD MOdule Attribute

<module_name*…><-PIPELINE_Retime [-DFF2Buffer]| -COMPARE_Effort < Low | Medium | High | AUto | None>| -CPU_Limit # >[-Golden |-Revised]

[-ECO_module][-HIER_Compare <hier_compare_script>](Setup Mode)

Defines the attributes for specified modules.

Parameters

module_name*… Applies the attribute to the specified modules. The wildcard (*)is supported.

-PIPELINE_Retime Checks the specified modules for pipeline retiming (andremodel if pipeline retiming is detected).

This option requires Conformal to check the module andremodel it if the Golden and Revised designs havepipeline-retiming.

-DFF2Buffer Changes registers to buffers.This option lets you comparemodels with no registers to those with pipeline registersinserted.

-COMPARE_Effort Assigns a specified comparison effort level to the module. Thisoption is generally applied to hierarchical comparisons wheresome modules need a higher compare effort than others.

For advanced pipeline retiming, see ANALYZE RETIMING.

Low Applies minimal effort to equivalencychecking for the specified module. This isthe default.

Medium Applies greater effort to equivalencychecking for the specified module.

High Applies the maximum effort to equivalencychecking for the specified module.



Example

In the following command sequence, the hierarchical dofile script hier.do that is generatedwith the ’write hier_compare dofile’ command contains the commands ‘addpartition points -all,’ ‘set compare effort high,’ ‘add compared points-all,’ and ‘compare’ for module modA, instead of the default ‘add compared points-all’ and ‘compare’ command sequence:

add module attribute modA -hier_compare "add partition points -all; set compareeffort high; add compared points -all; compare"

write hier_compare dofile hier.do -constraints

Related Commands

ANALYZE RETIMING

DELETE MODULE ATTRIBUTE

REPORT MODULE ATTRIBUTE


AUto Starts with low effort and automaticallyincreases the compare effort when abortpoints are in the specified module.

None Applies no compare effort to equivalencychecking for the specified module.

-CPU_Limit # Specifies a number of seconds for each module duringhierarchical compare.This option decreases the amount of timeConformal spends comparing a particular module.

-Golden Specifies that the module attribute applies to the Goldendesign. This is the default.

-Revised Specifies that the module attribute applies to the Reviseddesign.

-HIER_Compare <hier_compare_script>

For the specified module, replaces the default ’add comparedpoints -all’ and ’compare’ commands in the hierarchicalscript generated using the ’write hier_compare dofile’command with the specified <hier_compare_script>.



ADD MOS DIRECTIONADD MOs Direction

<module_name instance_name net_name | <-Module <name> | -All>[-FROM_Source_pin | -FROM_Drain_pin]>

>[-Golden | -Revised](Setup Mode)

Note: This is a Conformal Custom command.

Adds unidirection to bidirectional MOS devices. This can change a tranif0 into a PMOS,or change a tranif1 to an NMOS.

Use the REPORT MOS DIRECTION command to display the list of all unidirectional andbidirectional transistor-MOS instances and their source and drain ports.

Use this command to resolve bidirectional transistor-MOS instances, when the ABSTRACTcommand is not able to fully resolve all bidirectional transistor-MOS instances not supportedfor comparison.

Parameters

module_name Adds unidirection to the specified module.

instance_name Adds unidirection to the specified instance.

net_name Specifies the source net name, which is the input pin of theMOS device.

-Module name Adds unidirection to all bidirectional MOS devices in thismodule.

-All Adds unidirection to all bidirectional MOS devices. -Allapplies within the given defaults.

-FROM_Source_pin Specifies that all source pins are inputs. This is the default.

-FROM_Drain_pin Specifies that all drain pins are inputs.

-Golden Applies the MOS direction to the Golden design. This is thedefault.

-Revised Applies the MOS direction to the Revised design.



Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD NET ATTRIBUTE


DELETE CLOCK



READ PATTERN

REPORT CLOCK




RESOLVE



ADD NET ATTRIBUTEADD NEt Attribute

<VDD | GND | CLOCK0 | CLOCK1 | DYNSTate><net_name>[-Module <name>][-Golden | -Revised](Setup Mode)


Defines pre-charge nets; power and ground; or with DYNSTate, defines a dynamic latchstate.

If you do not use the -module option with this command, Conformal applies the attribute toevery module on the specified side (Golden or Revised).

Parameters

VDD Specifies that the net has a VDD attribute.

GND Specifies that the net has a GND attribute.

CLOCK0 Specifies that the net has a Clock-0 attribute. This optionplaces an off-state of 0 at the specified net.

The off-state is defined as the value at which the clock portis inactive.

CLOCK1 Specifies that the net has a Clock-1 attribute. This optionplaces an off-state of 1 at the specified net.

The off-state is defined as the value at which the clock portis inactive.

DYNSTate Specifies that the net is a dynamic state point, whichConformal Custom will abstract as a latch.

net_name Specifies the transistor-MOS net name.

-Module name Specifies that the specified module contains thetransistor-MOS. If you do not use the -module option withthis command, Conformal applies the attribute to everymodule on the specified side (Golden or Revised).

-Golden Applies the net attribute to the Golden design. This is thedefault.



Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION


DELETE CLOCK



READ PATTERN

REPORT CLOCK




RESOLVE

SET ABSTRACT MODEL

-Revised Applies the net attribute to the Revised design.



ADD NET CONSTRAINTSADD NEt Constraints

<ONE_Hot | ONE_Cold | ZERO_ONE_Hot | ZERO_ONE_Cold><net_pathname…>[-Golden | -Revised | -Both](Setup Mode)

Adds one-hot or one-cold constraints on specified net paths. The one-hot constraint lets onlyone net be at a 1-state and the remaining nets be at a 0-state. The one-cold constraint letsonly one net be at a 0-state and the remaining nets be at a 1-state.

Parameters

Related Commands

DELETE NET CONSTRAINTS

REPORT NET CONSTRAINTS

ONE_Hot Places one-hot constraints on the specified net paths.

ONE_Cold Places one-cold constraints on the specified net paths.

ZERO_ONE_Hot Places zero-one-hot constraints on the specified net paths.

ZERO_ONE_Cold Places zero-one-cold constraints on the specified net paths.

net_pathname… Places constraints on the listed net paths.

-Golden Applies the net constraints to the Golden design. This is thedefault.

-Revised Applies the net constraints to the Revised design.

-Both Applies the net constraints to both the Golden and Reviseddesigns.



ADD NOBLACK BOXADD NOblack Box

<module_name*… | All>[-Golden | -Revised | -Both](Setup Mode)

Specifies the modules that are excluded from the hierarchical dofile script generation.(Execute it before the WRITE HIER_COMPARE DOFILE command.)

Wildcard: The wildcard (*) represents any zero or more characters in module names.

Parameters

Related Commands

DELETE NOBLACK BOX

REPORT NOBLACK BOX


module_name*… Does not include the listed modules in the hierarchical dofilescript generation.


All Does not include any instances or modules in the hierarchicaldofile script generation except the top module.

“All” applies within the given defaults.

-Golden Does not include the specified modules in the Golden design.This is the default.

-Revised Does not include the specified modules in the Revised design.

-Both Does not include the specified modules in either the Golden orRevised designs.



ADD NOTRANSLATE FILEPATHNAMESADD NOtranslate Filepathnames

<filepath_names*…>[ | -Library | -Design][-Both | -Golden | -Revised](Setup Mode)

Specifies library or design files, where modules defined in these files will not be translatedwhen running the READ LIBRARY or READ DESIGN command. These modules willautomatically become blackboxes.

This command is applied during initial parsing, so name matching applies only to originalmodule names. For parameterized or VHDL generic modules whose names are determinedand applied by the Conformal software after parsing and preprocessing, you must use theADD BLACK BOX command.

The following are examples of modules that should not be compiled:

■ RAM models

■ Analog blocks

■ Modules that contain non synthesizable RTL constructs


Parameters

filepath_names*… Specifies the filepath name, which can be directory namesand Verilog filenames.The wildcard (*) and search path issupported.

-Library Does not translate the modules in the specified library. If youdo not specify -library or -design, Conformal appliesthis command to both the library and design modules.

-Design Does not translate the modules in the specified design. If youdo not specify -library or -design, Conformal appliesthis command to both the library and design modules.

-Both Does not translate the specified modules in either the Goldenor Revised libraries and designs. This is the default.

-Golden Does not translate the specified modules in the Golden libraryor design.



Related Commands

ADD NOTRANSLATE MODULES

ADD SEARCH PATH

DELETE NOTRANSLATE FILEPATHNAMES

DELETE NOTRANSLATE MODULES

REPORT NOTRANSLATE FILEPATHNAMES

REPORT NOTRANSLATE MODULES

-Revised Does not translate the specified modules in the Revisedlibrary or design.



ADD NOTRANSLATE LINESADD NOtranslated Lines

<filename><[start:end | line] ... >(Setup Mode)

Specifies lines to skip in a Verilog or VHDL file. This has the same effect as commenting outthe lines in the file. With this command, you can instruct the Conformal software to skipcertain lines in the design file without having to modify the file.

Parameters

Example

The following commands skip lines 6 through 8 and line 17 in the foo.v file when reading inthe design:

add notranslated lines foo.v 6:8 17

read dessign foo.v

As a result, lines 6, 7, 8 and 17 are skipped in the foo.v file:

(1) module test(clk, rst, set, d, z);(2) input clk, set, rst, d;(3) output z;(4) reg z;(5)(6) garbage 1...........(7) initial begin end(8) garbage 2...........(9)(10) always @(negedge clk or negedge set or negedge rst) begin(11) if (!rst) z <= 1’b0;(12) else if (!set) z <= 1’b1;(13) else z <= d;(14) end(15)(17) garbage 3....(18)(19)endmodule

filename Specifies the Verilog or VHDL file.

start:end Specifies the a line number range to skip. For example, 6:8would skip lines 6, 7, and 8.

line Specifies a line number to skip.



Related Commands

READ DESIGN

READ LIBRARY



ADD NOTRANSLATE MODULESADD NOtranslate Modules

<module_name*…>[ | -Library | -Design][-Both | -Golden | -Revised](Setup Mode)

Specifies library or design modules that are parsed, but will not be translated when runningthe READ LIBRARY or READ DESIGN command. These modules automatically becomeblackboxes.

Note: The ADD NOTRANSLATE MODULES command is applied during initial parsing, soname matching applies only to original module names. For parameterized or VHDL genericmodules whose names are determined and applied by Conformal after parsing andpreprocessing, you must use the ADD BLACK BOX command.

Examples of modules that should not be compiled include:

■ RAM models

■ Analog blocks

■ Modules that contain non-synthesizable RTL constructs


Parameters

module_name*… Does not compile the listed library or design modules. Thewildcard (*) is supported.

-Library Does not compile the specified library modules. If you do notspecify -library or -design, Conformal applies thiscommand to both the library and design modules.

-Design Does not compile the specified design modules. If you do notspecify -library or -design, Conformal applies thiscommand to both the library and design modules.

-Both Does not compile the specified modules in either the Golden orRevised libraries and designs. This is the default.

-Golden Does not compile the specified modules in the Golden library ordesign.



Related Commands

ADD BLACK BOX


READ DESIGN

READ LIBRARY


-Revised Does not compile the specified modules in the Revised libraryor design.



ADD OUTPUT EQUIVALENCESADD OUtput Equivalences

<primary_pin primary_pin*…>[-Invert <primary_pin*…>][-ROot | -Module < name*> | -All][-Golden | -Revised | -Both](Setup Mode)

Specifies output pin equivalences or inverted pin equivalences on output boundary modulepins. Conformal uses the equivalences when the parent module is being compared and thesubsequent module is a blackbox. The first specified output pin is the representative pin. Theremaining primary output pins refer to the representative pin in that added equivalence group.

Effects on Comparison

This command affects comparisons when you use add compared points -all. In thatsituation, Conformal merges the output pins specified with the ADD OUTPUT EQUIVALENCEScommand and then verifies them at the end of the comparison.

Wildcard: The wildcard (*) represents any zero or more characters in output boundarymodule pin and module names.

Parameters

primary_pin primary_pin*…

Specifies a list of output boundary module pins that areequivalent. The first output pin is classified as therepresentative pin.

The wildcard (*) is supported for the second pin.

-Invert primary_pin*…

Specifies a list of output boundary module pins that haveinverted equivalences with respect to the representative pin.These inverted output pins are identified as (-) with the REPORTOUTPUT EQUIVALENCES command.


-ROot Adds output equivalences to the root module output pins. Thisis the default.

-Module name* Adds output equivalences to the specified module output pins.



Related Commands

ADD COMPARED POINTS



-All Adds output equivalences to “all” modules. -All applies withinthe given defaults.

-Golden Adds output equivalences to the Golden design. This is thedefault.

-Revised Adds output equivalences to the Revised design.

-Both Adds output equivalences to both the Golden and Reviseddesigns.



ADD OUTPUT STUCK_ATADD OUtput Stuck_at

<0 | 1><primary_pin*…>[-ROot | -Module <name*> | -All][-Golden | -Revised | -Both](Setup Mode)

Places values at the output boundary module pins. This value has no effect on the currentspecified module comparison. However, Conformal uses the value when it compares theparent (or higher) module.

Note: This command is limited to blackboxes. For a flat run, if the module is not blackboxed,all applied constraints will not take effect.

Wildcard: The wildcard (*) represents any zero or more characters in boundary module pinand module names.

Parameters

0 Specifies that the output stuck_at value is 0.

1 Specifies that the output stuck_at value is 1.

primary_pin*… Applies the stuck_at value to this list of output boundarymodule pins. The wildcard (*) is supported.

-ROot Applies the output stuck_at value to the root moduleboundary pin. This is the default.

-Module name* Applies the output stuck_at value to the specified moduleboundary pin. The wildcard (*) is supported.

-All Applies the output stuck_at value to all output boundarymodule pins.

-Golden Applies the output stuck_at value to the Golden design. Thisis the default.

-Revised Applies the output stuck_at value to the Revised design.

-Both Applies the output stuck_at value to both the Golden andRevised designs.



Related Commands

DELETE OUTPUT STUCK_AT

REPORT OUTPUT STUCK_AT



ADD PARTITION KEY_POINTADD PArtition Key_point

[-Pin |-Instance]< name… [-Golden |-Revised]]

|gname0 rname0 gname1 rname1… -Pair>[-ALL_pattern | -ONE_Hot | -ONE_Cold](Setup Mode)

Specifies the pin or instance names that partition the design into different compare iterationswhen the normal comparison process cannot finish. Execute this command before the WRITEPARTITION DOFILE command.

■ The -all_pattern option creates all possible binary combinations for n key pointsspecified.

■ The -one_hot option creates all combinations where only one key point has a 1-stateand the rest have a 0-state.

■ The -one_cold option creates combinations where only one key point has a 0-stateand the rest have a 1-state.

Important

A maximum of 14 partition points can be added. If you try to add more than 14partition points, then only the first 14 will be taken.

Parameters

-Pin Specifies that the partition key point names are pin names.This is the default.

-Instance Specifies that the partition key point names are instancenames.

name… Specifies a list of partition pin or instance key point names.

-Golden Specifies that the partition key points are in the Golden design.This is the default.

-Revised Specifies that the partition key points are in the Revised design.

gname0 rname0 gname1 rname1… -Pair

Individually specifies that the Golden and Revised partition keypoint names when the names differ between the Golden andRevised designs.



Related Commands

DELETE PARTITION KEY_POINT

REPORT PARTITION KEY_POINT

WRITE PARTITION DOFILE

-ALL_pattern Applies all possible combinations of constraints to the partitionkey point names. This is the default.

-ONE_Hot Applies a one-hot constraint to the partition key point names.

-ONE_Cold Applies a one-cold constraint to the partition key point names.



ADD PARTITION POINTSADD PARtition Points

< [-Net | -Pin | -GAte_instance | -ID] identifier... [-Pair]| -MODule <module_name* ...>| -INstance <instance_pathname* ...>| -Datapath | -OUTPUT_TRIstate| -ALL

>[-OUTPUT_port | -INPUT_port | -INTRA_operator][-NAME][-ABORT_cone [compare point ...] ][-Cut | -NOCut][-Golden | -Revised][-EFFORT <Low | Medium | High>][-Verbose](LEC Mode)

Note: This is a Conformal Ultra command.

Adds partition (cut) points to the design. If a location in one design is specified, the Conformalsoftware will attempt to find the corresponding point in the other design. If found, it adds a cutpoint to both the Golden and Revised designs. These cut points are automatically mapped.This command automatically handles inverted points.

In the cases where the added cut points are not equivalent, you will need to diagnose them.If the non-equivalency is caused by the cut point, then you will need to delete that pair of cutpoints with the DELETE PARTITION POINTS command.

After adding the partition points, you would normally run the ADD COMPARED POINTS -allcommand to add the cut points to the compare list.

Note: If a cut point has already been added to a location, a second cut point cannot be addedto the same location. If a specified point has more than one corresponding point in the design,the software will not add a cut point.

Caution

Adding cut points in LEC mode causes flattened netlists to change. As aresult, all the gate IDs are subjected to change. Adding cut points doesnot affect the existing compare points list; however, all the compare datais invalidated after adding cut points.



Parameters

-Net Specifies that the identifier is a net pathname.

-Pin Specifies that the identifier is a pin pathname.

-GAte_instance Specifies that the identifier is a gate-instance pathname.

-ID Specifies that the identifier is a gate identification number.This number is an integer assigned automatically byConformal.

ID numbers can differ from one version of Conformal toanother. Always use the full path in dofiles and any time yourerun a design with a different Conformal version.

identifier Specifies the identifier for adding the partition point.

If you do not specify -Net, -Pin, -GAte_instance, or-ID, the Conformal software automatically determines if theidentifier is a gate-identification number, pin pathname, netpathname, or a gate-instance pathname.

-Pair Allows specification of multiple pairs of identifiers, where thefirst identifier in each pair refers to the Golden design andthe second identifier in each pair refers to the Reviseddesign.

-MODule <module_name* ...>

Adds partition points to all the instances of the specifiedmodule(s).

-INstance <instance_pathname* ...>

Specifies the module instance pathname. By default, thepartition points are all the output pins of the specifiedinstance.

Note: If an instance is removed during the Conformalflattening and modeling process, you cannot add partitionpoints to the instance.

-Datapath Adds partition points to all module instances containingdatapath operators. The datapath operator is the multiplier(including the merged operator) in the Golden design.

By default, the partition points are all the output pins of thedatapath operator(s).



-OUTPUT_TRIstate Specifies the partition points as the tri-state buffer at theprimary output.

-ALL Adds partition points to all possible locations. This is usefulwhen resolving aborts.

-OUTPUT_port Specifies the partition points as all the output pins of themodule instance or datapath operator. This is the default.

-INPUT_port Specifies the partition points as all the input pins of themodule instance or datapath operator.

-INTRA_operator Specifies the partition points as the gates inside thedatapath operator.

-NAME Adds partition points around instances using a name-basedalgorithm. This is faster than the default algorithm whichadds partition points based on function.

To perform a flat run with hierarchical partitioning, addpartition points to all module instances using the followingcommand:

add partition points -instance * -name -input -output

To get better datapath quality, add partition points to allmodule instances containing datapath operators using thefollowing command:

add partition points -datapath -name -input -output

-ABORT_cone [compare point ...]

Adds the specified partition points only in the fan-in logiccone of the specified compare points. If no compare point isspecified, by default, the partition points are added in thefanin logic cone of all the compare points with abort orunknown results.

Note: You must add compare points first to use this option.

-CUT Generates the cut gates in the flattened netlists for thefeasible partition points in Golden and Revised design. Thisis the default.

-NOCUT Does not generate any cut gates in flattened netlists.

-Golden Specifies that the partition points are from the Goldendesign. This is the default.



Examples

■ The following commands specify partition points in Golden and Revised design by pinpathnames:

add partition points -pin i0_gold/sum[17] i0_rev/z[17] -pair

add compared points -all

■ The following commands specify the partition points in the Golden design. Thecommands will automatically find the corresponding gates in the Revised design, and iffound, will physically add the cut gate pair in the flattened netlist.

add partition points -pin i0/sum[17] i0/sum[16] -golden


■ The following commands specify the partition points from the output pins of multiplieroperators in the Golden design. The commands will automatically find thecorrespondence gates in the Revised design, and add partition point pairs as cut gatesin the flattened netlists.

add partition points -datapath


■ The following command specifies an instance of datapath operator in the Golden designand add some gates inside the operator as partition points:

add partition points -instance i0 -intra_operator

■ The following command specifies all the datapath operators in the Golden design andadd some gates inside the operators as partition points:

add partition points -datapath -intra_operator

-Revised Specifies that the partition points are from the Reviseddesign.

-EFFORT <Low | Medium | High>

Specifies the effort level for adding partition points.Increasing the effort level from Low to High will improve thequality of partition points being added, but will result inincreased time.

The default effort level is Medium.

-Verbose Reports the partition points with correspondences in theother design.



■ The following command adds partition points for all the tri-state buffers at the primaryoutputs:

add partition points -output_tristate

■ The following command adds partition points to all instances of the DW_ module:

add partition points -module DW_*

■ The following commands add partition points at all the possible locations in the fan-inlogic cone of the compare points with abort or unknown compare results:

add partition points -all -abort_cone


Related Commands

ADD COMPARED POINTS

DELETE PARTITION POINTS

REPORT PARTITION POINTS



ADD PIN CONSTRAINTSADD PIn Constraints

<0 | 1 | ONE_Hot | ONE_Cold | ZERO_ONE_Hot | ZERO_ONE_Cold><primary_pin*…>[-REPlace] [-ROot | -Module <name*> | -All][-Golden | -Revised | -Both](Setup Mode)

Constrains pins to a logic value or relationship. You can use this command on primary inputpins, or compare two different designs under certain input constraints. The supportedconstraints are:

■ 0-state

■ 1-state

■ One-hot

■ One-cold

■ Zero-one-hot

■ Zero-one-cold

The one-hot constraint lets only one pin be at a 1-state and the remaining pins be at a 0-state.The one-cold constraint lets only one pin be at a 0-state and the remaining pins be at a1-state.

Wildcard: The wildcard (*) represents any zero or more characters in primary input andmodule names.

Parameters

0 | 1 Constrains pins to a constant 0 or 1 value.

ONE_Hot Specifies that only one of the pins can have a high value.

ONE_Cold Specifies that only one of the pins can have a low value.

ZERO_ONE_Hot Specifies that all pins can have a low value, but only one canhave a high value.

ZERO_ONE_Cold Specifies that all pins can have a high value, but only one canhave a low value.



Related Commands

DELETE PIN CONSTRAINTS

REPORT PIN CONSTRAINTS

primary_pin*… Specifies that a list of primary input names that will beconstrained to a certain state. (These primary inputs are fromeither the Golden or Revised design.) The wildcard (*) issupported.

-REPlace Changes the previously specified pin constraint.

-ROot Applies the constraints to the root module(s). This is thedefault.

-Module name* Applies the constraints to the specified module(s). The wildcard(*) is supported.

-All Applies pin constraints to “all” modules. -All applies within thegiven defaults.

-Golden Specifies that the primary input names are from the Goldendesign. This is the default.

-Revised Specifies that the primary input names are from the Reviseddesign.

-Both Specifies that the primary input names are from both theGolden and Revised designs.



ADD PIN EQUIVALENCESADD PIn Equivalences

< primary_pin primary_pin*…>[-Invert <primary_pin*…>][-ROot | -Module <name*> | -All][-INPUT_OUTPUT][-User | -Hier][-Golden | -REvised | -Both](Setup Mode)

Defines the relationship between pins; specifies whether module pins are equal or inverted.Use this command to complete logic abstraction or to resolve differences in logic duringcomparisons.

Note: Pin equivalences are considered only when the pin equivalences are on a root module.If a submodule has black-box pin equivalences, the Conformal Equivalence Checker checksto see if they are true when you use the ADD COMPARE POINT -all command.

Wildcard: The wildcard (*) represents any zero or more characters in primary input andmodule names. Wildcards are not valid for buses.

Parameters

primary_pin primary_pin*…

Specifies a list of primary input pins that are equivalent. Thefirst input pin is classified as the representative pin.

The wildcard (*) is supported for the second pin.

-Invert primary_pin*…

Specifies that the primary pins are inverted with respect tothe referenced primary pin. Use the REPORT PINEQUIVALENCES command to identify the inverted primaryinput pins. The (-) denotes inverted pins.


-ROot Applies the pin equivalences to the root module. This is thedefault.

-Module name* Applies the pin equivalences to the specified module. Thedefault is the root module.

You can also use this command on buses, by defining thebus range using <name[msb:lsb]>.



Example

The following example implies that p1, p2, and p3 are equivalent and are inverted to p4, p5,and p6.

add pin equivalences p1 p2 p3 -inv p4 p5 p6

Related Commands

DELETE PIN EQUIVALENCES

REPORT PIN EQUIVALENCES

-All Applies the pin equivalences to “all” the modules. -Allapplies within the given defaults.

-INPUT_OUTPUT Enables the handling of internal signals that pass in and outof the same module. With this option, you can also constrainan output pin of a blackbox to be equivalent to an input pin.

Note: The representative pin should always be driving all theequivalent pins.

-User When you use this option, Conformal includes these addedpin equivalences in the comparison, when thecorresponding module is a blackbox. (This option does notapply to primary inputs.) This is the default.

-Hier When you use this option, Conformal does not do theadditional check associated with the -user option.

-Golden Specifies that the pin equivalences are from the Goldendesign. This is the default.

-Revised Specifies that the pin equivalences are from the Reviseddesign.

-Both Specifies that the pins specified as equivalent exist in boththe Golden and Revised designs.

Note: If you use the -both option, every primary input pinyou list must exist in both designs (Golden and Revised).Otherwise, Conformal returns an error message.



ADD PRIMARY INPUTADD PRimary Input

< pathname* [-Net] | pathname -Pin>[-Cut | -NOCut][-Golden | -Revised | -Both](Setup Mode)

Adds a new primary input pin to a specified net or pin name. This new primary input pin isclassified in the User class of primary inputs. (The original primary inputs of the design areclassified in the System class of primary inputs.) Use the -cut option if the added primaryinput is the only driver to the net or pin. Otherwise, along with the other original drivers, thenet becomes a wired net.

Wildcard: The wildcard (*) represents any zero or more characters in net paths.

Parameters

Related Commands

DELETE PRIMARY INPUTS

REPORT PRIMARY INPUTS

pathname* -Net Adds the primary input to the specified net path. -Net is thedefault.

pathname -Pin Adds the primary input to the specified pin path.

-Cut Cuts the other original drivers of the specified path and allowonly the newly added primary input as the driver of the net orpin. This is the default.

-NOCut Does not cut the other original drivers of the specified net or pinname. This option makes the new net a wired net.

-Golden Adds the new primary input in the Golden design. This is thedefault.

-Revised Adds the new primary input in the Revised design.

-Both Adds the new primary input in both the Golden and Reviseddesigns.



ADD PRIMARY OUTPUTADD PRimary Output

<net_pathname*>[-Golden | -Revised | -Both](Setup Mode)

Adds a new primary output pin to a specified net name. This new primary output pin isclassified in the User class of primary outputs. (The original primary outputs of the design areclassified in the System class of primary outputs.) This command is used for diagnosis whenan internal value can be observed at a primary output.

Wildcard: The wildcard (*) represents any zero or more characters in net paths.

Parameters

Related Commands

DELETE PRIMARY OUTPUTS

REPORT PRIMARY OUTPUTS

net_pathname* Adds the primary output to the specified net path.


-Golden Adds the new primary output in the Golden design. This is thedefault.

-Revised Adds the new primary output in the Revised design.

-Both Adds the new primary output in both the Golden and Reviseddesigns.



ADD RENAMING RULEADD REnaming Rule

[[-PIN_MULTIDIM_TO_1DIM][-ADD | -NOADD][-NOASCEND | -ASCEND][-VERBOSE] ]

[<rule_name> <string> <string>[[ -MAp ]

[-TYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>…|-NOTYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>…]

|-MOdule|-PIn [-BBox <module_name>]

][-REPlace][-Golden | -Revised | -BOth] ](Setup / LEC Mode)

Specifies renaming rules for key point mapping, module renaming (when reading in the libraryand designs for hierarchical comparisons), and pin renaming for blackboxes

Use the REPORT RENAMING RULE command to display the list of all renaming rules.Conformal applies renaming rules sequentially, in the order they were added.

Key Point Mapping

When you define renaming rules in the Setup system mode, they guide the automaticmapping process that occurs during the system mode switch from Setup to LEC. When youare in the LEC system mode, and find that the key point mapping is not complete, defineadditional renaming rules and repeat key point mapping to improve the mapping results. Theautomatic mapping process refers to the naming specified by the final renaming rules.

Module Renaming

You must use this command before the READ LIBRARY and READ DESIGN commands. Ithelps map modules together for hierarchical comparisons.

Pin Renaming

This command applies to the specified blackbox or to all blackboxes, which is the default.



Renaming Rule Structure

When defining renaming rules, the first string specifies the pattern to be matched; the secondstring specifies how Conformal is to rename or make substitutions. The first string can containexpressions of the following types:

Any character can be preceded by the escape character “\” to cancel any special meaning ithas. Use the escape character whenever any of the following special characters representsa simple character.

% . * + ^ $ | ( ) [ ] \

The second string can contain expressions of the following types:

%d Matches one or more digits, [0-9]+

%a Matches one or more alphabetical characters, [a-zA-Z]+

%s Matches one or more digits or alphabetical characters,[0-9a-zA-Z]+

%u Matches one or more alphabetical characters or underscores,[a-zA-Z_]+

%w Matches one or more digits or alphabetical characters orunderscores, [0-9a-zA-Z_]+

x Matches character “x”

abc Matches string “abc”

. Matches any single character

* Matches zero or more repetitions of the preceding expression

+ Matches one or more repetitions of the preceding expression

^bol Matches “bol” only when it occurs at the beginning of a string

eol$ Matches “eol” only when it occurs at the end of a string

x|abc Matches “x” or “abc”

[oz!] Matches “o”, “z”, or “!”

(pattern) Matches anything that is matched by “pattern” and renders itreferable (through @n) in the substitution string

abc Replaces string “abc” for each matched string



The following table shows implementation examples for various pattern-matching andsubstitution strings. For pattern-matching strings, use parentheses to group individualpatterns into a single pattern, as demonstrated in the example (ab|de)*.

@n Replaces the string that matches the nth %d, %a, %s, or apattern enclosed in parentheses.The n is a digit other than 0, and you can use @{nn} to refer tofurther matches (that is, 10…99)

#(expr) Where “expr” is an arbitrary expression that can only containconstant integers, @n expressions, and the operators +,-,*, /and ( )

First String Second String Source Result

%a%d @1[@2] xyz123 xyz[123]

%a_%d @1[@2] arr_5 arr[5]

_z_ / _z_top_z_inst /top/inst

âbc XYZ abcabc XYZabc

abc$ XYZ abcabc abcXYZ

âbc$ XYZ abcabc abcabc

âbc$ XYZ abc XYZ

[oz!] $ aaoaazaa!aa aa$aa$aa$aa

\%d\%s AA %a%d%s%b %aAA%b

\(ab ZZ xx(abcd xxZZcd

%s\.%d @1[@2] xx.123 xx[123]

(x|abc) YY abcx abcx YYYY YYYY

(ab|de)* YY ababdeab YY

%s%d @1[#(7-@2)] abc3 abc[4]

%s%d @1[#(2*@2)] abc5 abc[10]

reg%d\[%d\] reg[@2] reg2[5] reg[5]



Important

Do not include the forward slash, “/”, at the top level for either the first or secondstring.

For example, express /top_module/adder/reg[5] astop_module/adder/reg[5].

Parameters

-PIN_MULTIDIM_TO_1DIM

Allows you to create renaming rules to map multidimensionalarray pins to one-dimensional array pins.

-ADD Shows the pins found when adding the rules into the system.This is the default.

-NOADD Shows the pins found without adding the rules.

-NOASCEND Renames the pins in an descending order. This is the default.

-ASCEND Renames the pins in an ascending order.

-VERBOSE Shows the renaming patterns.

rule_name Specifies a rule identification name assigned to a specificrenaming rule.

<string> <string> The first string represents the pattern to be matched.The second string represents the substitution pattern.

-MAp Specifies that the renaming rule applies to key point mapping.This is the default.

-TYpe keypoint_type…

Renames all key points with the specified type. The availabletypes are as follows:

PI Primary Inputs

E TIE-E gates

Z TIE-Z gates

DFF D flip-flops

DLAT D-latches



CUT Artificial gates for breaking combinationalfeedback loops

BBOX Blackboxes

PO Primary Outputs

-NOTYpe keypoint_type…

Renames all key points except the specified types. Theavailable types are as follows:

PI Primary Inputs

E TIE-E gates

Z TIE-Z gates

DFF D flip-flops

DLAT D-latches


BBOX Blackboxes

PO Primary Outputs

-MOdule Specifies that the renaming rule applies to module renamingwhen the library and design are read in.

-PIn Specifies that the renaming rule applies to pin names ofblackboxes.

-BBox module_name Specifies that the pin renaming rules apply to the specifiedblackbox module.

-REPlace Allows the redefinition of an existing renaming rule.

Tip

The difference between using add renaming rule-replace as opposed to using delete renamingrule followed by add renaming rule is thatrenaming rules that are redefined remain in the sameposition in the list of renaming rules. By deleting andadding a rule, the new definition will appear at the endof the list. In some cases, the order in which renamingrules are applied might affect the result.



Example

In the following command, y2[1:0][2:0] in module test2 is renamed y2[5:0]:

add renaming rule -pin_multidim_to_1dim

// Rule created for (test2) y2[1:0][2:0]

// Rule created for (test1) y1[1:0][1:0]

// Rule created for (top) y2[1:0][2:0]

// Rule created for (top) y1[1:0][1:0]

// Rule created for (top) ym[2:3][2:0][1:0]

// 5 rules created. Rules for top module must be manually validated.

You can use the REPORT RENAMING RULE command to view the added rules.

Related Commands

CHANGE NAME

DELETE RENAMING RULE

MAP KEY POINTS

READ DESIGN

READ LIBRARY

REPORT RENAMING RULE

SET MAPPING METHOD

SET NAMING RULE

TEST RENAMING RULE

-Golden Specifies that the renaming rule applies to the Golden design.This is the default.

-Revised Specifies that the renaming rule applies to the Revised design.

-BOth Specifies that the renaming rule applies to both the Golden andRevised designs.



ADD RETENTION MAPPINGADD REtention Mapping

<rule_name><-Module <module_name*> | -Instance <instance_pathname*>

|-NOTag | -Tag <tag_name1*> -Tag <tag_name2*> ... ><-NOAttribute | -Attribute <attribute name>>

[-TYpe <ALL | DFF | DLAT>](Setup / LEC Mode)


Adds the state retention mapping rules for validation of technology mapping of the sequentialelements (DFFs or DLATs) from RTL to gate-level, gate-level to gate-level, or RTL to RTL.

For a description of the default rules that are added by the system, see CHECK LOWPOWERCELLS on page 143.

Parameters

rule_name Specifies a rule identification name assigned to a specificretention mapping rule.

-Module Specifies the module name in the Golden design. All theDFFs or DLATs under the named module will be subjectedto this rule.

-Instance Specifies the instance pathname in the Golden design. Hereinstance pathname refers to only DFF or DLAT instances.The named DFF or DLAT instance(s) would be subjected tothis rule.

Wildcards (*) are supported for the instance pathname.When using a wildcard, it might point to multiple instances.

-Tag Specifies the tag name in the RTL golden side. The ’tagname’ refers to the label names used with a) ’process’blocks in the VHDL RTL and b) ’always’ blocks in the VerilogRTL. All the DFFs or DLATs under the tag-named block willbe subjected to this rule.

Wildcards (*) are supported.



Examples

■ The following command verifies that all registers with a tag label lp_sel* areimplemented with a state retention cell whose power_gating_cell attribute isLPRET_DFF1:

add retention mapping R0 -tag lp_sel* -attribute LPRET_DFF1

■ The following command verifies that all registers in module blockA are implementedwith a state retention cell whose power_gating_cell attribute is LPRET_DFF1:

add retention mapping R1 -module dma -attribute LPRET_DFF1

-NOTag When the Golden side is an RTL design, this implies that allthe DFFs or DLATs which do not have any tag-nameassociated with their ’process’ or ’always’ block will besubjected to this rule.

-Attribute Specifies the ’power gating cell attribute’ for the DFFs orDLATs in the Revised netlist. Different power gating cellattributes are defined for different sets of retention cells inthe Synopsys library (liberty format). When synthesized(technology mapped), the DFFs or DLATs in the Goldendesign (specified using module-name, instance-name, ortag-name) should have the named attribute in Revisednetlist.

-NOAttribute Specifies that, when synthesized (technology mapped), theDFFs or DLATs in the Golden design (specified usingmodule-name, instance-name, or tag-name) should nothave any attribute (power gating cell attribute) in Revisednetlist. In other words, the specified DFFs or DLATs shouldbe technology mapped as ordinary or non-retention cells.

-TYpe <ALL | DFF | DLAT>

Indicates the sequential element type on which to apply theretention mapping rule.

ALL applies the retention mapping rule to all sequentialelements (both DFF and DLAT type). This is the commanddefault when you do not specify the -TYpe option.

DFF applies the retention mapping rule to DFFs only, andDLAT applies the retention mapping rule to DLATs only.



■ The following command verifies that all registers with instance name/U0/*/fifo_dma* are implemented with a state retention cell whosepower_gating_cell attribute is LPRET_DFF2:

add retention mapping R2 -instance "/U0/*/fifo_dma*" -attribute LPRET_DFF2

Related Commands


DELETE RETENTION MAPPING

REPORT RETENTION MAPPING



ADD SEARCH PATHADD SEarch Path

<pathname…>[ |-Design | -Library][-Both | -Golden | -Revised](Setup Mode)

Defines additional search paths outside the current directory for filenames you use in theREAD DESIGN and READ LIBRARY commands. This command is necessary because thedefault is to search for filenames in the current directory; but your design or library can includefilenames that are housed in other directories.

When you add multiple search paths to the list, Conformal does the search in the order pathswere added to the list.

Use the REPORT SEARCH PATH command to display all search paths. Use the tilde character(~) to shorten the specified path.

Parameters

pathname… Specifies the search path for filenames used in the READDESIGN and READ LIBRARY commands.

-Design The READ DESIGN command uses the specified search path.

If you do not specify -library or -design, Conformalapplies this command to both the READ DESIGN and READLIBRARY commands.

-Library The READ LIBRARY command uses the specified search path.

If you do not specify -library or -design, Conformalapplies this command to both the READ DESIGN and READLIBRARY commands.

-Both Specifies that the search path applies to both the Golden andRevised designs. This is the default.

-Golden Specifies that the search path applies to the Golden design andlibrary.

-Revised Specifies that the search path applies to the Revised designand library.



Related Commands

DELETE SEARCH PATH

READ DESIGN

READ LIBRARY

REPORT SEARCH PATH



ADD SUPPLYADD SUpply

<-power | -ground>[-port [-root | -Module <name>] | -global] <name ...>[-Golden | -Revised](Setup Mode)


Defines power/ground ports of a module or the global power/ground signals for the entiredesign.

Parameters

Examples

Instead of specifying .global in a spice netlist, the following commands command have thesame effect:

add supply -power VDD

add supply -ground GND

-power Specifies that the listed names have a VDD attribute.

-ground Specifies that the listed names have a GND attribute.

-port Specifies that the listed names are module ports.

-root Specifies that the listed names reside in the rootmodule. By default, all modules will be applied.

-Module <name> Specifies that the listed names reside in the specifiedmodule. By default, all modules will be applied.

-global Specifies that the listed names are global signals.This is the default.

<name> ... Specifies that a list of net/port names that will bespecified as VDD or GND.

-Golden Specifies that the listed names are from the Goldendesign.

-Revised Specifies that the listed names are from the Reviseddesign.



Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION


DELETE CLOCK



READ PATTERN

REPORT CLOCK




RESOLVE

SET ABSTRACT MODEL



ADD TIED SIGNALSADD TIed Signals

<0 | 1><name*…>[-Net | -Pin][-ROot | -Module <name*> | -All][ |-Design |-Library][-Golden | -Revised | -Both](Setup Mode)

Assigns the specified floating nets or pins to a 0-state or a 1-state in the Golden or Reviseddesign. These tied signals are classified in the User class of tied signals. The original tiedsignals of the design are classified in the System class of tied signals.

Wildcard: The wildcard (*) represents any zero or more characters in net, pin, and modulenames.

Parameters

0 Ties the floating nets or pins to a 0-state.

1 Ties the floating nets or pins to a 1-state.

name*… Specifies a list of names that correspond to either floating nets orfloating pins where you intend to add the tied signal.

-Net Specifies that the listed names are net names. This is thedefault.

-Pin Specifies that the listed names are pin names.

-ROot Specifies that the floating net or pin resides in the current rootmodule. This is the default.

-Module name* Specifies that the floating net or pin resides in the specifiedmodule. The default is the root module.


-All Applies the tied signals to “all” the modules. -All applies withinthe given defaults.

-Design Applies the tied signals to the design.

If you do not specify -design or -library, Conformal appliestied signals to both designs and libraries.



Related Commands

DELETE TIED SIGNALS

REPORT FLOATING SIGNALS

REPORT TIED SIGNALS

-Library Applies the tied signals to the library.

If you do not specify -design or -library, Conformal appliestied signals to both designs and libraries.

-Golden Adds the tied signals to the Golden design. This is the default.

-Revised Adds the tied signals to the Revised design.

-Both Adds the tied signals to both the Golden and Revised designs.



ANALYZE ABORTANAlyze ABort

[-All | <<gate_id | instance_pathname | pin_pathname> ...[-Golden | -Revised]> | -Number <number>][-Summary | -Verbose | -COmpare][-CLass <Abort | Notcompared>](LEC Mode)


Analyzes abort points and recommends actions to help solve the abort points. This commandcan also provide useful information for further abort investigation.

Parameters

-ALL Analyzes all abort points. This is the default.

gate_id Specifies the gate ID for abort analysis.

instance_pathname Specifies the instance pathname for abort analysis.

pin_pathname Specifies the pin pathname for abort analysis.

-Golden Specifies whether the gate ID or pathname is in the Goldendesign. This is the default.

-Revised Specifies whether the gate ID or pathname is in the Reviseddesign.

-Number <number> Specifies the number of abort points to analyze.

-Summary Prints out the summary count of the abort points. This is thedefault.

-Verbose Prints out additional information, such as RTL statistics.

-COmpare Automatically compares the aborted points. Cadencerecommends using this option when running the ANALYZEABORT command.

-CLass <Abort | Notcompared>

Specifies the class of points to analyze. Select Abort toanalyze abort points, or Notcompared to analyzenot-compared points.



Example

The following commands run abort analysis after the initial compare:

compare

analyze abort -compare

Related Commands

COMPARE

RUN HIER_COMPARE

SET ANALYZE OPTION



ANALYZE DATAPATHANAlyze DAtapath

[-MODULE [-RESOURCEFILE <filename>]][-MERGE | -NOMERGE][-NOSHARE | -SHARE][-EFFort <MEDium | HIgh>][-SHARE_OPerator <r1 r2 [.. rN]> ][-NOADDERTREE | -ADDERTREE][-Verbose](LEC Mode)


Analyzes datapath modules. Based on the results of the analysis, Conformal canautomatically resolve multipliers, operator merging, and resource sharing problems.

Note: You cannot run datapath analysis without first mapping the Revised design keypointsto the Golden design keypoints.

Parameters

-MODULE Applies analysis on the datapath modules. The default is in theRevised design netlist.

-RESOURCEFILE <filename>

Specifies the resource filename to analyze the datapathmodules.

-MERGE Applies the operator merging technique. This is the default.

-NOMERGE Does not apply the operator merging technique.

-NOSHARE Does not apply the resource sharing technique. This is thedefault.

-SHARE Analyzes the design for datapath resource sharing.

-SHARE_OPerator Shares the specified operators. See the example for therecommended flow.

Note: If this option is specified, only the sharing is performed,and does not run datapath analysis.



Example

■ The following commands show an example of the recommended flow when using the-SHARE_OPerator option:

analyze datapath -verbose -share_operator mult_30 mult_31

// Note: mult_30: shared

analyze datapath -verbose -share_operator mult_32 mult_33

// Note: mult_32: shared

analyze datapath -verbose

// Note: add_2(clustered): quality evaluated 70% success

// Note: mult_30: quality evaluated 80% success

// Note: mult_32: quality evaluated 100% success

■ The following commands apply datapath module-based analysis followed by thedatapath operator-level analysis:

analyze datapath -verbose -module -resourcefile resourcefile.name

analyze datapath -verbose

Related Commands

ANALYZE MULTIPLIER

REPORT DATAPATH OPTION

REPORT DATAPATH RESOURCE

REPORT MULTIPLIER OPTION

SET DATAPATH OPTION

-EFFort <MEDium | HIgh>

Specifies the effort level. Choose MEDium (the default), or HIghto help provide better analysis of some multipliers, but mightincrease the analysis runtime.

-NOADDERTREE Does not automatically add parentheses to the input operandsof adder trees. This is the default.

-ADDERTREE Automatically adds parentheses to the input operands of addertrees.

-Verbose Provides additional information.



SET MULTIPLIER IMPLEMENTATION

SET MULTIPLIER OPTION




ANALYZE ECOANAlyze ECo

<patch_filename>[-REPlace][-EFFort <HIGH | LOW | MEDIUM | SUPER | ULTRA>][-PRESERVE_clock](LEC Mode)

Analyzes the ECO change in the Revised root module comparing to the Golden root module.The logic change is written to the specified patch file, which contains the Verilog module withthe port names corresponding to the nets in the Golden design.

Note: Only the logic cone under Non-EQ points are analyzed by the command.

Parameters

Examples

In the following commands, module G1 contains the placed and routed netlist, and module G2contains the synthesized netlist from modified RTL. The two netlist will be compared first, thenthe ANALYZE ECO command will analyze the change implemented by G2 and generates apatch file, which contains a single Verilog module G1_eco. The patch can then can be readback and applied to G1 with the APPLY PATCH command, such that the G1 will be equivalentto G2, meaning that G1 implements the ECO change in G2.

Note: The patch can be remapped or optimized by other tools before it is read back.

SETUP> set root module G1 -golden

SETUP> set root module G2 -revised

SETUP> set system mode lec

LEC> add compare point -all

LEC> compare

LEC> analyze eco patch.v -replace

<patch_filename> Specifies the name of the patch file.

-REPlace Replaces the existing file.

[-EFFort <HIGH | LOW | MEDIUM | SUPER | ULTRA>]

Specifies the analysis effort level. The command default isHIGH.

-PRESERVE_clock Attempts to minimize the changes to the clock network.



SETUP> set system mode setup

SETUP> read design patch.v -append

SETUP> apply patch G1 G1_eco

Related Commands

ADD ECO PATCH

APPLY PATCH

COMPARE




ANALYZE IMPLICATIONANAlyze IMplication

[-ONE | -1 <GateID...>][-ZERO | -0 <GateID...>][-ADD <-ONE | -1 | -ZERO | -0> <GateID...>][-DELete <GateID...>][-CHECK_Redundancy <GateID...>][-CHECK_Constant <GateID...> ][-Block <GateID...>][-DEPTH <depth>][-Golden | -Revised](LEC Mode)


Analyzes implication values on the design. If you assign value(s) on certain gate(s), thiscommand shows what the necessary values are on other gates to satisfy the assignment. Itcan also show if a gate has redundant fanin and if a gate is a constant gate.

The results are displayed in the schematic view with the following colors:

■ Blue: initial assignments

■ Green: current implication values

■ Red: gates on the conflict path

■ Purple: location where conflict occurred

In the schematic view, you can also right click the gate and set a value. Holding the mousepointer on a gate, an information box will show if this gate has redundant fanin and if it is aconstant gate.

Parameters

-ONE | -1 Specifies that the following gate(s) will be assigned one.

-ZERO | -0 Specifies that the following gate(s) will be assigned zero.

-ADD Specifies that the following assignment(s) will be added intoprevious assignment(s).

-DELete Specifies that the following gate(s) will be removed fromprevious assignment(s).

-CHECK_Redundacy Checks the specified gate to see if it has redundant fanins.



Related Commands

READ DESIGN

READ LIBRARY

-CHECK_Constant Checks the specified gate to see if it is constant gate.

-Block Blocks the gate(s) so that implication will not go across it.

-DEPTH Specifies the logic depth beyond which implication will not beperformed. The default value is 10.

-Golden Specifies that the gate IDs are from the Golden design. This isthe default.

-Revised Specifies that the gate IDs are from the Revised design.



ANALYZE MULTIPLIERANAlyze MUltiplier

[-NOCDP_INFO | -CDP_INFO](LEC Mode)

Initiates an analysis of multiplier modules. Based on the results of the analysis, Conformalcan automatically resolve architecture mismatches and operand swapping problems.Additionally, use the -cdp_info option if you want Conformal to let you know whenConformal Ultra will be helpful.

Use this command after switching from Setup to LEC mode:

set system mode lec

…

analyze multiplier -cdp_info


compare

Parameters

Related Commands

ANALYZE DATAPATH

ANALYZE MULTIPLIER




SET DATAPATH OPTION


-NOCDP_INFO Does not display a message when Conformal Ultra canenhance multiplier analysis. This is the default.

-CDP_INFO Displays a message when Conformal Ultra can enhancemultiplier analysis.



ANALYZE NONEQUIVALENTANAlyze NOnequivalent

[ | <gate_id> | <instance_pathname*> ...[-Golden | -Revised] ]

[-Summary | -Verbose](LEC Mode)


Helps identify the possible causes of non-equivalent compared points.

Parameters

Examples

The following shows an example of a report when running the ANALYZE NONEQUIVALENTcommand. The lines in bold indicate the cause of the problems:

LEC> analyze noneq 213

//Command analyze noneq 213

Analyzing non-equivalent compared points:

(G) + 213 DFF /wbs/hvlen_reg[28]

(R) + 6277 DFF /wbs/hvlen_reg[28]/U$1

The clock of DFF in Golden is not gated.

The clock of DFF in Revised is gated.

Analysis of non-equivalent compared points:

<gate_id> Analyzes non-equivalent compared points for the specifiedgate.

<instance_pathname*> ...

Analyzes non-equivalent compared points for the specifiedinstance.

-Golden Analyzes non-equivalent compared points in the Goldendesign. This is the default.

-Revised Analyzes non-equivalent compared points in the Reviseddesign.

-Summary Provides a summary of the analysis. This is the default.

-Verbose Provides additional information for each individualnon-equivalent compared point.



Gated clock of of DFF or DLAT. (Occurrence: 1)

Unknown reason. (Occurrence: 1)

LEC> analyze noneq 170 -revised

//Command analyze noneq 170 -revised

Analyzing non-equivalent compared points:

(G) + 167 PO /wbm_sel_o[0]

(R) + 170 PO /wbm_sel_o[0]

Following constraints may be necessary:

Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0]

Analysis of non-equivalent compared points:

Sequential constant. (Occurrence: 1)

Unknown reason. (Occurrence: 1)

Clock Gating

You can fix the first problem in the report:

The clock of DFF in Golden is not gated.

The clock of DFF in Revised is gated.

by running the following command in Setup mode:

set analyze option -auto

or the following command in LEC mode:

analyze setup

Sequential Constant

You can fix the second problem in the report:

Following constraints may be necessary:

Constant 1: (G) 1026 DFF /wbm/sel_o_reg[0]

by running auto analysis in Setup mode with the following commands:

set analyze option -auto

set flatten model -seq_constant

or the following command in LEC mode:

remodel -seq_constant

Related Command

ANALYZE SETUP



ANALYZE POWER ASSOCIATIONANAlyze POwer Association

[-Golden | -Revised][-Module <module_name*>...>][-OUT_Dofile <dofile_name> | -OUT_CPF <filename>][-REPlace](Setup / Verify Mode)


Analyzes the module’s SPICE netlist and identifies the power/ground pin for each input andoutput pin with which it is associated.

Notes:

■ The power/ground pin definition can come from LEF or SPICE.

■ Run the SET SPICE OPTION -NOBULK command before reading in the SPICE designto maintain the connectivity of power/ground ports.

■ Each input or output pin can have only one associated power/ground pin. Multiplepower/ground pin association are ignored.

Parameters

-Golden Analyze the Golden design. This is the default.

-Revised Analyze the Revised design.

-Module <module_name*> ...>

Specifies the module(s) to be analyzed. Without this option, allmodules in the design are analyzed. This accepts wildcards.

-OUT_Dofile <dofile_name>

Specifies the file to output the ADD POWER ASSOCIATIONcommand.

-OUT_CPF <filename>

Specifies the output CPF file.

-REPlace Replaces the specified -OUT_Dofile or -OUT_CPF file if italready exists.



Related Commands

READ DESIGN -spice

SET SPICE OPTION



ANALYZE RETIMINGANAlyze REtiming

[-COMBinational_identical][-PIPELINE [<identifier* ...>] [-BACKWARD] ][-GENERAL][-MERGE | -NOMERGE][-DIAGNOSIS <identifier> [-BACKWARD] ][-VERBose][-BOth | -GOLden | -REVised](LEC Mode)


Initiates pipeline retiming, retiming for RC synthesized netlist, or retiming for designs that arecombinationally equivalent. Normally, you use this command to retime a Revised design tomatch a referenced Golden design. If this command is successful, you can use the COMPAREcommand to ensure that the two designs are equivalent. If this command is unsuccessful,then the original retiming you performed is incorrect.

For more guidelines and examples, see “Conformal Ultra: Advanced LEC Capabilities” in theEncounter Conformal Equivalence Checking User Guide.

Parameters

-COMBinational_identical Use this option on combinationally equivalent designs.Use option when you have retimed a design and want toconfirm that it is equivalent to another design. Conformalretimes its registers to match their position in thereference design.

Note: If you specify this option, it must be the first optionin the command line.

Tip

If you can replace the DFF -> Q connectionswith buffers and your designs are still identical,then your Golden and Revised designs areconsidered combinationally equivalent.



-PIPELINE <identifier* ...> -BACKWARD

Moves all registers to the primary output side of thedesign as much as possible, or use the <identifier>option to specify one or more registers, separated by aspace. The wildcard (*) is accepted.

-BACKWARD moves registers backward to the primaryinput side of the design as much as possible. With thisoption, pipeline backward retiming can be performed oneither all registers or a selected set of registers.

-GENERAL Retimes the Revised design to match the registers onthe Golden side. Registers in the Golden design will notbe retimed.

-MERGE Specifies that equivalent registers are merged afterregisters are moved, including inverted-equivalentregisters. This helps to reduce the unmapped registerkeypoints and the resulting false non-equivalences. Thisis the default.

-NOMERGE Disables the merging of equivalent registers after theyare moved.

-DIAGNOSIS <identifier> -BACKWARD

Checks that a register can be retimed a step forward orbackward. If the retime movement cannot succeed, thereason for the failure is reported. By default, thisdiagnoses the forward retiming step.

Note: This option will not change the netlist, it onlyprovides information about the specified retiming step.

-BACKWARD specifies that the backward retiming step isdiagnosed.

-VERbose Prints additional information, including a list of currenttasks and statistics.

-BOTh Executes this command on both the Golden and Reviseddesigns. This is the default.

-REVised Executes this command on the Revised design and usesthe Golden design as the reference design.

-GOLden Executes this command on the Golden design and usesthe Revised design as the reference design.



Examples

The following command initiates backward pipeline retiming for register r1 and registerswhose identifiers begin with r2, such as r2a and r21, in the Revised design:

analyze retiming -pipeline r1 r2* \-revised -backward

The following demonstrates how to use the ANALYZE RETIMING -comb_identicalcommand with other commands.

1. Read in your library.

SETUP> read lib -lib matrox_test1.lib// Parsing file matrox_test1.lib ...// Note: Read Liberty library successfully

2. Read in your Golden and Revised designs.

SETUP> read design -golden matrox_test1_brt.v// Parsing file matrox_test1_brt.v ...// Golden root module is set to ’hst_ssurfdes’// Note: Read VERILOG design successfully

SETUP> read design -revised matrox_test1_art.v// Parsing file matrox_test1_art.v ...// Revised root module is set to ’hst_ssurfdes’// Note: Read VERILOG design successfully

3. Switch to LEC mode.

SETUP> set system mode LEC

// Processing Golden ...// Modeling Golden ...// Processing Revised ...// Modeling Revised ...// Mapping key points ...

.

.

.

4. Use the ANALYZE RETIMING -comb_identical command and attempt to retime theRevised design to match the Golden design.

LEC> analyze retiming -combinational_identical

// Retimed successfully 859 registers in Revised as 141 registers// All comparison points have been deleted// All key points have been unmapped// Mapping key points ...===========================================================================Mapped points: SYSTEM class---------------------------------------------------------------------------Mapped points PI PO DFF Total---------------------------------------------------------------------------Golden 1632 29 147 1808---------------------------------------------------------------------------Revised 1632 29 147 1808===========================================================================



5. Add “all” mapped points, excluding primary inputs, as compare points.

LEC> add comp points -all

// 176 compared points added to compare list

6. Use the COMPARE command to start the equivalency checking comparison.

LEC> compare===========================================================================Compared points PO DFF Total---------------------------------------------------------------------------Equivalent 29 147 176===========================================================================

Related Commands

ADD COMPARED POINTS

ADD MODULE ATTRIBUTE

COMPARE



ANALYZE SETUPANAlyze SEtup

[-NOCUT | -CUT][-NOLIBRARY_VERIFICATION | -LIBRARY_VERIFICATION][-VERBose](LEC Mode)


Automatically resolves the setup related issues so that non-equivalency due to incorrectsetup can be prevented or resolved.

Note: To resolve sequential constant optimization with this command, you must use thefollowing command:


Parameters

Related Commands

ANALYZE NONEQUIVALENT

SET ANALYZE OPTION

-NOCUT Does not analyze loop cutting. This is the default.

-CUT Analyzes loop cutting. When creating flattened netlists, theConformal software breaks all loops by inserting CUT gates,which could cause false non-equivalences. With this option, youcan resolve these false non-equivalences.

-NOLIBRARY_VERIFICATION

Does not perform setup analysis for library cell verification. Thisis the default.

-LIBRARY_VERIFICATION

Performs setup analysis for library cell verification.

-VERBose Provides additional information.



APPLY PATCHAPPly PAtch

<module_under_ECO_name><patch_module_name>[-KEEPHierarchy][-NETnaming <format_string>][-INStancenaming <format_string>][-SEQuentialnaming <format_string>][-Golden | -Revised](Setup Mode)

Applies the ECO change specified in the patch module, generated by the ANALYZE ECOcommand, to the module under ECO. The patched module can be written out with the WRITEDESIGN command.

Note: The patch generated by the ANALYZE ECO command can contain unmappedprimitives. You can use the synthesis tool or the MAP ECO PATCH command to map the patch.

Parameters


Specifies the name of the module being changed for ECO.

<patch_module_name> Specifies the name of the patch module containing the ECOchanges.

-KEEPHierarchy Specifies that the ECO changes will be put in a submodule.

-NETnaming <format_string>

Specifies the net naming format of the ECO nets. For example,for eco_net_%d, the %d will be an integer that makes the netname unique.

-INStancenaming <format_string>

Specifies the instance naming format of the ECO combinationalcells. For example, for eco_instance_%d, the %d will be aninteger that makes the instance name unique.

-SEQuentialnaming <format_string>

Specifies the instance naming format of the ECO registers andlatches. For example, eco_%s, where %s is the original registername.




Examples

For a set of sample commands that shows this command and related commands in context,see the example for ADD BLACK BOX on page 37.

Related Commands

MAP ECO PATCH

OPTIMIZE PATCH




ASSIGN PIN DIRECTIONASSign PIn Direction

<IN | OUT | IO><module_name><pin_name*>[-Golden | -Revised | -Both][-FROM_DIr <IN | OUT | IO>](Setup Mode)

Defines a module pin’s direction. SPICE netlist ports do not have direction, unless you supply*.pininfo <pin>:<direction> as a CDL comment and read it in as an inout.Abstraction analyzes the circuit and assigns pin direction—when determinable. In somecases, you need to assign pin direction manually to complete abstraction.

Note: You can use this command instead of the ADD MOS DIRECTION command to assistabstraction.

Wildcard: The wildcard (*) represents any zero or more characters in pin names.

Parameters

Examplesassign pin direction in mux2p sela -revised

assign pin direction out mux4p y -golden

IN Specifies that the assigned pin direction is input.

OUT Specifies that the assigned pin direction is output.

IO Specifies that the assigned pin direction is I/O.

module_name Specifies that the pin resides in the specified module.

pin_name* Assigns a direction to the specified pin.

-Golden Assigns the pin direction to the Golden design. This is thedefault.

-Revised Assigns the pin direction to the Revised design.

-Both Assigns the pin direction to both the Golden and Reviseddesigns.

-FROM_DIr Only pins which have the direction specified by this option’sargument will be redirected.



assign pin direction in mux2p sela y -both

//Assigns direction to pins sela and y.

assign pin direction IN mod pin_* -from_type IO

//Changes all IO pins whose name matches ‘pin_*’ in//module ‘mod’ to IN pins on the golden side.

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE

DELETE CLOCK



READ PATTERN

REPORT CLOCK




RESOLVE



BACKWARDBACkward

[integer](LEC Mode)

Reports fanin gate information from the currently displayed flattened gate information. Thefanin gate you choose with this command becomes the current flattened gate. Use thiscommand to trace gates in place of repeatedly using the REPORT GATE command.

Note: This command does not report gates at the design level.

Parameters

Related Commands

FORWARD

REPORT GATE

integer Specifies which fanin gate is reported. The value 1 denotes thefirst fanin. The default value is 1.



BREAKBREak

(Setup / LEC Mode)

Terminates the dofile script and returns you to the system mode prompt.

Related Commands

CONTINUE

DOFILE

SET DOFILE ABORT



CHANGE GATE TYPECHAnge GAte Type

<identifier>-Type <gate_type>[-help][-Golden | -Revised](LEC Mode)

Changes the gate type of a selected object in the schematic viewer.

Note: You cannot use this command on pins and nets.

Note: If you invoke the Flatten Schematics window for a candidate gate (such asCorresponding Supports and Compared Points) from the Diagnosis Manager, you cannotchange its gate type.

Parameters

identifier Specifies the gate ID or instance pathname.

If you do not specify one of the following options, Conformalautomatically determines if the identifier is a number or a path.In the case of a number, Conformal uses the -id option;otherwise, Conformal searches for the gate with the-instance, -pin, or -net option; in this respective order.

-Type <gate_type> Changes the specified gate type, where <gate_type> could beone of the following:

■ AND

■ NAND

■ OR

■ NOR

■ XOR

■ XNOR

■ BUF

■ INV

Note: Not all types are available for all objects



Related Commands

REPORT GATE

-help Returns a list of potential candidate gate types that can beapplied.

-Golden Specifies that the identifier is in the Golden design. This is thedefault.

-Revised Specifies that the identifier is in the Revised design.



CHANGE NAMECHAnge NAme

<filename>[-Summary |-Verbose][-Golden |-Revised |-Both](Setup Mode)

Converts netlist net names, port names, and cell names back to their original names. Thus,Conformal does key point mapping faster and more efficiently. The most common use of thiscommand is to change the names in a post synthesis netlist back to their original,presynthesis forms.

After Conformal reads in the file containing the original names and new names, it makes theconversion. Generally, the synthesis tool you have used generates the file describing thechanges. Consult the specific vendor’s tool documentation for additional change nameinformation.

The format of the change name file is as follows:

■ The change name information is preceded by dashes.Note the dashes in the example below that separate column headers and the changename information. Conformal recognizes this file as a change name file format when itdetects the dashes.

■ The “Design” column consists of module names.For example, see mod0_module in the sample Change Name file below.

■ The “Type” column consists of elements that belong to the specified design (that is, cell,port, and net).

■ The “Object” is the original name. Conformal will change the name back from the “NewName” to the original name.

■ The “New Name” is the name assigned by the synthesis tool

Sample Change Name File

Design Type Object New Name

----------------------------------------------------------

mod0_module port port0_input1 port0_1

mod0_module net net0_output net0_t

mod1_module port port1_input1a port_1a

mod1_module cell net1_subinstantiation net1_n



Parameters

Related Commands

ADD RENAMING RULE



filename Specifies the file that contains name changes.

-Summary Prints out the summary count of the number of name changes.This is the default.

-Verbose Prints out a message for each name change.

-Golden Changes names in the Golden design. This is the default.

-Revised Changes names in the Revised design.

-Both Changes names in both the Golden and Revised designs.



CHECK LOWPOWER CELLSCHEck LOwpower Cells

(LEC Mode)


Performs low power checks for low power cell types that were specified with the SETLOWPOWER OPTION command. This check consists of the state retention technologymapping check, isolation and level-shifter cell check, and the power domain consistencycheck. These checks are described as follows:

State Retention Cells

For state retention cells, this command does the technology mapping check to ensure thatthe sequential elements (DFFs or DLATs) are technology mapped in accordance with theretention mapping rules during synthesis. These retention mapping rules include all the userrules added with the ADD RETENTION MAPPING command and the default rule added bythe system.

The following three default rules are added by the system:

Note: For any sequential pairs, only one of the default rules take effect.

■ Default: Checks that the tag name used in the Golden design is mapped to a non-stateretention cell in the Revised design. A non-state retention cell is a cell that does not havea power_gating_cell attribute. This rule is normally applied during RTL to gate-levelchecks.

■ Default1: Checks that the power_gating_cell attribute in the Golden design isexactly the same as the power_gating_cell in the Revised design. This checkensures that non-state retention cells (regular DFFs or DLATs) are mapped to non-stateretention cells, or state retention cells are mapped to state retention cells. This rule isnormally applied during gate-level to gate-level checks.

■ Default2: Checks that the tag name used in the Golden design is exactly the same asthe tag name used in the Revised design. This rule is normally applied during RTL to RTLchecks.



Isolation Cells and Level-Shifter Cells

For isolation cells and level-shifter cells, this command does the technology mapping checkand equivalence check.

The technology mapping check ensures that for each low power cell (isolation cell orlevel-shifter cell) in the Golden design, there is a corresponding low power cell in the Reviseddesign. To establish the correspondence, the Conformal software inserts key points (cutgates) at the output of low power cells and performs name-based mapping. If it does not findmapping for a low power cut gate, it sets the status of the corresponding low power cell toFAIL; otherwise, the status is set to PASS.

The equivalence check (EC) ensures that for the mapped low power cell pair, the logic feedingthem is equivalent in both the Golden and Revised designs. To perform EC, the Conformalsoftware adds the low power cut gates as compare points and these are proven equivalent ornon-equivalent during compare (when running the COMPARE command).

Note: The CHECK LOWPOWER CELLS command performs only the technology mappingcheck for isolation cells and level-shifter cells. The EC checking results are received afterrunning the COMPARE command.

After performing the low power check, a status summary is printed for all low power cells.

Power Domain Consistency Check

Power domain consistency checking is available in the CPF flow. This checks whether thesequential mapped pair resides in the same power domain between the Golden and Reviseddesigns. You can perform this check after reading in the CPF files for both the Golden andRevised designs. For RTL and synthesized gate netlists, the power domain of key-points canonly be obtained from the CPF specification. For the physical netlist, the power domain canbe obtained either from the CPF specification or by tracing the power and ground pins.

The power domain consistency check sets the status of the mapped pair to FAIL if the powerdomains of the Golden and Revised sequential points in the mapped pair are different. In thecase of merged sequential points, if the power domains of any of the merged elements aredifferent, the power domain consistency check will set the status of the corresponding pair toFAIL.

Note: The power domain consistency check is only enabled for sequential compare points.

Note: Use the SET MAPPING METHOD -unreach command to allow mapping and checkingthe consistency of power domains for unreachable key-points.



If the power domain cannot be obtained for sequential element in the mapped pair, the powerdomain consistency check sets the mapped pair status to NOT-CHECKED. The following arethe scenarios where power domains cannot be obtained for a sequential element:

■ CPF is not read in.

■ CPF specification is incomplete.

For example, no default power domain is specified or CPF does not have the definitionof internal power and ground nets.

■ LEF file is not read in.

■ Power and Ground pins are floating in the physical netlist.

Related Commands

ADD LOWPOWER CELLS

ADD RETENTION MAPPING

COMPARE



SET LOWPOWER OPTION



CHANGE NET TYPECHAnge NEt Type

<TRI | TRI0 | TRI1 | TRIREG | TRIAND | TRIOR><net_name>|-Module <name>][-Golden | -Revised](Setup Mode)


Modifies the database so that it appears that the changed net types were declared in theoriginal Verilog netlist.

Parameters

Related Command

ADD NET ATTRIBUTE

TRI Specifies a tristate net type. This is the default.

TRI0 Specifies a net of type TRI0.

TRI1 Specifies a net of type TRI1.

TRIREG Specifies a net of type TRIREG.

TRIAND Specifies a net of type TRIAND.

TRIOR Specifies a net of type TRIOR.

-Module <name> Specifies the module name of the net to be changed. By default, thiscommand changes the net in the root module.



CLOSE SCHEMATICSCLOse SChematics

(Setup / LEC Mode)

Closes all schematic viewer windows.

Note: You cannot use this command in non-GUI mode.

Related Command

OPEN SCHEMATICS



COMMIT CPFCOMmit CPf

[-INSERT][-GOLden | -REVised | -BOTH](Setup Mode)


Applies CPF low power cell information. When performing insertion, the cell types can belevel shifter cells, isolation cells, and state retention cells. These low power cells can eitherbe defined in .lib or defined in CPF files. You can only run this command after successfullyreading in the CPF files.

Parameters

Examples

The following commands show an example of the CPF equivalency checking flow, whichperforms low power cell insertion on the Golden side, and performs equivalency checks withphysical implementation in two CPF files named rtl.cpf and my_library.cpf:

read lef file my_library.lef

read library -liberty my_library.lib -both

read design rtl.v -verilog -golden

read cpf rtl.cpf my_library.cpf

commit cpf -insert

read design physical.v -verilog -revised

add compare point -all

compare

-INSERT Inserts low power cells, which include level shifter, isolation,and state retention cells, into the original design.

-GOLden Inserts low power cells in the Golden design. This is thedefault.

-REVised Inserts low power cells in the Revised design.

-BOTH Inserts low power cells in both the Golden and Reviseddesigns.



Related Command

READ CPF

REPORT CPF LOGIC



COMPARECOMpare

[-NONEQ_Stop <integer>][-ABORT_Stop <integer>][-NONEQ_Print][-ABORT_Print][-PARALLEL <machine_file>][-GATE_TO_GATE][-SIngle][-NOREPORT_BBOX_INPUT | -REPORT_BBOX_INPUT][-NOREPORT_SINGLE_LINE_SUMMARY | -REPORT_SINGLE_LINE_SUMMARY](LEC Mode)

Starts the equivalency checking comparison between the Golden and Revised designs on theadded compared points. During the comparison, the following information is displayed:

■ Progress percentile number, which displays the completion rate

■ Running count, which displays the number of key points that have been compared alongwith the total number of non-equivalent key points

Each compared point results in a status drawn from the following five possibilities:

■ Equivalent

■ Inverted equivalent

■ Nonequivalent

■ Abort

■ Not compared

When Conformal completes the comparison, it displays a summary table of the number ofequivalent and non-equivalent compared points.

Note: If you must interrupt the comparison, the Control-C keys stop the process.

Parameters

-NONEQ_Stop <integer> Stops the comparison after finding the specified number ofnon-equivalent points.

-ABORT_Stop <integer> Stops the comparison after finding the specified number ofabort points.

-NONEQ_Print Displays the non-equivalent points as they are found.



Examples

The following is a set of sample commands that shows this and related commands in context.The following set of commands assumes that you have read in your library, design, and haveswitched to the LEC mode.

-ABORT_Print Displays the abort points as they are found.

-PARALLEL <machine_file>

Note: This is a Conformal Ultra feature.

Runs a comparison on multiple machines.

Tip

You can use the USAGE command to display thetotal CPU time used for all processes.

For more information on creating a machine_file, seeParallel Processing in the Encounter ConformalEquivalence Checking User Guide.

-GATE_TO_GATE Enables an algorithm that might improve the run time oflarge gate-to-gate netlist comparisons.

-SIngle Compares each key point as a single point. By default, theCOMPARE command compares by key point groups.

-NOREPORT_BBOX_INPUT Does not report the blackbox input pins in the comparereport results. This is the default.

-REPORT_BBOX_INPUT Reports the blackbox input pins in the compare reportresults (Equivalent, Non-equivalent, Abort, andNot-compared).

-NOREPORT_SINGLE_LINE_SUMMARY

Does not print a single line summary of the compare results.This is the default.

-REPORT_SINGLE_LINE_SUMMARY

Prints a single line summary of the compare results.



1. Use the ADD COMPARED POINTS command to add mapped points to the compare list.

LEC> add compare point -all

//2 compared points added to compare list

2. Use the COMPARE command to start the equivalency comparison between the Goldenand Revised designs.

LEC> compare

============================================================================Compared points PO Total----------------------------------------------------------------------------Equivalent 1 1----------------------------------------------------------------------------Non-equivalent 1 1============================================================================

3. Use the REPORT COMPARE DATA command to report the non-equivalent points.

LEC> rep comp data -noneq

Compared points are: Non-equivalent+ 11 PO /x + 11 PO /x

1 compared point(s) reported============================================================================Compared points PO Total----------------------------------------------------------------------------Equivalent 1 1----------------------------------------------------------------------------Non-equivalent 1 1============================================================================

4. Use the ADD DYNAMIC CONSTRAINT command to add a dynamic constraint to thedesign.

LEC> add dyn con 0 /c -gold

LEC> add dyn con 0 /c -rev

5. Use the REPORT DYNAMIC CONSTRAINTS to report the dynamic constraints in thedesign.

LEC> report dynamic constraints

============================================================================Design ID Type Value Name----------------------------------------------------------------------------Golden 3 PI 0 /cRevised 3 PI 0 /c============================================================================

6. Use the PROVE command to show whether the specified gates are equivalent or notequivalent.

LEC> prove /x /x

//Compared points are: Non-equivalent//(G) + 11 PO /x//(R) + 11 PO /x



7. Use the DIAGNOSE command to diagnose the non-equivalent points.

LEC> diag /x

//Diagnosis for Non-equivalent key points://(G) + 11 PO /x//(R) + 11 PO /x

The diagnosis point can be corrected by changing the following gates:============================================================================Correction ID (R) Type Name----------------------------------------------------------------------------DEL_INVERTER 24 INV /gextra

Related Commands

ADD COMPARED POINTS


DIAGNOSE

PROVE

REPORT COMPARE DATA


RUN PARALLEL COMPARE

SET COMPARE EFFORT

USAGE



CONTINUECONTinue

(Setup / LEC Mode)

Used in conjunction with the BREAK command in a dofile, when a dofile executes the BREAKcommand, Conformal issues a warning and prompts you to use the CONTINUE command.The CONTINUE command has no effect if you type it without being prompted by Conformal.

The CONTINUE command supports mixed GUI and non-GUI mode. For example, you can runa dofile in non-GUI mode, encounter a break in the dofile, issue set gui on, and runcontinue from the GUI. The same applies when you break in the GUI mode: switch tocommand mode and enter continue.

Conformal also supports nested breaks inside dofiles, working in a stack fashion. Forexample, when you type in continue from a lower-level dofile, Conformal proceeds until itencounters the next BREAK command.

Example//Warning: Break dofile ‘my_dofile’ at line 32. Use ‘continue’ command to continue.

% continue

Related Commands

BREAK

DOFILE

SET DOFILE ABORT



COPY MODULECOPy MOdule

<[-Golden | -Revised] source_module_name[-Revised | -Golden] target_module_name>

[-LOGIC | -PINDIR][-USE_RENAME_RULE | -NOUSE_RENAME_RULE](Setup Mode)

Copies the logic or pin direction from a source module in one design to a target module in theother design. If you must copy both the logic and the pin direction, use two separatecommands.

Parameters

-Golden Specifies that the source module is located in the Goldendesign. This is the default.

-Revised Specifies that the source module is located in the Reviseddesign.

source_module_name Specifies the name of the source module to be copied.

-Revised Specifies that the target module is located in the Reviseddesign. This is the default.

-Golden Specifies that the target module is located in the Goldendesign.

target_module_name Specifies the name of the target module for the copy operation.

-LOGIC Copies the logic from the source module into the target module.This is the default.

If you must copy both logic and pin direction, use two separateCOPY MODULE commands.

-PINDIR Copies the pin direction from the source module into the targetmodule. If you must copy both logic and pin direction, use twoseparate Copy Module commands.

-USE_RENAME_RULE Uses renaming rules for matching pin and module names. Thisis the default.

-NOUSE_RENAME_RULE Does not use renaming rules for matching pin and modulenames.



Related Command




DELETE ALIASDELete ALias

<name*…>(Setup / LEC Mode)

Deletes aliases created with the ADD ALIAS command. Use the REPORT ALIAS commandto display a list of all aliases.

Wildcard: The wildcard (*) represents any zero or more characters in alias names.

Parameters

Related Commands

ADD ALIAS

REPORT ALIAS

name*… Deletes the specified aliases.



DELETE BLACK BOXDELete BLack Box

<name*… [-Module] | name… -Instance | -All>[-Golden | -Revised | -Both](Setup Mode)

Deletes specified blackboxes from the design. These blackboxes were either created with theADD BLACK BOX command or were a part of the original design.

Use the REPORT BLACK BOX command to display a list of all blackboxes.


Parameters

Related Commands

ADD BLACK BOX

REPORT BLACK BOX

name*… -Module Deletes blackboxes specified by this list. -module is thedefault.

name… -Instance Specifies that the blackbox names are instance names.

-All Deletes “all” defined blackboxes. -All applies within thegiven defaults.

-Golden Deletes blackboxes from the Golden design. This is thedefault.

-Revised Deletes blackboxes from the Revised design.

-Both Deletes blackboxes from both the Golden and Reviseddesigns.



DELETE CLOCKDELete CLock

<-ALL_Pin | primary_pin…>[-Golden |-Revised](Setup Mode)

Deletes clocks added with the ADD CLOCK command.

Use the REPORT CLOCK command to display a list of all aliases.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE




READ PATTERN

REPORT CLOCK


-ALL_Pin Deletes “all” the defined clocks. -All applies within the givendefaults.

primary_pin… Deletes the primary input pins that were defined as clocks andspecified in this list.

-Golden Deletes the clock(s) from the Golden design. This is thedefault.

-Revised Deletes the clock(s) from the Revised design.





RESOLVE



DELETE COMPARED POINTSDELete COmpared Points

< -All |<<gate_id | instance_pathname* | pin_pathname*>…[-Golden |-Revised]>

>(LEC Mode)

Deletes compared points originally added with the ADD COMPARED POINTS command. If thecompared point is deleted from the Golden design, Conformal also deletes its mappedcompared point from the Revised design. Alternately, if the compared point is deleted fromthe Revised design, Conformal also deletes its mapped compared point from the Goldendesign.

Use the REPORT COMPARED POINTS command to display a list of all added comparedpoints.

Wildcard: The wildcard (*) represents any zero or more characters in instance and pin paths.

Parameters

Related Commands

ADD COMPARED POINTS

COMPARE

-All Deletes “all” compare points. -All applies within the givendefaults.

gate_id… Deletes the specified gates as compare points.


instance_pathname*…

Deletes the specified instance paths as compare points.

pin_pathname*… Deletes the specified pin paths as compare points.

-Golden Deletes the compare points from the Golden design. This isthe default.

-Revised Deletes the compare points from the Revised design.



DELETE CUT POINTDELete CUt Point

<-All | pathname…>[-Net | -Pin][-Golden | -Revised | -Both](Setup Mode)

Deletes cut points originally added with the ADD CUT POINT command.

Use the REPORT CUT POINT command to display a list of all added cut points.

Parameters

Related Commands

ADD CUT POINT

REPORT CUT POINT

REPORT PATH

-All Deletes “all” cut points. -All applies within the given defaults.

pathname… Deletes cut points from the specified paths.

-Net Specifies that the named path is a net. This is the default.

-Pin Specifies that the named path is a pin.

-Golden Deletes the cut points from the Golden design. This is thedefault.

-Revised Deletes the cut points from the Revised design.

-Both Deletes the cut points from both the Golden and Reviseddesigns.



DELETE DYNAMIC CONSTRAINTSDELete DYnamic Constraints

<-All | identifier…>[-INStance | -Pin | -Net | -ID][-Golden | -Revised | -Both](LEC Mode)

Deletes dynamic constraints originally added with the ADD DYNAMIC CONSTRAINTScommand.

Use the REPORT DYNAMIC CONSTRAINTS command to display a list of all added dynamicconstraints.

Parameters

-All Deletes “all” dynamic constraints. -All applies within the givendefaults.

identifier… Deletes dynamic constraints from the specified identifier. If youdo not specify one of the following options, Conformalautomatically determines if the identifier is a number or a path.In the case of a number, Conformal uses the -id option;otherwise, Conformal searches for the gate with the-instance, -pin, or -net option; in this respective order.

-INStance Specifies the hierarchical instance pathThis is the default.

-Pin Specifies the pin path, which is the moduleinstance name concatenated with the pinname.

-Net Specifies the net path, which is the instancename concatenated with the net name.

-ID Specifies the identification number (ID) of agate.





Related Commands

ADD DYNAMIC CONSTRAINTS

PROVE


-Golden Deletes dynamic constraints from the Golden design. This isthe default.

-Revised Deletes dynamic constraints from the Revised design.

-Both Deletes dynamic constraints from both the Golden and Reviseddesigns.



DELETE ECO CELLDELete ECo Cell

[-FReedcell <cell_name*>][-SParecell <cell_name*>][-ALL](Setup Mode)

Deletes the spare cells or freed cells from the available cells for the MAP ECO PATCHcommand.

Parameters

Related Commands

ADD ECO CELL

MAP ECO PATCH

REPORT ECO CELL

-FReedcell Specifies the name(s) of the freed cell(s) to be deleted. Thissupports wildcards.

-SParecell Specifies the name(s) of the spare cell(s) to be deleted. Thissupports wildcards.

-ALL Deletes all the cells.



DELETE ECO PATCHDELete ECo PAtch

[-ALL| <module_under_ECO_name> [<patch_module_name>] ](Setup Mode)

Deletes the ECO patch from the module list to be mapped by the MAP ECO PATCH command.

Parameters

Related Commands

ADD ECO PATCH

MAP ECO PATCH

REPORT ECO PATCH

-ALL Deletes all the added ECO patches.


Specifies the name of the module to delete

<patch_module_name> Specifies the name of the patch module that contains the ECOchanges.



DELETE ECO PINDELete ECo PIn

<module_name><pin_name> | <bus_name> ...[-Golden | -Revised][-REPort <filename>](Setup Mode)

Deletes the pins from the module that were added with the ADD ECO PIN command.

Parameters

Related Commands

ADD ECO PIN

MAP ECO PATCH

<module_name> Specifies the name of the module.

<pin_name> Specifies the name of the pin(s).

<bus_name> Specifies the name of the bus(es).

Note: You cannot delete only partial bits. For example, if thereis a bus port OUT[1:0], the command should be:

delete eco pin top OUT

not

delete eco pin top OUT[1:0]



-REPort <filename> Specifies the name of the report.



DELETE IGNORE RTLCHECKDELete IGnore Rtlcheck

<-All | -Module <name*…>>(Setup Mode)

Re-enables RTL (HDL) rule checking for all or specified modules. By default, rule checking isenabled. Thus, you will only use the DELETE IGNORE RTLCHECK command to reverse theeffects of the ADD IGNORE RTLCHECK command.

Refer to the Encounter Conformal Equivalence Checking User Guide for additionalinformation about specific rules.

Note: If you enter multiple IGNORE RTLCHECK commands, later commands replaceprevious commands. In the following example, Conformal enables RTL rule checking for allmodules, including module abc.

add ignore rtlcheck -module abc

delete ignore rtlcheck -all

Parameters

Related Commands

ADD IGNORE RTLCHECK

REPORT RULE CHECK

-All Enables RTL rule checking for all modules.

-Module* name… Enables RTL rule checking for the specified modules.



DELETE IGNORED INPUTSDELete IGnored Inputs

<-ALL_Pin | primary_pin*…>[-ROot |-Module <name> | -ALL_Module][-Golden | -REvised | -Both](Setup Mode)

Deletes input pins originally added as ignored inputs in the Golden or Revised design withthe ADD IGNORED INPUTS command.

Use the REPORT IGNORED INPUTS command to display a list of all added ignored input pins.

Wildcard: The wildcard (*) represents any zero or more characters in ignored input names.

Parameters

Related Commands

ADD IGNORED INPUTS

REPORT IGNORED INPUTS

-ALL_Pin Deletes “all” previously added ignored inputs within the givendefaults.

primary_pin*… Deletes the specified pins as ignored inputs. The wildcard (*) isaccepted.

-ROot Deletes the ignored inputs in the root module. This is thedefault.

-Module name Deletes the ignored inputs from the specified module.

-ALL_Module Deletes the ignored inputs from all of the modules, including theroot module.

-Golden Deletes the specified ignored inputs from the Golden design.This is the default.

-REvised Deletes the specified ignored inputs from the Revised design.

-Both Deletes the specified ignored inputs from both the Golden andRevised designs.



DELETE IGNORED OUTPUTSDELete IGnored Outputs

<-ALL_Pin | primary_pin*…>[-ROot | -Module <name> | -ALL_Module][-Golden | -REvised | -Both](Setup Mode)

Deletes output or I/O pins originally added as ignored outputs with the ADD IGNOREDOUTPUTS command.

Use the REPORT IGNORED OUTPUTS command to display a list of all added ignored outputor I/O pins.

Wildcard: The wildcard (*) represents any zero or more characters in ignored output names.

Parameters

Related Commands

ADD IGNORED OUTPUTS

REPORT IGNORED OUTPUTS

-ALL_Pin Deletes “all” added ignored outputs.


primary_pin*… Deletes the specified pins as ignored outputs.


-ROot Deletes the ignored outputs in the root module. This is thedefault.

-Module name Deletes the ignored outputs from the specified module.

-ALL_Module Deletes the ignored outputs from all modules, including the rootmodule.

-Golden Deletes the specified ignored outputs from the Golden design.This is the default.

-REvised Deletes the specified ignored outputs from the Revised design.

-Both Deletes the specified ignored outputs from both the Golden andRevised designs.



DELETE INSTANCE ATTRIBUTEDELete INstance Attribute

<module_name> <instance_name> <WEAK>[-Golden | -Revised](Setup Mode)

Deletes instance attributes originally added with the ADD INSTANCE ATTRIBUTE command.

Use the REPORT INSTANCE ATTRIBUTE command to display a list of all added instanceattributes.

Parameters

Related Commands

ADD INSTANCE ATTRIBUTE

REPORT INSTANCE ATTRIBUTE

module_name Deletes the instance attribute from the specified module.

instance_name Deletes the instance attribute from the specified instance.

WEAK Specifies drive strength.

Note: This option applies to Conformal Custom.

-Golden Deletes the instance attribute from the Golden design. This isthe default.

-Revised Deletes the instance attribute from the Revised design.



DELETE INSTANCE CONSTRAINTSDELete INstance Constraints

<<name…> [-Module name*] | -All>[-Golden | -Revised | -BOTH](Setup Mode)

Deletes instance constraints originally added with the ADD INSTANCE CONSTRAINTScommand.

Use the REPORT INSTANCE CONSTRAINTS command to display a list of all added instanceconstraints.

Parameters

Related Commands

ADD INSTANCE CONSTRAINTS

REPORT INSTANCE CONSTRAINTS

name… Deletes constraints on the specified instance paths.

Note: The names are either DFFs or D-latches.

-Module name* Deletes the constraints from the specified module(s). Thewildcard (*) is supported.

-All Deletes “all” instance constraints. -All applies within the givendefaults.

-Golden Deletes instance constraints in the Golden design. This is thedefault.

-Revised Deletes instance constraints in the Revised design.

-BOTH Deletes instance constraints in both the Golden and Reviseddesigns.



DELETE INSTANCE EQUIVALENCESDELete INstance Equivalences

<instance_pathname…| -All>[-Golden | -Revised](Setup Mode)

Deletes instance equivalences originally added with the ADD INSTANCE EQUIVALENCEScommand.

Use the REPORT INSTANCE EQUIVALENCES command to display a list of all added instanceequivalences.

Parameters

Related Commands

ADD INSTANCE EQUIVALENCES

REPORT INSTANCE EQUIVALENCES

instance_pathname… Deletes equivalences on the specified instance paths.

-All Deletes “all” instance equivalences. -All applies within thegiven defaults.

-Golden Deletes instance equivalences in the Golden design. This isthe default.

-Revised Deletes instance equivalences in the Revised design.



DELETE LOWPOWER CELLSDELete LOwpower Cells

<module_name* | -All>[-Both | -Golden | -Revised](Setup Mode)

Deletes low power cells that were originally defined for modules with the ADD LOWPOWERCELLS command.

Use the REPORT LOWPOWER CELLS command to display a list of the low power cells usedin the design.

Parameters

Related Commands

ADD LOWPOWER CELLS




SET LOWPOWER OPTION

module_name Deletes previously added low power cells from the specifiedmodules. This supports wildcards.

-ALL Deletes previously added low power cells from “all” modules.“All” applies within the given defaults.

-Both Deletes the low power cells in the Golden and Revised designs.This is the default.

-Golden Deletes the low power cells in the Golden design.

-Revised Deletes the low power cells in the Revised design.



DELETE MAPPED POINTSDELete MApped Points

<-All [-Class <Full | User | System>]|<<gate_id | instance_pathname* | pin_pathname*>…[-Golden | -Revised]>|[-NONEQ]|[-UNREACH]

>(LEC Mode)

Deletes mapped points that were one of the following:

■ Automatically identified

■ Added with the ADD MAPPED POINTS command.

Additionally, Conformal deletes all compared points associated with the added mappedpoints.

Use the REPORT MAPPED POINTS command to display a list of all mapped points in the Userand System classes of the Golden and Revised designs.

Wildcard: The wildcard (*) represents any zero or more characters in instance or pin pathsof mapped points.

Parameters

-All Deletes “all” mapped points. -All applies within the givendefaults.

-Class Deletes the specified class of mapped points.

Full The Full class includes mapped points from boththe User and System classes. This is thedefault.

User The User class includes mapped points that werepreviously added with the ADD MAPPED POINTScommand.

System The System class includes mapped points thatwere automatically identified when Conformalexited the Setup system mode or were mappedwith the MAP KEY POINTS command.



Related Commands

ADD MAPPED POINTS

MAP KEY POINTS



SET MAPPING METHOD

SET NAMING RULE

gate_id… Deletes mapped points with these gate ID numbers.

ID numbers can differ from one version of Conformal to another.Always use the full path in dofiles and any time you rerun adesign with a different Conformal version.


instance_pathname*… Deletes mapped points from the specified instance paths.

pin_pathname*… Deletes mapped points from the specified pin paths.

-Golden Delete the mapped points from the Golden design. This is thedefault.

-Revised Deletes the mapped points from the Revised design.

-NONEQ Deletes all non-equivalent mapped points.

-UNREACH Deletes all unreachable mapped points. An unreachablemapped point is one where both the Golden and Revised keypoints are unreachable.

If the key point is the representative of the equivalence group orsequential merge group, it is considered unreachable only if allthe member key points in the group are unreachable.



DELETE MODULE ATTRIBUTEDELete MOdule Attribute

<module_name… | -All><-PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit >[-Golden | -Revised](Setup Mode)

Deletes attributes originally assigned to modules with the ADD MODULE ATTRIBUTEcommand.

Use the REPORT MODULE ATTRIBUTE command to display a list of all added moduleattributes.

Parameters

Related Commands




module_name… Deletes previously added attributes from the specified modules.

-ALL Deletes previously added attributes from “all” modules withinthe given defaults.

-PIPELINE_Retime Deletes attributes previously added for pipeline-retiming.

-COMPARE_Effort Deletes compare effort levels previously added to modules.

-CPU_Limit Deletes the CPU time limit imposed with the ADD MODULEATTRIBUTE command.

-Golden Deletes the specified module attributes in the Golden design.This is the default.

-Revised Deletes the specified module attributes in the Revised design.



DELETE MOS DIRECTIONDELete MOs Direction

<module_name> <instance_name>[-Golden | -Revised](Setup Mode)


Deletes the unidirection that was placed on transistor-MOS instances with the ADD MOSDIRECTION command.

Use the REPORT MOS DIRECTION command to display a list of all transistor-MOS directioninstances.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE


DELETE CLOCK


READ PATTERN

REPORT CLOCK

module_name Deletes MOS direction for the specified module.

instance_name Deletes MOS direction for the specified instance.

-Golden Deletes MOS direction from the Golden design. This is thedefault.

-Revised Deletes MOS direction from the Revised design.






RESOLVE



DELETE NET ATTRIBUTEDELete NEt Attribute

<-ALL_Net | net_name>[-ROot | -Module <name> | -ALL_Module][-Golden | -Revised | -Both](Setup Mode)


Deletes attributes that were placed on transistor-MOS nets with the ADD NET ATTRIBUTEcommand.

Use the REPORT NET ATTRIBUTE command to display a list of all attributes placed ontransistor-MOS nets.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

-ALL_Net Deletes “all” net attributes within the given defaults.

net_name Deletes the specified transistor-MOS net attributes.

-ROot Deletes net attributes associated with the root module, whichcontains the transistor-MOS. This is the default.

-Module name Deletes net attributes associated with the specified module,which contains the transistor-MOS.

-ALL_Module Deletes a specified net attribute for all modules, or delete all netattributes for all modules. (Refer to -all_net and-net_name to understand the two choices.)

-Golden Deletes net attributes from the Golden design. This is thedefault.

-Revised Deletes net attributes from the Revised design.

-Both Deletes net attributes from both the Golden and Reviseddesigns.



ADD MOS DIRECTION

ADD NET ATTRIBUTE


DELETE CLOCK


READ PATTERN

REPORT CLOCK




RESOLVE



DELETE NET CONSTRAINTSDELete NEt Constraints

[-Golden | -Revised | -Both](Setup Mode)

Deletes either the Golden or Revised design net constraints originally added with the ADDNET CONSTRAINTS command.

Use the REPORT NET CONSTRAINTS command to display a list of all added net constraints.

Parameters

Related Commands

ADD NET CONSTRAINTS

REPORT NET CONSTRAINTS

-Golden Deletes net constraints from the Golden design. This is thedefault.

-Revised Deletes net constraints from the Revised design.

-Both Deletes net constraints from both the Golden and Reviseddesigns.



DELETE NOBLACK BOXDELete NOblack Box

<module_name*… | -All>[-Golden | -Revised | -Both](Setup Mode)

Deletes the specified module names originally added with the ADD NOBLACK BOX command.

Use the REPORT NOBLACK BOX command to display a list of all of the modules that will beresolved (flattened) to their parents’ modules during hierarchical dofile script generation.


Parameters

Related Commands

ADD NOBLACK BOX

REPORT NOBLACK BOX


module_name*… Deletes the previously added noblackbox modules.

-All Deletes “all” previously added noblackboxes. -All applieswithin the given defaults.

-Golden Deletes the specified Golden module names. This is thedefault.

-Revised Deletes the specified Revised module names.

-Both Deletes all of the specified modules from both the Golden andRevised designs.



DELETE NOTRANSLATE FILEPATHNAMESADD NOtranslate Filepathnames

<filepath_names*… | -All>[ | -Library | -Design][-Both | -Golden | -Revised](Setup Mode)

Deletes the specified file pathnames originally added with the ADD NOTRANSLATEFILEPATHNAMES command.

Use the REPORT NOTRANSLATE FILEPATHNAMES command to display a list of all of thelibrary and design file pathnames.


Parameters

Related Commands

ADD NOTRANSLATE FILEPATHNAMES


REPORT NOTRANSLATE FILEPATHNAMES


filepath_name*… Deletes the listed notranslate file pathnames.

-All Deletes “all” previously added notranslate file pathnames.-All applies within the given defaults.

-Library Deletes the specified library file pathnames. This is thedefault.

-Design Deletes the specified design file pathnames.

-Both Deletes the specified file pathnames from both the Goldenand Revised designs. This is the default.

-Golden Deletes the specified Golden file pathnames.

-Revised Deletes the specified Revised file pathnames.



DELETE NOTRANSLATE MODULESDELete NOtranslate Modules

<module_name*… | -All>[-Library | -Design][-Both | -Golden | -Revised](Setup Mode)

Deletes the specified module names originally added with the ADD NOTRANSLATE MODULEScommand.

Use the REPORT NOTRANSLATE MODULES command to display a list of all of the library anddesign module names that will not be compiled.


Parameters

Related Commands


READ DESIGN

READ LIBRARY


module_name*… Deletes the listed modules.

-All Deletes “all” previously added notranslate module names. -Allapplies within the given defaults.

-Library Deletes the specified library module names. This is thedefault.

-Design Deletes the specified design module names.

-Both Deletes the specified modules from both the Golden andRevised designs. This is the default.

-Golden Deletes the specified Golden module names.

-Revised Deletes the specified Revised module names.



DELETE OUTPUT EQUIVALENCESDELete OUtput Equivalences

<-ALL_Pin | primary_pin*…>[-ROot | -Module <name> | -ALL_Module][-Golden | -Revised | -Both](Setup Mode)

Deletes the output pin equivalences placed on output boundary module pins with the ADDOUTPUT EQUIVALENCES command.

Use the REPORT OUTPUT EQUIVALENCES command to display a list of all added output pinequivalences.

Wildcard: The wildcard (*) represents any zero or more characters in output boundarymodule pin names.

Parameters

Related Commands



-ALL_Pin Deletes “all” output pin equivalences within the given defaults.

primary_pin*… Deletes output pin equivalences from the listed outputboundary module pins.

-ROot Deletes the output pin equivalences from the root module.

-Module name Deletes the output pin equivalences from the specified module.

-ALL_Module Deletes the output pin equivalences from all modules.

-Golden Deletes the specified output pin equivalences in the Goldendesign. This is the default.

-Revised Deletes the specified output pin equivalences in the Reviseddesign.

-Both Deletes the specified output pin equivalences in both theGolden and Revised designs.



DELETE OUTPUT STUCK_ATDELete OUtput Stuck_at

<-ALL_Pin | primary_pin…>[-Module <name>][-Golden |-Revised]

Deletes the output stuck_at values placed on output boundary module pins with the ADDOUTPUT STUCK_AT command.

Use the REPORT OUTPUT STUCK_AT command to display a list of all added outputstuck_at values and their pin names.

Parameters

Related Commands

ADD OUTPUT STUCK_AT

REPORT OUTPUT STUCK_AT

-ALL_Pin Deletes “all” output stuck_at values within the given defaults.

primary_pin… Deletes the output stuck_at values associated with the listedoutput boundary module pins.

-Module name Deletes the output stuck_at values in the specified module.

-Golden Deletes the output stuck_at values in the Golden design.This is the default.

-Revised Deletes the output stuck_at values in the Revised design.



DELETE PARTITION KEY_POINTDELete PArtition Key_point

(Setup Mode)

Deletes all of the specified partition key points originally added with the ADD PARTITIONKEY_POINT command.

Use the REPORT PARTITION KEY_POINT command to display a list of all added partitionkey points.

Related Commands

ADD PARTITION KEY_POINT





DELETE PARTITION POINTSDELete PARtition Points

<pathname | -All | -BAD_cuts [-EFFORT <Low | Medium | High]>[-NONequivalent][-Golden | -Revised][-NOVerbose | -Verbose](LEC Mode)


Deletes the partition points that were created with the ADD PARTITION POINTS command.

Note: Partition points are always deleted in pairs.

Tip

You can get the pathname of the partition point with the REPORT PARTITIONPOINT command.

Caution

Deleting partition (CUT) points in LEC mode causes flattened netlists tochange. As a result, all the gate-ids are subjected to change. Deleting cutpoints does not affect the existing compare points list; however, all thecompare data is invalidated after deleting cut points.

Parameters

pathname Specifies the name of the path for the partition points to bedeleted.

-All Specifies that all the existing partition points will be deleted.

-BAD_cuts Automatically deletes the bad set of partition points causingfalse non-equivalence.

-EFFORT <Low | Medium | High>



Related Commands

ADD PARTITION POINTS

REPORT PARTITION POINTS

Specifies the effort level for deleting the bad set of partitionpoints.

Increasing the effort level from Low to High will intelligentlydelete more partition points decreasing the probability of falsenon-equivalence. However, increasing the effort will result inincreased time as well.

The default effort level is Low.

-NONequivalent Deletes partition cut points that caused false non-equivalentpoints.

-Golden Specifies that the partition point is in the Golden design. This isthe default.

-Revised Specifies that the partition point is in the revised design.

-NOVerbose Does not provide additional information. This is the default.




DELETE PIN CONSTRAINTSDELete PIn Constraints

<-ALL_Pin | primary_pin*…>[-Module <name>][-Golden | -Revised | -Both](Setup Mode)

Deletes constraints originally placed on named primary input pins with the ADD PINCONSTRAINTS command.

Use the REPORT PIN CONSTRAINTS command to display a list of all added pin constraints.

Wildcard: The wildcard (*) represents any zero or more characters in primary input names.

Parameters

Related Commands

ADD PIN CONSTRAINTS

REPORT PIN CONSTRAINTS

-ALL_Pin Deletes “all” constraints placed on primary input pins within thegiven defaults.

primary_pin*… Deletes constraints from the listed primary inputs.

-Module name Deletes pin constraints from the specified module.

-Golden Deletes the specified pin constraints from the Golden design.This is the default.

-Revised Deletes the specified pin constraints from the Revised design.

-Both Deletes the specified pin constraints from both the Golden andRevised designs.



DELETE PIN EQUIVALENCESDELete PIn Equivalences

<-ALL_Pin | primary_pin*…>[-ROot | -Module <name> | -ALL_Module][-Golden | -REvised | -Both](Setup Mode)

Deletes the added pin equivalences from the specified primary input pins. Theseequivalences were placed on primary input pins with the ADD PIN EQUIVALENCE command.

Use the REPORT PIN EQUIVALENCES command to display a list of all of the added pinequivalences.

Wildcard: The wildcard (*) represents any zero or more characters in primary input names.

Parameters

Related Commands

ADD PIN EQUIVALENCES

REPORT PIN EQUIVALENCES

-ALL_Pin Deletes “all” added pin equivalences within the given defaults.

primary_pin*… Deletes pin equivalences from the listed primary input pins. (Pinequivalence was originally added with the ADD PINEQUIVALENCE command.)

-ROot Deletes pin equivalences from the root module.

-Module name Deletes pin equivalences from the specified module.

-ALL_Module Deletes pin equivalences from all modules.

-Golden Deletes the specified pin equivalences from the Golden design.This is the default.

-REvised Deletes the specified pin equivalences from the Reviseddesign.

-Both Deletes the specified pin equivalences from both the Goldenand Revised designs.



DELETE PRIMARY INPUTSDELete PRimary Inputs

<-All | pathname*…>[-Golden | -Revised | -Both](Setup Mode)

Deletes specified primary inputs that were originally added with the ADD PRIMARY INPUTcommand. After you delete the primary input pins from either the Golden or Revised design,the associated nets become floating nets, unless there are other net drivers.

Use the REPORT PRIMARY INPUTS command to display a list of all primary inputs.

Wildcard: The wildcard (*) represents any zero or more characters in paths of primaryinputs.

Parameters

Related Commands

ADD PRIMARY INPUT

REPORT PRIMARY INPUTS

-All Deletes “all” primary inputs within the given defaults.

pathname*… Deletes the specified primary inputs.

-Golden Deletes the specified primary inputs from the Golden design.This is the default.

-Revised Deletes the specified primary inputs from the Revised design.

-Both Deletes the specified primary inputs from both the Golden andRevised designs.



DELETE PRIMARY OUTPUTSDELete PRimary Outputs

<-All | pathname*…>[-Golden | -Revised | -Both](Setup Mode)

Deletes primary outputs that were originally added with the ADD PRIMARY OUTPUTcommand. When you delete the primary output pins from the Golden or Revised design, thenets become floating nets, unless there are other net drivers.

Use the REPORT PRIMARY OUTPUTS command to display a list of all primary outputs.

Wildcard: The wildcard (*) represents any zero or more characters in paths of primaryoutputs.

Parameters

Related Commands

ADD PRIMARY OUTPUT

REPORT PRIMARY OUTPUTS

-All Deletes “all” primary outputs within the given defaults.

pathname*… Deletes the specified primary outputs.

-Golden Deletes primary outputs from the Golden design. This is thedefault.

-Revised Deletes primary outputs from the Revised design.

-Both Deletes primary outputs from both the Golden and Reviseddesigns.



DELETE RENAMING RULEDELete REnaming Rule

<-All | <rule_name>>[-MAp | -MOdule | -PIn](Setup / LEC Mode)

Deletes renaming rules originally added with the ADD RENAMING RULE command.

Use the REPORT RENAMING RULE command to display a list of all of the renaming rules andtheir rule numbers.

Parameters

Related Commands

ADD RENAMING RULE

CHANGE NAME

MAP KEY POINTS

READ DESIGN

READ LIBRARY

-All Deletes all previously added renaming rules in one of thefollowing three categories:

■ Map

■ Module

■ Pin

If you do not specify a category, Conformal deletes allpreviously added renaming rules from the Map category.

rule_name Deletes the specified renaming rule.

-MAp Deletes map renaming rules. This is the default.

-MOdule Deletes module renaming rules.

-PIn Deletes pin renaming rules.




SET MAPPING METHOD

SET NAMING RULE

TEST RENAMING RULE



DELETE RETENTION MAPPINGDELete REtention Mapping

<-All | <rule_name>>(Setup / LEC Mode)


Deletes the state retention mapping rules added using the ADD REtention_registerMapping command.

Note: Use the REPORT RETENTION MAPPING command to display a list of all the stateretention mapping rules. Note that the default rule added by the system can never be deleted.


Parameters

Related Commands


REPORT RETENTION MAPPING

-All Deletes all the state retention register mapping rules addedusing the ADD RETENTION MAPPING Mapping command.

This option does not delete the default rule added by thesystem.

rule_name Deletes the specified state retention mapping rule.

Note: The default rule added by the system cannot be deleted.



DELETE SEARCH PATHDELete SEarch Path

<-All | pathname…>[-Design | -Library][-Golden | -Revised](Setup Mode)

Deletes search paths Conformal uses for the READ DESIGN and READ LIBRARY commands.

Use the REPORT SEARCH PATH command to display a list of all search paths.

Parameters

Related Commands

ADD SEARCH PATH

READ DESIGN

READ LIBRARY

REPORT SEARCH PATH

-All Deletes “all” previously added search paths within the givendefaults.

pathname… Deletes the specified search paths.

-Design Deletes search paths used by the READ DESIGN command.This is the default.

-Library Deletes search paths used by the READ LIBRARY command.

-Golden Deletes search paths used by the Golden design or library.This is the default.

-Revised Deletes search paths used by the Revised design or library.



DELETE TIED SIGNALSDELete TIed Signals

<-All | name…>[-Net |-Pin][-Module <name>][-Class <Full | User | System>][-Golden |-Revised](Setup Mode)

Deletes specified tied signals from the Golden or Revised design.

Use the REPORT TIED SIGNALS command to display a list of all of the tied signals.

Parameters

Related Commands

ADD TIED SIGNALS

-All Deletes “all” tied signals within the given defaults.

name… Deletes the specified tied signals.

-Net Specifies that the deleted tied signal is a net. This is thedefault.

-Pin Specifies that the deleted tied signal is a pin.

-Module name Specifies the name of the module where the floating net or pinresides.

-Class Deletes tied signals of this class.

Full Tied signals from both the User and Systemclasses. This is the default.

User Tied signals the user previously added withthe ADD TIED SIGNALS command.

System Tied signals from the original design.

-Golden Deletes tied signals from the Golden design. This is thedefault.

-Revised Deletes tied signals from the Revised design.



REPORT TIED SIGNALS



DIAGNOSEDIAgnose

< < gate_id | instance_pathname | pin_pathname>[-Golden |-Revised][-SUPport][-NUm <integer>]| -SUMmary [integer][-SOrt <SUpport | SIze>]|[-NOneq]>(LEC Mode)

Performs diagnosis on a specified compared point. Specify the compared point by its gateidentification number, instance path, or a pin path. Use this command to determine why thesoftware identified non-equivalence between compared points.

The diagnosis displays all of the non-corresponding support key points with a list of all likelyerror candidates from the Revised design. The list organizes likelihood in descending orderwith 1.00 being the greatest possible error candidate.

Use the REPORT ENVIRONMENT command to display the maximum diagnosis candidatessetting.

Parameters

gate_id Diagnoses the specified gate.


instance_pathname Diagnoses the specified instance path.

pin_pathname Diagnoses the specified pin path.

-Golden Diagnoses the Golden design. This is the default.

-Revised Diagnoses the Revised design.

-SUPport Displays the list of corresponding and non-correspondingsupport points.

-NUm integer Lists the specified number of error candidates. By default,Conformal lists all error candidates.



Examples


Related Commands

PROVE

REPORT COMPARE DATA

REPORT ENVIRONMENT

REPORT TEST VECTOR

-SUMmary integer Displays a table of the non-equivalent points with theircorresponding support size, non-corresponding support size,and cone size.

The integer represents the number of nonequivalent points youwish to display in the table. By default, Conformal displaysall nonequivalent points.

-SOrt Sorts the summary table results by one of the following.

SUpport Sorts by corresponding support size

This is the default.

SIze Sorts by cone size

-NOneq Diagnoses every nonequivalent point.



DOFILEDOFile

< <filename> [-FORCE] | -SHOW_STACK>(Setup / LEC Mode)

Executes a set of commands contained in a specified file. If there is an error while theConformal software is executing the dofile script, it terminates the dofile execution and returnsto the system mode prompt.

Use the SET DOFILE ABORT command to specify how you want the Conformal software torespond when an error message occurs. You can choose to terminate, continue, or exit thesession.

Use the BREAK command in a dofile script to terminate the dofile script and return to thesystem mode prompt.

Parameters

Related Commands

BREAK

CONTINUE

SET DOFILE ABORT

filename Specifies a file containing a set of commands the Conformalsoftware executes one at a time.

-FORCE Allows a dofile to be executed multiple times, up to a limit of 16.Without this option, you will get an error if you attempt to run adofile multiple times.

-SHOW_STACK Specifies that if the current execution is stopped because of abreak in one or more dofiles, it will display the current dofileexecution stack. For example:

1: dofile_2

break (line:2)

2: dofile_1

dofile dofile_2 (line:5)



ELABORATE DESIGNELAborate DEsign

[-ROot <module_name>][-ROOTConfig <configuration_name>][-PARAmeter [-INT | -STR | -ENUM] <name> <value>][-RAngeconstraint][-GOlden | -REvised](Setup Mode)

Completes the READ DESIGN command specified with the -noelaborate option. Duringthis step, modules are synthesized and the complete design hierarchy is created.

This command is typically used for mixed design flows where the Verilog modules and VHDLentity or architectures are read in separately. Then they can be elaborated using thiscommand.

Parameters

-ROot <module_name> Specifies the root module to be elaborated. If this option is notspecified, the Conformal software automatically select a rootmodule.

-ROOTConfig <configuration_name>

Specifies that the design includes the specified configuration forthe top-level module.

Note: This option applies to only VHDL designs.

Use this option when the design includes multipleconfigurations for the top-level module. When you use the-rootconfig option, you must also use the -rootmodule_name option (above).



-PARAmeter [-INT | -STR | -ENUM] <name> <value>

Assigns design parameters or replace existing designparameters. To specify multiple parameters, use the-parameter option for each parameter you want to set. Forexample:

read design filename -parameter parm1 value1 \-parameter -int parm2 value2

This option applies to both Verilog and VHDL files. (Combinewith -root.)

When using the -parameter -int <name> <value>command, the <value> will be converted to integer value,which can be a positive integer (1), negative integer (-1), aninteger value recognized as a string ("1"/"-1"), or a Verilogstyle integer ("16’h0001"). When using a Verilog style integer,the value must be specified between double-quotes (" ").

When using the -parameter -str <name> <value>command, the <value> will be saved as a string.

When using the -parameter -enum <name> <value>command, the <value> will be converted to a VHDLenumeration literal. For example, the following command setsthe parameter P4 to VHDL enumeration literal GREEN:

read design -root mod1 filename \-parameter -enum P4 GREEN

Note: Any value that is not recognized as an unsigned decimalinteger value is interpreted as string value.

Note: If -int or -str is not specified, then the parameter valuewill be interpreted as an integer if it is not betweendouble-quotes (" "), and as a string if it is betweendouble-quotes. Therefore, if you want to specify a Verilog formatvalue, it must be between double-quotes and used with the -intoption.

-RAngeconstraint Applies range constraints during verification. If this option is notspecified, all range constraints are ignored.

-Golden Specifies to elaborate the Golden design. This is the default.

-Revised Specifies to elaborate the Revised design.



Related Commands

READ DESIGN

READ LIBRARY



EXITEXIt

[-Force](Setup / LEC Mode)

Ends the existing Conformal session and returns you to the operating system.

Exit Status Codes

On exiting, Conformal returns a status code. A nonzero status code means there is a potentialerror; that is, either no comparison was done or unmapped, abort, or nonequivalent pointsexist. The exit status code consists of flags that represent different conditions.

Saving GUI Settings

By default, Conformal does not automatically save GUI settings for future sessions. To saveyour preferred settings, use the GUI exit window and click the Save GUI settings check box.

Refer to the Encounter Conformal Equivalence Checking User Guide for additionalinformation about exit status codes and the procedure to save GUI settings.

Parameters

-Force Exits without confirmation.



FLATTENFLAtten

<-MODule <name> | -ALL>[-Force | -NOForce][-Golden | -Revised](Setup Mode)


Removes all hierarchy on a specified module or for all modules in the database. If you do notspecify one or all modules, Conformal flattens the root module by default. Thus, thiscommand expands all of the gate primitive or transistor primitive devices into the cell that isbeing flattened.

The following example illustrates the effects of this command:

A cell that is to be flattened contains three cells. One cell has 25 gates and the other two arethe same, each with 33 gates. After flattening, the cell now contains 0 cells and 91 gates (1 *25 + 2 * 33 = 91).

Parameters

Related Command

RESOLVE

-MODule name Flattens the specified module. The default is to flatten theroot module.

-ALL Flattens “all” modules within the given defaults.

-Force Forces flattening of specified modules in the Golden or Reviseddesign even if those modules have not been flattened in thecomplementing design. (For example, force flattening forGolden modules when the Revised have not been flattened.)This is the default.

-NOForce Does not force flattening when those modules have not beenflattened in the complementing design.

-Golden Flattens the specified module(s) from the Golden design. Thisis the default.

-Revised Flattens the specified module(s) from the Revised design.



FORWARDFORward

[integer](LEC Mode)

Reports fan-out gate information from the currently displayed flatten gate information. Thefan-out gate you choose with this command becomes the current flattened gate. Use thiscommand to trace gates in place of repeatedly using the REPORT GATE command.

Note: This command does not report gates at the design level.

Parameters

Related Commands

BACKWARD

REPORT GATE

integer Reports the specified fan-out gate. The value 1 denotes the firstfan-out. The default is 1.



GENERATE ROM PRIMITIVEGENerate ROm Primitive

<-SIM <outfile>><-CODE_FILE <codefilename>>[-MOD <modulename>][-CODE_FILE_FORMAT [BIN | HEX]][-NO_ACCESS_OUT_LOW | -NO_ACCESS_OUT_HIGH](Setup Mode)


Generates a ROM primitive model that you can use to verify against a valid ROM circuit.Conformal generates a ROM primitive that has the following interface:

■ Addr—Address bus for accessing ROM data.

■ Dout—Output data from ROM.

■ RE—Control clock for the output latch or flip-flop, when you set the -outstate option todlat or dff. When RE is high, ROM data is sampled.

■ CK—Address decode clock for ROM read operations. ROM is read when the clock ishigh.

This command reads in a code file that initializes the ROM. This code file should contain onenumber per line, in binary format. The number of entries in the code file should match thenumber of words in the memory. As Conformal reads the code file, it assigns each entry to asuccessive word element in the memory.

The following illustrates sample contents for a code file called rom.code, which initializes a4 X 4 ROM:

0000111110100111

Note: To perform simulation, you must define the macro SIM.

Parameters

-SIM <outfile> Specifies the output file for the ROM primitive.

-CODE_FILE <codefilename>



Related Command

READ ROM PRIMITIVE

Examples

The following command generates a ROM model with a code file called rom.code.

generate rom primitive -sim VROM.v -code_file rom.code -mod VROM /-code_file_format bin -no_access_out_low

Specifies the code file that will initialize the ROM. Thiscode file should contain initialization data in binary format.

-MOD <modulename> Specifies the module name of the ROM primitive that iscreated.

-CODE_FILE_FORMAT [BIN | HEX]

Specifies the output file format for the ROM primitive.

-NO_ACCESS_OUT_LOW Fills the memory address with ’0’ when it is not initialized.This is the default.

-NO_ACCESS_OUT_HIGH Fills the memory address with ’1’ when it is not initialized.



GROUPGROUP

<-Module <name> ><-Instance <instance_name*… > ><-NEWModule <name> ><-NEWInstance <name> >[-net_to_pin_name][-Golden | -Revised](Setup Mode)


Groups defined instances together so that they become a new submodule. This command isthe opposite of the RESOLVE command; it applies to submodules, latches, registers, gates,and transistors. By default, this command assigns unique and arbitrary submodule pinnames.

Wildcard: The wildcard (*) represents any zero or more characters in existing instancenames.

Parameters

Related Command

RESOLVE

-Module name Specifies a module for which to apply the grouping.

-Instance instance_name*…

Specifies the instances to group. This accepts wildcards.

-NEWModule name Specifies the name of the new module.

-NEWInstance name Specifies the instance name for the new module.

-net_to_pin_name Specifies that the pin names of the new modules will be thesame as the nets connected to them, and not unique andarbitrary.

-Golden Applies this command to modules and instances in theGolden design. This is the default.

-Revised Applies this command to modules and instances in theRevised design.



HELPHELp

[<command_name> | <message_name> | -message] [-Verbose][-NOSHOW_ERROR_ID | -SHOW_ERROR_ID][-NOSHOW_EXTENDED_HELP | -SHOW_EXTENDED_HELP][-COLOR | -NOCOLOR][-PAGE | -NOPAGE][<error_id>](Setup / LEC Mode)

Displays the Conformal commands and their command syntax. To display a group or set ofcommands, use a keyword such as ADD, DELETE, REPORT, or SET.

While in the Tcl mode, the HELP command displays a list of all available Conformal Tcl modecommands.

Parameters

<command_name> Displays the command syntax for a given command name. Ifyou do not specify a command name, the ConformalEquivalence Checker displays all of the commands.

<message_name> Displays help for the corresponding rule check message.

-message Displays all rule check messages.

-Verbose Expands information about the command, includingdescriptions of the parameters and related commands.

-NOSHOW_ERROR_ID Does not display the error ID. This is the default.

-SHOW_ERROR_ID Displays the error ID.

-NOSHOW_EXTENDED_HELP

Does not display the extended help. This is the default.

-SHOW_EXTENDED_HELP

Displays the extended help only. This does not include errorIDs.

-COLOR Displays the help text with color highlights. This is the default.

Note: This option has no effect if the terminal is not an ’xterm’,as determined by the environmental variable TERM, or whenrunning HELP in the GUI window.



Example

The following is an example of the Tcl mode system prompt and the HELP command:

TCL_SETUP> help set_current_module

Related Command

SEARCH

-NOCOLOR Disables the help text with color highlight display. Use this if thetext terminal does not support color.

-PAGE Displays the help text one screenful at a time. This is thedefault. The output is paused for input after one screenful oftext is displayed, where you can continue by pressing thefollowing:

■ spacebar—displays the next page

■ h-key—displays a complete list of options

■ q-key—quits from the pager

Note: Output displayed with the pager is not saved to the log filespecified by SET LOG FILE command.

Note: The pager is not enabled if the help text is less than ascreenful, when output is redirected to a file, or when runningHELP in the GUI window.

-NOPAGE Disables the help text paging display feature.

<error_id> Displays the error message of the specified message ID.



INVERT MAPPED POINTSINVert MApped Points

<gate_id | instance_pathname | pin_pathname>…[-Golden |-Revised](LEC Mode)

When switching the system from Setup mode to LEC mode, Conformal automatically mapskey points and places them in the System class of mapped points. Use this command toinvert the mapping phase for any mapped points. This command also places the points in theUser class of mapped points.

In the GUI Mapping Manager and in reports, a (-) sign represents an inverted-mapped point.A (+) sign represents a non-inverted mapped point.

Parameters

Related Commands

ADD MAPPED POINTS


MAP KEY POINTS



gate_id Inverts the mapping phase for the specified gates (identified bynumber).


instance_pathname Inverts the mapping phase for the specified instances.

pin_pathname Inverts the mapping phase for the specified pins.

-Golden Specifies that the point identifier refers to the Golden design.This is the default.

-Revised Specifies that the point identifier refers to the Revised design.



SET MAPPING METHOD

SET NAMING RULE



LICENSELICense

[<license_string>](Setup / LEC Mode)

Displays information about the currently installed Conformal license. By default, thiscommand displays all available Conformal licenses.

Parameters

<license_string> Displays information for a specific license. You can select one ofthe following:

■ conformal_explorer

■ conformal_asic

■ conformal_ultra

■ conformal_custom

■ conformal_low_power

■ conformal_low_power_gxl

■ conformal_eco

■ rtl_compiler_verification



MAP ECO PATCHMAP ECo Patch

<filename>[-NOConstraint][-REPlace](Setup Mode)

Maps the ECO patch(es), specified by the ADD ECO PATCH command, to the available ECOcells.

The available ECO cells are specified by the ADD ECO CELL command. The targettechnology libraries are specified by the ADD ECO LIBRARY command.

Parameters

Related Commands

ADD ECO CELL

ADD ECO LIBRARY

ADD ECO PATCH

OPTIMIZE PATCH

<filename> Specifies the file name for the mapped netlist.

-NOConstraint Specifies that the mapping process will use the cells in the ECOlibrary to implement the patch. Use this option for a pre-maskECO.




MAP KEY POINTSMAP KEy Points

(LEC Mode)

Automatically maps all key points, then displays a summary of the mapped points in theGolden and Revised designs. In addition, if there are any unmapped points, Conformaldisplays a summary of the unmapped points in the Golden and Revised designs. Conformalautomatically executes this command the first time you exit the Setup system mode and whenthe flattened gate model changes.

Related Commands

ADD MAPPED POINTS

ADD RENAMING RULE






SET MAPPING METHOD

SET NAMING RULE

TEST RENAMING RULE



MOS2BUFIFMOS2BUFIF

[-MODule mod1 mod2… modn | -ALL][-FORce | -DRIVENmos | -INStance ins1 ins2… insn][-Golden | -Revised](Setup Mode)


After abstraction for emulation and test support, this transforms all of the unidirectional NMOSdevices to BUFIF1 and unidirectional PMOS devices to BUFIF0.

Parameters

-MODule mod1 mod2… modn

Transforms the specified list of modules.

Note: If you do not specify modules, Conformal transforms thecurrent root module.

-ALL Transforms all modules.

-FORce Converts all [r]nmos to bufif1, [r]pmos to bufif0, [r]cmos to abufif0 – bufif1 pair. This is the default.

-DRIVENmos Converts only those MOS devices that are driven by a logicgate or a primary input.

-INStance ins1 ins2… insn

Transforms the specified instances. You can only use this optionwhen you have specified a single module. (Refer to the-module definition.)

Note: The following options are mutually exclusive. That is, youcan only use one of these options in the command:

■ -force

■ -drivenmos

■ -instance

Conformal issues a warning when the specified instances donot exist or they are not unidirectional.



Example

Sample Netlist Transformation:

The following is the original netlist:

nmos (out, in, ctl) ;

pmos (out, in, ctl) ;

The MOS2BUFIF command transforms the netlist to the following:

bufif1 (out, in, ctl) ;

bufif0 (out, in, ctl) ;

Related Command

ABSTRACT LOGIC

-Golden Applies transformation in the Golden design. This is thedefault.

-Revised Applies transformation in the Revised design.



MOVE INSTANCE DOWNMOVe INstance Down

-MODule <module_name>-From <from_instance>-TO <to_instance_list>[-Golden | -Revised](Setup Mode)

Moves instances in the same parent module.

Parameters

-MODule <module_name>

Specifies the parent module

-From <from_instance>

Specifies the instance that is to be moved.

-TO <to_instance>

Specifies the destination instance or list of instances.

-Golden Applies in the Golden design. This is the default.

-Revised Applies in the Revised design.



OPEN SCHEMATICSOPEn SChematics

[-Golden | -Revised][full pathname](Setup / LEC Mode)

Opens the schematic viewer and displays the root module schematics. This command cannotbe used in the non-graphic mode.

Parameters

Related Commands

CLOSE SCHEMATICS

DIAGNOSE

REPORT GATE

-Golden Specifies that the path is in the Golden design.

-Revised Specifies that the path is in the Revised design.

full pathname Opens a schematic for the specified path.



OPTIMIZE PATCHOPTimize PAtch

-WORKdir <working_directory>-LIBrary <library_file_list>[-RCExec <rc_executable>][-SDC <sdc_filename>][-VERbose][-KEEPHierarchy][-CLEANUP][-AVOID <cell_name>*][-USE <cell_name>*][-POSTLIBscript <script_name>][-POSTSYNscript <script_name>][-PRESYNscript <script_name][-NETnaming <format_string>][-INStancenaming <format_string>][-SEQuentialnaming <format_string>](Setup Mode)

Writes out an RTL Compiler script (run_rc.tcl) in the working directory that will optimizethe patches and execute the script.

After OPTIMIZE PATCH successfully completes, the ECO design will be in memory and canbe written out. The optimized patches will be in the working directory.

Important

Before running this command, you must run the APPLY PATCH -keephierarchycommand.

Parameters

-WORKdir <working_directory>

Specifies the name of the working directory for the optimizedpatches.

-LIBrary <library_file_list>

Specifies the name of the library files.

If the library name contains a relative path, the path should berelative to the directory declared in -workdir.



-RCExec <rc executable>

Specifies the path to the RTL Compiler executable. If this is notspecified, the software will use the rc command in your searchpath.

-SDC <sdc_filename> Specifies the name of the SDC file.

If the SDC filename contains a relative path, the path should berelative to the directory declared in -workdir.

-VERbose Outputs all RTL Compiler messages. By default, the commandonly outputs error messages.

-KEEPHierarchy Specifies that the ECO changes will be put in a submodule.

-CLEANUP Deletes the generated files.

-AVOID <cell_name>* Avoids the specified library cells. This accepts wildcards.

-USE <cell_name>* Uses the specified library cells. This accepts wildcards.

Note: The order that you specify the -AVOID and -USE optionsis significant. For example:

-avoid * -use NAND2 INV2

avoids all the library cell types except NAND2 and INV2. If theseoptions are specified in the following order:

-use NAND2 INV2 -avoid *

then no cell types will be available for mapping.

-POSTLIBscript <script_name>

Specifies the script to run after reading in the libraries.

-POSTSYNscript <script_name>

Specifies the script to run after each patch is synthesized.

-PRESYNscript <script_name>

Specifies the script to run before each patch is synthesized.

-NETnaming <format_string>

Specifies the net naming format of the ECO nets. For example,for eco_net_%d, the %d will be an integer that makes the netname unique.



Example

The following script reads in the original netlist and patch, then runs OPTIMIZE PATCH tomap and optimize the ECO changes:

read library typical.lib -liberty

read design top.gv patch1.v

apply patch mod1 mod1_eco -keephierarchy

optimize patch -workdir rc_work -library ../typical.lib

write design top.eco.gv -replace

Related Commands

APPLY PATCH

-INStancenaming <format_string>

Specifies the instance naming format of the ECO combinationalcells. For example, for eco_instance_%d, the %d will be aninteger that makes the instance name unique.

-SEQuentialnaming <format_string>

Specifies the instance naming format of the ECO registers andlatches. For example, eco_%s, where %s is the original registername.



PIN GROUPPIN GRoup

[-Golden | -Revised][-DEScend | -ASCend][-ADDEXPression <string> <string>][-ADDList <name>[#:#] "<net> <net> ..."][-ALL | -Module "<name> <name> ..."](Setup Mode)


Combines a group of single nets or pins into a bus. The Conformal software uses the followingtwo default patterns to group pins or nets into busses:

■ Name[#]

■ Name<#>

For example, nets blb[3] blb[4] blb[5] will be grouped into bus blb[5:3], and pinswladd<1> wladd<2> wladd<3> will be grouped into bus wladd[3:1].

Parameters

-DEScend Defines the bus in descending numerical order. This is thedefault.

-ASCend Defines the bus in ascending numerical order.

-ADDEXPression <string> <string>



Related Command

GROUP

Specifies expression(s) for rules on signals to bus. You canspecify your own renaming mapping of specific names to twodefault patterns, so that it recognizes those names as buses also.For example:

-ADDexpression "mybus_%d_bar" "mybus_bar[@1]"

maps the following names into the first default bus name:

mybus_12_bar mybus_13_bar mybus_14_bar => mybus_bar[12]mybus_bar[13] mybus_bar[14]

then the renamed names will be further grouped into busmybus_bar[14:12]

The renaming mapping syntax:

mybus_%d_bar" "mybus_bar[@1]"

is defined in the ADD RENAMING RULE command.

-AddList <name>[#:#] “<net> <net>”

Allows you to bus random signals. These nets can be single netsor mixed single nets and complete busses. The number of netsdefined must be equal to the bus range. If a bus range more thanthe number of nets is defined a "-" character is used as aplaceholder for that bit position.

-ALL Specifies that when pins of a module are converted to a bus, allinstantiations of that module need to be updated. This is thedefault.

-Module “<name> <name>”

Specifies the module that needs to be updated pins of thatmodule are converted to a bus.



PRINTENVPRINTENV

[<variable>](Setup / LEC Mode)

Displays environment variable values.

Parameters

Related Command

SETENV

<variable> Prints the value of the specified variable. If you do not specify avariable, this command displays the value of every environmentvariable.



PROVEPROve

<[-Golden | -Revised] identifier><-ONe |-ZEro | [-Revised | -Golden] identifier>[-NOInvert | -Invert | -Both](LEC Mode)

Starts a process that shows whether the specified gates are equivalent or nonequivalent. Theproof process checks equivalency for one of the following pairs:

■ One gate in each of the Golden and Revised designs

■ Two gates in the Golden design

■ Two gates in the Revised design.

Use the ADD DYNAMIC CONSTRAINTS command to specify constraints you want to useduring this proof process.

Parameters

-Golden Specifies that the first prove point is in the Golden design. Thisis the default.

-Revised Specifies that the first prove point is in the Revised design.

identifier Uses this gate from the specified design as the first prove point.The identifier will be one of the following:

■ Gate identification number

■ Instance path

■ Pin path


-ONe Proves whether the specified gate is equal to a one value.

-ZEro Proves whether the specified gate is equal to a zero value.

-Revised Specifies that the second prove point is in the Revised design.This is the default.

-Golden Specifies that the second prove point is in the Golden design.



Examples


Related Commands



DIAGNOSE

REPORT COMPARE DATA


-NOInvert Proves for equivalence. This is the default.

-Invert Proves for inverted equivalence.

-Both Proves for either non inverted or inverted equivalence.



READ CPFREAd CPf

<filename.cpf ...>[-GOLden | -REVised | -BOTH][-VERbose](Setup Mode)


Reads in the Common Power Format (CPF) files.

Cadence recommends reading in all the CPF files at once with this command. Any susequentruns will replace all the low power information issued by the previous READ CPF command.

All READ DESIGN and READ LIBRARY commands should be run before running thiscommand.

Parameters

Example

The following command reads the lib.cpf and design.cpf files and checks that they arespecified correctly:

read cpf lib.cpf design.cpf

Related Commands

COMMIT CPF

REPORT CPF LOGIC

<filename.cpf ...> Specifies the name of the Common Power Format file(s).

-GOLden Reads in the CPF files for the Golden design. This is thedefault.

-REVised Reads in the CPF files for the Revised design.

-BOTH Reads in the CPF files for both the Golden and Reviseddesigns.

-VERBose Displays additional messages during execution.



READ DESIGNREAd DEsign

<filename>[-ROot <module_name>][-CONFiguration | -NOCONFiguration][-ROOTConfig <configuration_name>][-VErilog | -VERILOG2K | -SYStemverilog

| -VHdl [93 | 87] | -SPice | -Ndl | -EDIF|-LIBErty][-File <command_filename>][ | -REPlace | -APPend][-Define <name>][-Map <library_name> <library_path>][-MAPRecursive <library_name> <library_path>][-MAPFile <library_name> <filename…>][-LIBRary <library_name> <library_path>]

(this option is the same as -Map)[-STATEtable | -NOSTATEtable][-BBOXUNResolve][-BLAST_inst_port][-RAngeconstraint | -NORAngeconstraint][-INITial_value][-VHDLESCaped_to_verilog][-CONTINUOUSASSIGNment <BIdirectional | UNIdirectional>][-NOZPUSHing | -ZPUSHing][-ENUMConstraint][-VMEM_LIB][-VMEM_ULTRA][-SUPPLY | -NOSUPPLY][-UNCompress <zip_file_name>][-UNZip <zip_file_name ...>][-PARAmeter [-INT | -STR | -ENUM] <name> <value>]

(combined with -ROot option)[-ARchitecture <architecture_name>][-FUnctiondefault [0 | 1 | x]][-NOKeep_unreach | -Keep_unreach][-SEnsitive | -NOSEnsitive][-NOELaborate][-EXClude <exclude_file_name*>][-VERBose][-OPTimize | -NOOPTimize][-LAstmod][-MErge BBox][-Golden | -REVised](Setup Mode)



Reads in the Golden and Revised designs.

Important

Review these important reminders before using the READ DESIGN command:

■ Use the SET NAMING RULE command first if you intend to read in an RTL design thatrequires specific naming conventions.

■ Use the SET UNDEFINED CELL command before the READ DESIGN command if yourdesign includes undefined cells that should be treated as blackboxes.

Note:

■ If your design includes duplicate modules, Conformal uses the first module and ignoreslater ones. However, you can use the -lastmod option to specify that Conformal use thelast module and ignore the earlier ones.

■ Use the tilde character (~) to shorten the path of the file.

■ Use the backslash character (\) at the end of a line to show that the command you areentering continues on the next line.

Supported Options

The following Verilog and VHDL considerations are offered:

■ Use the -file option with a Verilog Command file list. However, only the -v, -y,+incdir, +libext, and +define options are supported. Additionally, use the -ydoption to treat library modules as design modules.

■ The VHDL option supports all VHDL constructs and all standard and IEEE packages,including synthesis packages. It has an elaboration engine and RTL logic generation thatsupport most RTL VHDL synthesis subset constructs (see below for details). For mostnon-synthesizable VHDL constructs, Conformal displays warning messages.

VHDL and Verilog 2001 Library Mapping

You can specify how VHDL and Verilog 2001 libraries are mapped using the READ DESIGNcommand’s -map, -mapfile, or -library options.

The -map and -library options work the same in that they map logical library names tophysical directories. You can use multiple -map commands to map multiple physicaldirectories to one logical library. Use the -mapfile option for more specific library mapping,



such as specifying that a list of files must be compiled into a specified library. If you read in afile without specifying its library mapping, that file is stored in a default library called work.

Note: You can map a file into more than one library. In this case, the file is stored in eachlibrary for which it is mapped.

See the “VHDL Support” and “Verilog Support” appendices in the Encounter ConformalEquivalence Checking User Guide for additional information, including examples onlibrary mapping.

Parameters

<filename> Reads in the specified file. (Required.)

-ROot module_name The specified module is the top root module.

-CONFiguration Supports VHDL configuration constructs. This is the default.

-NOCONFiguration Does not interpret VHDL configuration.

-ROOTConfig <configuration_name>

The design includes the specified configuration for thetop-level module.

Note: This option applies to only VHDL designs.

Use this option when the design includes multipleconfigurations for the top-level module. When you use the-rootconfig option, you must also use the -rootmodule_name option (above).

-VErilog Specifies that this design is a Verilog design. (Use this optionfor Verilog designs that comply with IEEE 1364-1995.) This isthe default.

-VERILOG2K Specifies that this design is a Verilog2K design (Use thisoption for Verilog designs that comply with IEEE 1365-2001).

-SYStemverilog Specifies that this design is a SystemVerilog design.

-VHdl Specifies that this design is written in VHDL with the specifiedstandard:

93 VHDL-93 (Use this option for VHDLdesigns that comply with IEEE Std1076-1993.) This is the default.



87 VHDL-87 (Use this option for VHDLdesigns that comply with IEEE Std1076-1987.)

Note: The Conformal software supports multiple uses the-vhdl 93 and -vhdl 87 options. See the example.

-SPice Specifies that the design is a SPICE netlist design.

-Ndl Specifies that the design is an NDL design.

-EDIF Specifies that the design is an EDIF design.

-LIBErty Specifies that the design has a Liberty library format type.(Use this option to qualify the library as Liberty.)

-File <command_filename>

Reads in the specified command file as a design.

Note: This option is for Verilog or VHDL command file lists.

The options for <command_filename> are described inTable 2-1 on page 244 for Verilog and Table 2-2 on page 245for VHDL.

-REPlace Removes all designs that were previously read in, andreplaces them with the specified design.

-APPend Appends the design to the one that was previously read.

For example, you can use this option to fix a top module andthen read it in again without parsing the entire design fileagain:

read design top.v -append -lastmod

Note: The top module cannot pass parameters to modulesthat are read in previously.

-Define <name> Defines `ifdef variable names in Verilog.

-Map <library_name> <library_path>

Reads in files for the specified <library_name> from<library_path>.

Use this option to read in all of the VHDL or Verilog files in thespecified library path for the given library name. You can alsomap multiple directories to a single library. For example:

read design -vhdl top.vhd -map mylib /design/path1 \-map mylib /design/path2



-MAPRecursive <library_name> <library_path>

This option has the same function as -Map, but it searches forall VHDL or Verilog files recursively down to the subdirectoriesof the <library_path>.

-Map searches VHDL or Verilog files under the<library_path> and will not search any VHDL files underthe subdirectories of <library_path>.

-MAPFile <library_name> <file_name …>

Reads in the specified <file_name …> and includes them inthe <library_name>.

Use this option to specify the files that belong to a givenlibrary. The file list terminates with the next option or the endof the READ DESIGN command.

You can also use multiple -mapfile options to specifymultiple files in a library.

For example, the following two commands are the same:

read design -vhdl top.vhd -mapfile \mylib x1.vhd -mapfile mylib x2.vhd

read design -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd

-LIBRary <library_name> <library_path>

Reads in the specified file in the given library and path foruser-defined VHDL libraries. (This option is the same as-map.)

-STATEtable Enables support for Synopsys Liberty state tables. This isthe default.

Note: This option supersedes the SET STATETABLEcommand.

-NOSTATEtable Disables support for Synopsys Liberty state tables.

-BBOXUNResolve Specifies that unresolved semantics as unsupportedconstructs (in VHDL) will be blackboxed instead of erroringout.



-BLAST_inst_port Allows the cell model to have a bus pin while the instantiationis bit-blasted.

By default, instantiations that contain bit-blasted connectionsare errored out. The Verilog standard does not allow theseconnections.

-RAngeconstraint When a variable is of type integer with a value range, a valuecheck is made against the range. If a value is out of range, itwill be interpreted as don’t care. This is the default.

For example:

variable v : integer range 3 to 5;

With -RAngeconstraint, v will be interpreted as:

((v>=3 && v<=5)? v : 3’bx).

Note: This option applies only to VHDL designs.

-NORAngeconstraint Specifies that no value check is made against the integervalue range.


-INITial_value Specifies that the variable’s initial value will not be ignored.


-VHDLESCaped_to_verilog

Specifies that if the content between ‘\’ pairs does not containany white space, the new name is the escaped content.

For example, \A_B_C_\ changes to \A_B_C_. In all othercases, the VHDL escaped name is unchanged. For example,\1 2\ is unchanged.

-CONTINUOUSASSIGNment <BIdirectional | UNIdirectional>

Specifies that continuous assignment in the design should beinterpreted as uni-directional or bi-directional assignment.

-NOZPUSHing Does not pushes tristate toward module output. This is thedefault.

-ZPUSHing Pushes tristate toward module output.



-ENUMConstraint When a variable is of type of enumeration, a value check ismade against the enumeration range. If a value is out ofrange, it will be interpreted as don’t care. For example:

variable v : day;

Where day is an enumeration of {sun, mon, tue}

With -ENumconstraint, v will be interpreted as:

((v>=sun && v<=tue)? v : 2’bx).

-VMEM_LIB Reads in the RTL model containing the Conformal MemoryPrimitive.

This option is a Conformal Custom option.

Note: Without the -vmem_lib option, Conformal does notrecognize the Conformal Memory Primitive.

-VMEM_ULTRA Reads in the RTL model containing the Conformal MemoryPrimitive for checking by Conformal Ultra. To use this option,you must have a Conformal Ultra license.

This option is a Conformal Ultra option.

Note: When you use this option, no debugging is allowed. Usethe -vmem_lib option for memory verification.

-SUPPLY Keeps all Verilog supply0 and supply1 type netsunchanged. This is the default.

-NOSUPPLY Converts the Verilog supply0 and supply1 type nets toVerilog wire type nets.



-UNCompress <zip_file_name>

Reads in the specified compressed file. By default, theConformal software uses gunzip to unzip the file into the /tmpdirectory.

You can control the tool and directory used with UNIXvariables CONFORMAL_UNCOMPRESS and CONFORMAL_TMP.

-UNZip <zip_file_name ...>

This option has the same function as -UNCompress exceptthat it can include a list of filenames. For example:

read design fileABC -UNZ zip1 zip2 zip3

The list of filenames end when a subsequent option isspecified, or if it is at the end of the command line.

Note: Specifying -uncompress or -unzip is optional forgunzipped files because the Conformal software canautomatically recognize this file type.



-PARAmeter [-INT | -STR | -ENUM] <name> <value>

Assigns design parameters or replace existing designparameters. To specify multiple parameters, use the-parameter option for each parameter you want to set. Forexample:

read design filename -parameter parm1 value1 \-parameter -int parm2 value2

This option applies to both Verilog and VHDL files. (Combinewith -root.)

When using the -parameter -int <name> <value>command, the <value> will be converted to integer value,which can be a positive integer (1), negative integer (-1), aninteger value recognized as a string ("1"/"-1"), or a Verilogstyle integer ("16’h0001"). When using a Verilog styleinteger, the value must be specified between double-quotes ("").

When using the -parameter -str <name> <value>command, the <value> will be saved as a string.

When using the -parameter -enum <name> <value>command, the <value> will be converted to a VHDLenumeration literal. For example, the following command setsthe parameter P4 to VHDL enumeration literal GREEN:

read design -root mod1 filename \-parameter -enum P4 GREEN

Note: Any value that is not recognized as an unsigned decimalinteger value is interpreted as string value.

Note: If -int or -str is not specified, then the parametervalue will be interpreted as an integer if it is not betweendouble-quotes (" "), and as a string if it is betweendouble-quotes. Therefore, if you want to specify a Verilogformat value, it must be between double-quotes and used withthe -int option.



-ARchitecture architecture_name

Reads in files with the specified architecture.

Use this option when multiple architectures of the same rootdesign are compiled.

This option is associated with the -configuration option,otherwise only one architecture is kept for each entity.

-FUnctiondefault Specifies the default return value for unspecified orincompletely specified functions.

0 Returns zero.

1 Returns one.

x Returns x.

-NOKeep_unreach Remove any unreachable DFF or D-Latch in a module duringRTL synthesis. This is the default.

-Keep_unreach Keeps any unreachable DFF or D-Latch in a module duringRTL synthesis.

-SEnsitive Specifies that the design is case sensitive. This is thedefault.

-NOSEnsitive Specifies that the design is not case sensitive.

-NOELaborate Reads in multiple files of different languages.

-EXClude <exclude_file_name*>

Specifies files to exclude when reading in the design. Thisaccepts the wildcard.

Note: You cannot use multiple wildcards with this option.

-VERBose Displays the verbose messages of parsing and translatingeach design module.

-OPTimize Optimizes redundant logic (in library cells) that can affect theway Conformal interprets the design. This is the default.

Note: Using this option does not always optimize all redundantlogic.

See the following example:

read design file1 file2 file3 -nooptimize \-optimize -nooptimize -replace



Table 2-1 Supported Verilog Command-Line Options

The following table lists the Verilog command options that Conformal supports.

-NOOPTimize Preserves redundant logic in Library cells.

See the example listed above (-optimize).

-LAstmod If duplicate modules exist, the Conformal software uses thefirst module and ignores the later ones by default. Use thisoption to specify that Conformal use the last module andignore earlier ones.

-MErge BBox Replaces all blackboxed modules in the design space withmodules in the library space.

-Golden Designates this design “Golden.” This is the default.

-REVised Designates this design “Revised.”

Supported:

<file> (Design data file) A list of the design files.

-v <file> (Library file) A list of library files.

-y <directory> (Library directory) A list of library directories.Conformal searches for modulesnot defined in the design files.

Conformal reads in these modulesas library modules.

+incdir+<dirname>… (Include directories) A list of “include” directoriescontaining design files.

This option is similar to the ADDSEARCH PATH command.

+libext+<extension>…

(Library extensions) A list of library extensions you caninclude when using the -y option.

The default is .v.

+define+<name>… (Define macros) A list of macro names you caninclude in the `define statement



Table 2-2 Supported VHDL Command-Line Options

The following table lists the VHDL command options that Conformal supports.

Examples

The following example demonstrates how to use the backslash character to show that yourcommand continues on the next line.

read design tran1.spi tran2.spi tran3.spi \

-spice -revised

In the following example, only ent2.vhdl and arch2.vhdl will be parsed according toVHDL 87 syntax rules. All the other files will be parsed according to VHDL 93 syntax rules.

read design ent0.vhdl arch0.vhdl \

-vhdl 93 ent1.vhdl arch1.vhdl \

-vhdl 87 ent2.vhdl arch2.vhdl \

-vhdl ent3.vhdl arch3.vhdl

Related Commands


-yd <directory> (Design directory) A list of directories.

Conformal searches for modulesthat are not defined in the designfiles.

Conformal reads these modules inas design modules.

-f <file> (another command file)

Supported:

<file> Individual design file

-map <libname> <dirname> Map logical library name to a directory

-mapfile <libname> <filename ...> Map logical library name to a list of files

-library <libname> <dirname> Map logical library name to a directory



ADD RENAMING RULE

ADD SEARCH PATH



DELETE SEARCH PATH

READ LIBRARY

REPORT DESIGN DATA

REPORT MESSAGES

REPORT MODULES



REPORT RULE CHECK

REPORT SEARCH PATH

SET DIRECTIVE

SET NAMING RULE

SET ROOT MODULE

SET RULE HANDLING

SET STATETABLE

SET UNDEFINED CELL

WRITE DESIGN




READ FSM ENCODINGREAd FSm Encoding

<filename>[-Golden | -Revised](Setup Mode)

Directs Conformal to read in a file that defines new Finite State Machine (FSM) encoding.

By default, Conformal reads binary encoding when building an FSM. Therefore, if your gatenetlist uses different encoding (for example, one-hot), you must use the READ FSMENCODING command to specify the correct encoding. See the example of an FSM encodingfile below.

Parameters

Examples

The following example shows the need for the READ FSM ENCODING command. In this case,the user was alerted to encoding differences during mapping. The Golden design showed tworegisters, while the Revised showed four registers. The following is an example of an FSMencoding file that replaces the binary encoding with one-hot encoding:

.fromstates current_state_reg[1] current_state_reg[0]

.tostates current_state_reg[3] current_state_reg[2] current_state_reg[1]current_state_reg[0]

.begin

00 0001

01 0010

10 0100

11 1000

.end

In this example, between .begin and .end:

■ .fromstates are the left-hand side states

<filename> Reads in the specified file. This option is a required filenamethat contains the encoding differences.

-Golden Uses this library with the Golden design. This is the default.

-Revised Uses this library with the Revised design.



■ .tostates are the right-hand side states



READ LEF FILEREAd LEf File

<filename>[-GOLden | -REVised](Setup Mode)

Reads in the LEF file. For each cell in the LEF database with matching library cell, thiscommand will do the following:

■ Report library cell with ports that are not in the LEF file

■ Report non-power or ground ports in the LEF file and not in library

■ Add all ports in the LEF file, and not in library to library cell

Parameters

<filename> Specifies the name of the LEF file.

-Golden Reads in the LEF file for the Golden design. This is thedefault.

-Revised Reads in the LEF file for the Revised design.



READ LIBRARYREAd LIbrary

<filename*…>[-VErilog | -VERILOG2K | -SYStemverilog | -VHdl [93|87] | -Liberty][-SEnsitive | -NOSEnsitive][-EXtract][ | -REPlace | -APPend][-Define <name>][-Map <library_name> <library_path>][-MAPRecursive <library_name> <library_path>][-MAPFile <library_name> <filename ...>][-CONFiguration | -NOCONFiguration][-VERBose][-SUPPLY | -NOSUPPLY][-UNCompress <zip_file_name>][-UNZip <zip_file_name ...>][-OPTimize | -NOOPTimize][-STATEtable | -NOSTATEtable][-LAstmod][-MULTIPLE_LIBraries][-Both | -Golden | -Revised][-NOShare][-NOELaborate][-EXClude <exclude_file_name*>](Setup Mode)

Reads in the library model descriptions for Verilog, VHDL, or Liberty designs. The library iseither a Verilog simulation library or a Synopsys Liberty library. It is read for the Golden,Revised, or both designs.

Note: For RTL to gate formal equivalence checking, use simulation libraries instead ofsynthesis libraries because design verification signoff happens for simulation libraries—notfor synthesis libraries.

The READ LIBRARY command must be used before the READ DESIGN command if thedesign is Verilog, VHDL, or Liberty.

Note: Library in this context refers to the technology library, such as ASIC cell and memorydefinitions. See READ DESIGN for information on reading VHDL libraries and packages.

Important

■ If there are duplicate modules, the Conformal software uses the first module and ignoreslater ones. However, you can use the -lastmod option to specify that Conformal use thelast module and ignore earlier ones.



■ Use the backslash character (\) at the end of a line to show that the command you areentering continues on the next line.

■ Use the tilde character (~) to shorten the path of the file.

Parameters

<filename* ...> Reads in the specified file(s). This option is a required filenamethat contains the Verilog simulation library or the SynopsysLiberty library. This accepts wildcards.

-VErilog Contains the Verilog library model descriptions. This is thedefault.

Note: This supports NC-Protect and Cadence encryption.

-VERILOG2K Contains Verilog2k library model descriptions.

-SYStemverilog Contains SystemVerilog library model descriptions.

-VHdl Specifies that the library is written in VHDL. The VHDL file is ofthe specified standard:

93 VHDL-93 (Use this option for VHDL designsthat comply with IEEE Std 1076-1993.) Thisis the default.

87 VHDL-87 (Use this option for VHDL designsthat comply with IEEE Std 1076-1987.)

Note: The VITAL format is unsupported.

Note: This supports NC-Protect and Cadence encryption.

-Liberty Specifies that the library filename is in the Synopsys Libertyformat.

Note: This supports Cadence encryption.

-SEnsitive Specifies that the library model’s descriptions are casesensitive. This is the default.

-NOSEnsitive This library model’s descriptions are not case sensitive.

-EXtract Abstracts the gate information from any transistor librarymodels.

Note: This option requires a Conformal Custom license.

-REPlace Replaces the existing library. The designs are also deleted.



-APPend Appends this library to the one that was previously read.

For example, you can use this option to fix a top module andthen read it in again without parsing the entire library file again:

read library top.v -append -lastmod

Note: The top module cannot pass parameters to modules thatare read in previously.

-Define <name> Defines `ifdef variable names in Verilog.

-Map <library_name> <library_path>

Reads in files for the specified library_name fromlibrary_path.

Use this option to read in all of the VHDL or Verilog files in thespecified library path for the given library name. You can alsomap multiple directories to a single library. For example:

read library -vhdl top.vhd -map mylib /design/path1 \-map mylib /design/path2

-MAPRecursive <library_name> <library_path>

This option has same function as -Map, but it searches for allVHDL or Verilog files recursively down to the subdirectories ofthe <library_path>.

-Map searches VHDL or Verilog files under the<library_path> and will not search any VHDL or Verilogfiles under the subdirectories of <library_path>.

-MAPFile <library_name> <file_name …>

Reads in the specified files (file_name…) and include them inthe library (library_name).

Use this option to specify the files that belong to a given library.The file list terminates with the next option or the end of theREAD LIBRARY command.

You can also use multiple -mapfile options to specify multiplefiles in a library.

For example, the following two commands are the same:

read library -vhdl top.vhd -mapfile\ mylib x1.vhd -mapfile mylib x2.vhd

read library -vhdl top.vhd -mapfile mylib x1.vhd x2.vhd

-CONFiguration Supports VHDL configuration constructs. This is the default.



-NOCONFiguration Does not interpret VHDL configuration.

-VERBose Displays the verbose messages of parsing and translating eachlibrary module.

-SUPPLY Keeps all Verilog supply0 and supply1 type nets unchanged.This is the default.

-NOSUPPLY Converts the Verilog supply0 and supply1 type nets toVerilog wire type nets.

-UNCompress <zip_file_name>

Reads in the specified compressed file. By default, theConformal software uses gunzip to unzip the file into the /tmpdirectory.

You can control the tool and directory used with UNIX variablesCONFORMAL_UNCOMPRESS and CONFORMAL_TMP.

-UNZip <zip_file_name ...>

This option has the same function as -UNCompress exceptthat it can include a list of filenames. For example:

read design fileABC -UNZ zip1 zip2 zip3

The list of filenames end when a subsequent option isspecified, or if it is at the end of the command line.

Note: Specifying -uncompress or -unzip is optional forgunzipped files because the Conformal software canautomatically recognize this file type.

-OPTimize Removes redundant buffers in library cells. This is the default.

Note: Using this option does not always optimize all redundantlogic.

See the following example:

read library file1 file2 file3 -nooptimize -optimize \

-nooptimize -replace

-NOOPTimize Preserves redundant buffers in library cells.

See the example listed above (-optimize).



-STATEtable Enables support for Synopsys Liberty state tables. This is thedefault.

Note: This option supersedes the SET STATETABLEcommand.

-NOSTATEtable Disables support for Synopsys Liberty state tables.

-LAstmod If duplicate modules exist, Conformal uses the first module andignores the later ones by default. Use this option to specify thatConformal use the last module and ignore earlier ones.

-MULTIPLE_LIBraries If duplicate modules exist, Conformal uses the first modulesand ignores the later ones by default. Use this option to specifythat Conformal store duplicated liberty modules if they are in adifferent library.

-Both Uses this library for both the Golden and Revised designs. Thisis the default.

-Golden Uses this library with the Golden design.

-Revised Uses this library with the Revised design.

-NOShare Does not share the library files for both the Golden and Reviseddesigns, and appends the library files to both designs.

When this option is used together with the default -Bothoption, this is the equivalent of running the following twocommands:

read library -golden <filenames>

read library -revised <filenames>

By default, the Conformal software shares the library files forboth the Golden and Revised designs, and does not append thelibrary files to either design.

-NOELaborate Reads in multiple files of different languages. With this option,you can defer the binding of entity or module instantiations.

This is for cases when you have mixed library files in VHDL andVerilog languages, where a VHDL entity in one library fileinstantiates a Verilog module, and a Verilog module in anotherlibrary file instantiates a VHDL entity.



Related Commands


ADD RENAMING RULE

ADD SEARCH PATH



DELETE SEARCH PATH

READ DESIGN

REPORT DESIGN DATA

REPORT MESSAGES

REPORT MODULES



REPORT RULE CHECK

REPORT SEARCH PATH

SET DIRECTIVE

SET RULE HANDLING

SET STATETABLE

SET UNDEFINED CELL

-EXClude <exclude_file_name*>

Specifies files to exclude when reading in the library. Thisaccepts the wildcard.

Note: You cannot use multiple wildcards with this option.




WRITE LIBRARY



READ MAPPED POINTSREAd MApped Points

<filename>[-GOLDen_prefix <string>][-REVIsed_prefix <string>][-EXACT_name](LEC Mode)

Reads in the mapped point information you created with the WRITE MAPPED POINTScommand. By default, Conformal automatically maps key points during the transition fromSetup to LEC mode. And if the key points are already mapped, Conformal ignores anymapped point information in the file. Thus, to prevent Conformal from automatically mappingkey points during the transition from Setup to LEC mode and enable Conformal to read inmapped point information completely from the file, do one of the following:

■ Use the set flatten model -nomap command before you set the system mode toLEC.

■ Use the set system mode lec -nomap command to suppress automatic mappingduring the transition to LEC mode.

Use the tilde character (~) to shorten the file’s path.

Note: Use the Golden and Revised prefix options to specify the hierarchy of the instancename. If a hierarchical submodule’s map point information is written to a file, it can be read inat a higher level module or the top root module with the specified hierarchical prefix string.

Parameters

<filename> Reads mapped point information from the specified file.

-GOLDen_prefix string

Appends this Golden prefix string to the instance names.

This option lets Conformal read the mapped point file for ahigher-level module containing hierarchy.

-REVIsed_prefix string

Appends this revised prefix string to the instance names.

This option lets Conformal read the mapped point file for ahigher-level module containing hierarchy.



Related Commands

SET FLATTEN MODEL

WRITE MAPPED POINTS

-EXACT_name Specifies an exact match for the names specified in the file.This can help speed up the process of reading files where manynames are incorrect.



READ MEMORY PRIMITIVEREAd MEmory Primitive

<filename1 filename2…>(Setup Mode)


Reads in Verilog memory primitive simulation models that were created using the Conformalmemory primitive generator. This command creates a memory-friendly, synthesized view thatyou can use for comparison with a memory circuit.

Important

Read in designs that use the memory primitive after you use this command.

Parameters

Related Command

READ DESIGN

<filename1 filename2...> Specifies the files to read in.



READ ROM PRIMITIVEREAd ROm Primitive

<filename>[-CODE_FILE <codefilename>][-CODE_FILE_FORMAT <BIN | HEX>](Setup Mode)


Reads in Verilog ROM primitive simulation models that were created using the ConformalROM primitive generator.

Parameters

Related Command

READ DESIGN

<filename> Specifies the file to read in.

-CODE_FILE <codefilename>

Specifies the code file that will initialize the ROM.

-CODE_FILE_FORMAT <BIN | HEX>

Specifies the format of the code file.

If you do not specify the -code_file_format option, thesoftware uses the format selected during primitivegeneration.



READ RULE CHECKREAd RUle Check

<filename> <-EXClude |-INClude>[-Design | -Library][-GOLden | -REVised](Setup Mode)

Performs incremental rule checks. The first time you run a session, write the rule violationsinto a rule file using the write rule check <filename> -golden (or-revised) command. For later runs, exclude the violations already flagged with the readrule check -exclude <filename> command.

Use the tilde character (~) to shorten the path of the file.

Parameters

<filename> Specifies the name of the file that contains rule violations froma previous session.

-EXClude Excludes checks for violations noted in the specified file.Thisoption works as a filter; therefore, use it after the READDESIGN command.

-INClude Includes checks for violations noted in the specified file. Thisoption lets you reinstate violations that were previouslyexcluded.

-DEsign Reads only design rule check violations. If you do not specify-design or -library, Conformal reads rule check violationsfrom both designs and libraries.

-LIbrary Reads only library rule check violations. If you do not specify-design or -library, Conformal reads rule check violationsfrom both designs and libraries.

-Golden Applies this command to the Golden design. This is thedefault.

-Revised Applies this command to the Revised design.



Examples

In the following example, the second report rule check will not report any rules.

read design g.v -goldenread design r.v -revised

write rule check rule.g -golden -replacewrite rule check rule.r -revised -replace

read design g.v -golden -replaceread design r.v -revised -replace

report rule check -verbose -both

read rule check rule.g -exclude -goldenread rule check rule.r -exclude -revised


Related Command

WRITE RULE CHECK



READ PATTERNREAd PAttern

<filename>[-Verilog | -SPice ][-Golden | -Revised | -Both][-SEnsitive | -NOSEnsitive][-LAstmod](Setup Mode)


Reads in the transistor description from a file that Conformal Custom applies to the Goldenand Revised designs. (The file format type is either Verilog or SPICE.)

The transistor description represents a pattern that Conformal Custom seeks duringabstraction. When Conformal Custom detects a pattern, it substitutes a user-specifiedfunctional model. Before this command can be executed correctly, you must provide theuser-specified functional model using the READ LIBRARY command. The transistordescription file and functional model have the same module and port names; port directioncan be different, but, neither the transistor description file nor the library database can containsubmodules—every cell must be flat.


Parameters

<filename> A required filename. It contains the transistor abstractioninformation.

-Verilog The transistor description file format is Verilog. This is thedefault.

-SPice The transistor description file format is SPICE.

-Golden Applies the file’s sub-circuit information to the Golden design.This is the default.

-Revised Applies the file’s sub-circuit information to the Revised design.

-Both Applies the file’s sub-circuit information to both the Golden andRevised designs.

-SEnsitive The transistor description file is case-sensitive. This is thedefault.

-NOSEnsitive The transistor description file is not case-sensitive.



Examplesread pattern DLTCH1.v -verilog -revised

read pattern DLT2.v -verilog -both

read pattern xtran.spi -spice -golden

// Functional description of the transistor

// pattern

read library lib.v -verilog -golden

// Transistor pattern description

read pattern pattern.v -golden

read design design.v -golden

abstract logic -golden

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE


DELETE CLOCK



REPORT CLOCK



-LAstmod If duplicate modules exist, Conformal uses the first module andignores the later ones by default. Use this option to specify thatConformal use the last module and ignore earlier ones.




RESOLVE



REDUCE MOSREDuce MOs

[-ALL | -MODule <module name> ...][-Golden | -Revised][-MERGE_TRAN][-SD_GND][-SD_VDD][-DIODE][-PARALLEL][-GATE_ON][-GATE_OFF][-NOVERbose](Setup Mode)


Performs varieties of reduction on MOS transistor(s) from the circuit.

Parameters

-All Reduces transistor logic from all modules. This is thedefault.

-MODule <module name> ...

Specifies the module(s) to reduce transistor logic.

-Golden Reduces transistor logic from the Golden design. This isthe default.

-Revised Reduces transistor logic from the Revised design.

-MERGE_TRAN Collapses the tran or rtran device into the wire.

-SD_GND Removes MOS devices with source and drain on GND.

-SD_VDD Remove MOS devices with the source and drain on VDD.

-DIODE Collapses [PN]mos into the wire if the source is on[VDD|GND] and the gate and drain are on the same net.

-PARALLEL Collapses parallel-connected MOS devices into one MOS.

-GATE_ON Collapses non-weak MOS devices into the wire if the gate isa constant that causes current to flow.

-GATE_OFF Removes non-weak MOS devices if the gate is a constantthat does not cause the current to flow.



Related Commands

ABSTRACT LOGIC

READ DESIGN -spice

-NOVERbose Does not report detailed statistical information.



REMODELREMODEL

<-SEQ_MERGE | -SEQ_CONSTant | -DFF_CONST_ASYNC | -UNFOLD_DFF| -BBOX_MERGE | -RED_DLAT | -GATED_CLOCK | -REVERSE_SEQ_REDundant| -SEQ2BUFfer | -SEQ_CONSTANT_GROUP | -UNREACH>

<-UNMAPPED | -MAPPED | -ALL | gate_id ... | instance_pathname ...>[-MAX_UNMAP <number_of_keypoints>][-BOTH | -GOLden | -REVised][-REPEAT][-VERBose](LEC Mode)

Used in LEC mode and after mapping, this takes a set of key points and attempts to remodelthem. Use this command in conjunction with the SET FLATTEN MODEL command to resolvemis-compares due to key point issues.

When you use this command, the Conformal software invalidates compare results (if theyexist), closes schematics, and updates the Mapping Manager.

Parameters

-SEQ_MERGE Merges common groups of sequential elements into onesequential element in a logic cone of a key point.

Note: This modeling can only be applied to unmapped DFFs orD-latches.

-SEQ_CONSTant Converts a DFF or D-latch to a ONE or ZERO gate.

Note: This modeling can only be applied to unmapped DFFs orD-latches.

-DFF_CONST_ASYNC Converts a DFF to a ZERO or ONE gate due to itsasynchronous set or reset condition. This can be applied toboth unmapped or mapped DFFs.

-UNFOLD_DFF Converts a DFF to 2 D-latches with a master/slaveconfiguration.

Note: For latch-based custom logic comparisons, this optionmight work better than set flatten model -latch_fold.

-BBOX_MERGE Performs automatic blackbox merging.



-RED_DLAT Collapses serial D-latches (even when there is logic betweenthem) into the last latch on that clock phase. You cannot usethis option with latches that have set or reset pins.

-GATED_CLOCK Transforms the gated clock of DFF to a MUX feedback loop.

-REVERSE_SEQ_REDundant

Restores the sequential redundancy to the outputs of thespecified DFFs or DLATs.

-SEQ2BUFfer Remodels a DFF or DLAT to a buffer or inverter due toasynchronous connections.

-SEQ_CONSTANT_GROUP Validates and remodels a group of registers to ZERO and ONEgates, which are dependent upon each other.

Note: You must specify a correct group of registers for thismodeling to be effective; otherwise, any non-constant register inthe group will prevent the true constant group from beingrecognized.

-UNREACH Determines if the specified mapped key points are functionallyunreachable to primary outputs. After the key point is proved tobe functionally unreachable, the fan-out nets from this key pointare tied to constant zero. This analysis is useful to subsequentlyremove the functionally unreachable non-equivalent comparedpoints from the compare and mapping lists.

Note: This remodeling can only be performed on mapped keypoints and should be used after running the COMPAREcommand.

Note: Use the DELETE MAPPED POINTS -unreachcommand to delete unreachable mapped points.

-UNMAPPED | -MAPPED | -ALL | gate_id | instance_pathname…

Applies the specified remodeling to all unmapped key points, allmapped key points, all key points, or the specified gate orinstance. By default, Conformal remodels all unmappedpoints.

Note: -ALL only applies to the options: -gated_clock,-reverse_seq_redundant, -seq2buffer, and-seq_constant_group.



Exampleremodel –seq_constant Q1_reg

Sample Implementation for the REMODEL Command:

In the following example, the design can be mapped almost completely by name, but thereare key points that have not been merged. To remodel replicated registers into a singleregister, use the REMODEL command. Then Conformal can remap key points and compare.

…

set flatten model -seq_merge

set map method -name only

set system mode lec

remodel -seq_merge -both -unmapped

set map method -name first

map key points

add compare points -all

compare

Related Commands

COMPARE


-MAX_UNMAP <number_of_keypoints>

Specifies an upper limit of unmapped keypoints to beremodeled.

-BOTH Applies the specified remodeling to the Golden and Reviseddesigns. This is the default.

-GOLden Applies the specified remodeling to the Golden design only.

-REVised Applies the specified remodeling to the Revised design only.

-REPEAT Repeats until no further modeling is possible. Except forsequential constant modeling, by default, the Conformalsoftware attempts to remodel once.

Note: Use Ctrl-C to interrupt remodeling.

-VERBose Provides additional information.



MAP KEY POINTS

SET FLATTEN MODEL



REMOVEREMove

<name* ...>[-Golden | -Revised][-INSTance | -INS_Module][-MODule <mod_name*> | -ALL](Setup Mode)

Removes instances from the database.

Tip

To report instances removed with this command, run the REPORT REMOVEDINSTANCE command.

Parameters

name* ... Specifies the name(s) of the instance(s) to remove. Thisaccepts wildcards.

-Golden Removes instances from the Golden design. This is thedefault.

-Revised Removes instances from the Revised design.

-INSTance Indicates that the <name* ...> specifies the instancenames. This specifies to remove all instances whose instancenames match <name* ...>. This is the default.

-INS_Module Indicates that the <name* ...> specifies the module names.This specifies to remove all instances whose module namesmatch <name* ...>.

-MODule <mod_name*> <mod_name*> specifies the module names. This acceptswildcards. This specifies to remove the specified instancesfrom only the specified modules in <mod_name*>.

Note: If you do not specify <mod_name*>, the REMOVEcommand removes the specified instances from only the rootmodule.


-ALL Removes the specified instances from all modules in thedesign.



Example

For these lines:

module top (...);

mod1 u01 (...); // inst1

mod2 u02 (...); // inst2

mod3 u03 (...); // inst3

endmodule

module mod3 (...);

mod1 u01 (...); // inst4

mod2 u02 (...); // inst5

endmodule

■ The following command removes u01 from the root module top:

remove u01 -ALL // remove inst1, inst4

■ The following command removes u01 from module mod3:

remove u01 -MODULE mod3 // remove inst4

■ The following command removes all mod1 instances from the root module top:

remove mod1 -INS_Module // remove inst1

■ The following command removes all mod1 instances from all modules:

remove mod1 -INS_Module -ALL // remove inst1, inst4

Related Commands

REPORT REMOVED INSTANCE



REPORT ABSTRACT MODELREPort ABSTract Model

[-ALL | -MODule <module_name>][-Both | -Golden | -Revised](Setup / LEC Mode)


If you used SET ABSTRACT MODEL command to abstract transistor logic from particularmodules, this reports their abstraction conditions.

Parameters

Related Commands

ABSTRACT LOGIC


SET ABSTRACT MODEL

-All Reports abstraction conditions for all modules.

-MODule module_name…

Reports abstraction conditions for the specified modules.

-Both Reports abstraction conditions for both the Golden and Reviseddesigns. This is the default.

-Golden Reports abstraction conditions for the Golden design.

-Revised Reports abstraction conditions for the Revised design.



REPORT ALIASREPort ALias

[name*]…(Setup / LEC Mode)

Displays a list of all or specified aliases you created with the ADD ALIAS command.

Wildcard: The wildcard (*) represents any zero or more characters in alias names.

Parameters

Related Commands

ADD ALIAS

DELETE ALIAS

name*… Reports the specified alias.



REPORT BLACK BOXREPort BLack Box

[-Module |-Instance][-DETail][-Class <Full | User | System | UNDefined | UNSupported | EMPty | NOTranslate>][-HIER | -NOHIER][-HIDden | -NOHIDden][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays blackboxes from the Golden and Revised designs. The blackboxes either alreadyexisted in the design, or you previously added them with the ADD BLACK BOX command.

Parameters

-Module Reports only the blackbox modules. This is the default.

-Instance Reports only the blackbox instances.

-DEtail Displays details about blackboxes, where:

■ USER—Indicates that the blackbox was added by theADD BLACK BOX command.

■ SYSTEM (undefined)—Indicates that the blackbox was addedby the SET UNDEFINED CELL blackbox command.

■ SYSTEM (unsupported)—Indicates that the module containsunsupported statements.

■ SYSTEM (empty)—Indicates that the module contains no logic.

■ SYSTEM (notranslate)—Indicates that the blackbox wasadded by the ADD NOTRANSLATE MODULES command.

-Class Displays the specified class of blackboxes.

Full Blackboxes from both the User and Systemclasses. This is the default.

User Blackboxes previously added with the ADDBLACK BOX command.

System Blackboxes included in the original design.

UNDefined Blackboxes for undefined modules.

UNSupported Blackboxes for unsupported modules.



Related Commands

ADD BLACK BOX

DELETE BLACK BOX

EMPty Blackboxes for empty modules.

NOTranslate Blackboxes for notranslate modules.

-HIER Displays the hierarchical blackboxes. This is the default.

-NOHIER Does not display the hierarchical blackboxes.

-HIDden Displays all blackbox instances in the design hierarchy includingthose contained within other blackboxes. This is the default.

-NOHIDden Does not display blackbox instances that are contained within otherblackboxes.

-Both Displays blackboxes from both the Golden and Revised designs.This is the default.

-Golden Displays blackboxes from the Golden design.

-Revised Displays blackboxes from the Revised design.



REPORT CLOCKREPort CLock

[-Both | -Golden | -Revised](Setup / LEC Mode)

Reports all clocks from the Golden and Revised designs that were added with the ADDCLOCK command.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE


DELETE CLOCK



READ PATTERN




-Both Displays all added clocks from both the Golden and Reviseddesigns. This is the default.

-Golden Displays all added clocks from the Golden design.

-Revised Displays all added clocks from the Revised design.



RESOLVE



REPORT COMMAND PROFILEREPort COmmand PRofile

[-Summary | -Detail](Setup / LEC Mode)

Displays a profile of all of the commands you executed after you used SET COMMANDPROFILE with the -on option. (The default setting for SET COMMAND PROFILE is -off.)

The profile report includes the order in which commands were executed and the memory use.The profile includes commands that were executed in the GUI mode.

Parameters

Related Commands

SET COMMAND PROFILE

SET LOG FILE

-SUMmary Lists a summary table of all of the commands in alphabeticalorder. This is the default.

-Detail Lists all commands in order of execution.



REPORT COMPARE DATAREPort COmpare Data

[-CLASS <EQuivalent | INVequivalent | NONEQuivalent| ABort | NOTcompared | SYStem | USEr | FULL| INSTance_eq | OUTput_eq | PIN_eq>…][-Type <PO | DFF | DLAT | BBOX | CUT >…][-Verbose | -SUMmary]|<identifier> [-INSTance_eq <identifier>|-OUTput_eq <identifier> | -PIN_eq <identifier>]

[-Golden |-REvised][-noreport_bbox_input | -report_bbox_input](LEC Mode)

Displays a list of all or specified compared points. If no options are specified, Conformalidentifies all equivalent and nonequivalent compared points and displays a summary.

The compared points are listed in pairs of rows with three fields in each row. The first row ineach pair represents the Golden design. The second row in each pair represents the Reviseddesign. The three fields in each row are:

■ First–the gate identification number

■ Second–the gate type

■ Third–the instance path or pin path

Parameters

-CLASS class_type…

Displays the specified class of compared points:

EQuivalent

INVequivalent

Inverted-equivalent points

NONEQuivalent

Nonequivalent points

ABort Aborted points

NOTcompared All points not compared

SYStem Automatically mapped points

USEr User-mapped points



FULL Both automatically-mapped anduser-mapped points

INSTance_eq Equivalent instances

OUTput_eq Equivalent outputs

PIN_eq Equivalent pins

-TYPE compared_points_type…

Displays the specified type of compared points:

PO Primary output

DFF D flip-flop

DLAT D-latch

BBOX Blackbox

CUT Compared points with artificial gates tobreak combinational loops

-Verbose Displays all compared points. This is the default.

-SUMmary Lists a summary report of the compared points.

identifier Lists compared points for the specified gate ID or path.


-INSTance_eq <identifier>

Displays compare data for a pair of instances previouslyidentified with the ADD INSTANCE EQUIVALENCE command.


-OUTput_eq <identifier>

Displays compare data for a pair of outputs previously identifiedwith the ADD OUTPUT EQUIVALENCES command.


-PIN_eq <identifier>



Examples


Related Commands

COMPARE

DIAGNOSE

PROVE

REPORT STATISTICS

REPORT COMPARE TIME

Display compare data for a pair of pins previously identified withthe ADD PIN EQUIVALENCE command.


-Golden The specified identifiers are from the Golden design. This isthe default.

-REvised The specified identifiers are from the Revised design.

-noreport_bbox_input

Does not report the blackbox input pins in the compare reportresults. This is the default.

-report_bbox_input Report the blackbox input pins in the compare report results(Equivalent, Non-equivalent, Abort, and Not-compared).



REPORT COMPARE TIMEREPort COmpare TIME

[-SORT][-MAX n][-RTLINFO][-ABORT_ONLY][-GOLD g][-REVI r][-ENABLE][-DISABLE](LEC Mode)

Reports the CPU time consumed during a comparison.

You must enable this feature before starting a comparison; otherwise, Conformal does notrecord any information.

For example:

compare

report compare time -enable

compare

report compare time

In this example, Conformal records the CPU time for the second comparison only.

Note: Conformal does not record compare time for trivial cones.

Parameters

-SORT Sorts the information based on the recorded CPU time.

-MAX n Specifies the maximum number, denoted by n, of key points toreport.

-RTLINFO Reports RTL information inside the cone.

-ABORT_ONLY Report only the abort points.

-GOLD g and -REVI r

Specifies particular key points to report. If you do not specify theseoptions, Conformal reports all key points.

-ENABLE Use this option to start recording CPU time. If you do not set thisoption before your comparison, Conformal does not record CPUtime.



Examples

The following demonstrates how to use this command with other commands.

Note: Use these steps after you read in your library and design files.

1. Add your compare points.

LEC > add compared points -all// 3113 compared points added to compare list

2. Enable the report compare time feature.

LEC> report compare time -enable

3. Start your comparison.

LEC> compare================================================================================Compared points PO DFF DLAT BBOX Total--------------------------------------------------------------------------------Equivalent 123 2983 2 5 3113================================================================================// Warning: 1 DFFs/DLATs have 1 disabled clock port: skipped data cone comparison

4. Report the compare time. In this example, Conformal sorts the information based onCPU time and only reports RTL information within the cone.

LEC>report compare time -sort -rtlinfo

CPU Time Used: 5.29, Result: Equivalent:(G) + 536 DFF /cpu_core/CPU/cpu_dp/alu/v_alo_1l_reg[30](R) + 1284 DFF /cpu_core$CPU$cpu_dp$alu$v_alo_1l_reg_30_/U$1/U$1RTL modules at Golden:RTL modules at Revised:

CPU Time Used: 4.64, Result: Equivalent:(G) + 533 DFF /cpu_core/CPU/cpu_dp/alu/o_alvo_1l_reg(R) + 1364 DFF /cpu_core$CPU$cpu_dp$alu$o_alvo_1l_reg/U$1/U$1RTL modules at Golden:RTL modules at Revised:

...

Related Commands

ADD COMPARED POINTS

COMPARE

-DISABLE Disables the recording of CPU time.



REPORT COMPARE DATA



REPORT COMPARED POINTSREPort COmpared Points

[-SUMmary | -PO | -DFf | -DLat | -Bbox | -Cut](LEC Mode)

Displays the compared points that were added with the ADD COMPARED POINTS command.

Refer to the sample report shown below. The first row represents the Golden design; thesecond row represents the Revised design. It also shows a tabulated summary of thecompared points for each design. This report includes the total number of compared pointsfor primary outputs, D flip-flops, D-latches, blackboxes, and cut gates.

If you do not specify any options, Conformal lists all added compared points, and a tabulatedsummary appears at the end of the list. However, if you use the -summary option, Conformaldisplays only the tabulated summary.

Parameters

Related Commands

ADD COMPARED POINTS

COMPARE


REPORT STATISTICS

-SUMmary Lists a summary table of all of the added compared points inthe Golden and Revised designs. (Refer to the sample reportgiven below.) This is the default.

-PO Lists all primary output compared points.

-DFf Lists all D flip-flop compared points.

-DLat Lists all D-latch compared points.

-Bbox Lists all blackbox compared points.

-Cut Lists all compared points for artificial gates that breakcombinational loops.



REPORT CPF LOGICREPort CPf Logic

[-ISOlation][-Level_shifter][-RETention][-Verbose](Setup / LEC Mode)


Reports the low power cells that were inserted by the Conformal Low Power software.

Parameters

Note: By default, this command reports all inserted low power cell types.

Example

The following commands read the lib.cpf and design.cpf files, performs low power cellinsertion, and reports only the interted isolation and level-shifter cells:

read cpf lib.cpf design.cpf

commit cpf -insert

report cpf logic -isolation -level_shifter

Related Commands

COMMIT CPF

READ CPF

-ISOlation Reports the inserted isolation cells only .

-Level_shifter Reports the inserted level-shifter cells only .

-RETention Reports the inserted state retention cells only .

-VERbose Reports detailed information of each defined CPF cell, includingcell types and rules that triggered this cell to be inserted in thedesign.



REPORT CUT POINTREPort CUt Point


Displays all cut points from the Golden and Revised designs that were added with the ADDCUT POINT command.

Parameters

Related Commands

ADD CUT POINT

DELETE CUT POINT

REPORT PATH

-Both Lists all cut points in both the Golden and Revised designs.This is the default.

-Golden Lists all cut points in the Golden design.

-Revised Lists all cut points in the Revised design.



REPORT DATAPATH OPTIONREPort DAtapath Option

(Setup / LEC Mode)

Displays current data path option settings.

Related Commands

ANALYZE DATAPATH

ANALYZE MULTIPLIER


SET DATAPATH OPTION


SET FLATTEN MODEL



REPORT DATAPATH RESOURCEREPort DATapath REsource

[-Verbose][-Analyzed][-Type <MULT | ADD | SUB | MERGED>](LEC Mode)

Displays information about data path resources from the Golden and Revised designs.

Parameters

Related Commands

ANALYZE DATAPATH

ANALYZE MULTIPLIER

REPORT DESIGN DATA

-Verbose Provides additional information, such as filename and linenumber.

-Analyzed Provides information only for resources analyzed by ANALYZEDATAPATH command.

-Type Provides information only for resources of the specified type.Choose one of the following:

■ MULT — multipliers

■ ADD — adders

■ SUB — subtractors

■ MERGED — merged operators



REPORT DESIGN DATAREPort DEsign Data

[module_name][-Summary | -Verbose][-NOKey_point | -Key_point][-Extra <INPut | Output | INOut>][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays design data on the Golden and Revised designs. It displays the number of designmodules, library cells, inputs, outputs, primitives, and one-to-one mapped state points.

This report includes word-level information about the design in terms of the number ofarithmetic/keyword operations. This report includes data path elements such as WMUX,WAND, WXOR and other word-level representations of Boolean logic. It displays simplerrepresentations of data path logic that may need to be separated out for the comparisonprocess.

Use Control-C to interrupt the key point listing if you find that the report is too long.

Parameters

module_name Reports design data for the named module. By default, theConformal software reports design data on the top root designmodule.

-Summary Summarizes the design data for the total number of thefollowing:

■ Design modules

■ Library cells

■ Inputs

■ Outputs

■ Primitives




Report Design Data

Figure 2-1 is an example of the default design data report.

-Verbose Reports a detailed list of the design’s total number of:

■ Design modules

■ Each different library cell

■ Inputs

■ Outputs

■ Each different primitive

-NOKey_point Does not report the total one-to-one mapped state points. Thisis the default.

-Key_point Reports the total one-to-one mapped state points.

Note: If you use the -verbose option in conjunction with thisoption, Conformal reports all one-to-one mapped state points.Otherwise, Conformal reports the total in summary.

-Extra Reports the extra input, output, or I/O pins for pair-able modulesbetween the Golden and Revised designs.

INPut Specifies input pins.

Output Specifies output pins.

INOut Specifies inout pins.

-Both Report design data on both the Golden and Revised designs.This is the default.

-Golden Report design data on the Golden design.

-Revised Report design data on the Revised design.



Figure 2-1 Design Data Report

Related Commands

READ DESIGN

READ LIBRARY




REPORT DESIGN SIMILARITYREPort DEsign SIMilarity

[-INStance <instance_name*>][-GOLDen | -REVised](LEC Mode)

Displays the similarity degree of a design with reference to the other netlist. The similarity ismeasured by the number of corresponding points in the two designs. The value of similarityranges from 0% to 100%. If the two designs are identical in structure, the similarity degree is100%.

Parameters

Examples

■ The following command displays the similarity of the Golden design’s netlist. TheRevised design’s netlist is used for reference.

report design similarity

■ The following command displays the similarities of the instances whose name beginswith mult in the Golden design’s netlist:

report design similarity -instance mult*

Related Topic

Reporting Design Similarities

-INStance <instance_name*>

Displays the similarity degree of the netlist inside the specifiedinstance. The similarity is evaluated with reference to the othernetlist.

If no instance is specified, the similarity is for the entire design.

-Golden Specifies that the similarity evaluation is performed on theGolden design. The Revised netlist is used for reference. Thisis the default.

-Revised Specifies that the similarity evaluation is performed on theRevised design. The Golden netlist is used for reference.



REPORT DYNAMIC CONSTRAINTSREPort DYnamic Constraints

[-Both | -Golden | -Revised](LEC Mode)

Displays all of the dynamic constraints you added to the Golden and Revised designs withthe ADD DYNAMIC CONSTRAINTS command.

Parameters

Examples


Related Commands


COMPARE


PROVE

-Both Lists all dynamic constraints in both the Golden and Reviseddesigns. This is the default.

-Golden Lists all dynamic constraints in the Golden design.

-Revised Lists all dynamic constraints in the Revised design.



REPORT ECO CELLREPort ECo Cell

[-FReedcell][-SParecell](Setup Mode)

Reports the spare cells or freed cells available for the MAP ECO PATCH command.

Parameters

Related Commands

ADD ECO CELL

MAP ECO PATCH

-FReedcell Reports only the freed cells.

-SParecell Reports only the spare cells.



REPORT ECO CHANGESREPort ECo Changes

[-MODule <module_name>][-SUMmary](Setup Mode)

Reports the ECO changes. To report the ECO change with this command, the ECOs musthave been applied with the APPLY PATCH or OPTIMIZE DESIGN command.

Parameters

Related Commands

WRITE ECO DESIGN

-MODule <module_name>

Specifies the module to report. By default, the commandreports all nets and instances that have been added anddeleted.

-SUMmary Shows a summary only.



REPORT ECO PATCHREPort ECo PAtch

(Setup Mode)

Reports the ECO patch specified by the ADD ECO PATCH command.

Related Commands

ADD ECO PATCH

DELETE ECO PATCH



REPORT ENVIRONMENTREPort ENvironment

[-Setup | -MOdeling | -MApping | -COMpare | -Diagnosis | -FUnctiondefault](Setup / LEC Mode)

Displays global settings for the Golden and Revised designs and system settings.

Parameters

Environment Report

Figure 2-2 is an example of the default environment report (no options were added).

-Setup Reports environment related to Setup. This is the default.

-MOdeling Reports environment related to Modeling.

-MApping Reports environment related to Mapping.

-COMpare Reports environment related to Compare.

-Diagnosis Reports environment related to Diagnosis.

-FUnctiondefault Reports environment related to the default return value.



Figure 2-2 Environment Report

Related Commands

SET CASE SENSITIVITY

SET COMPARE EFFORT

SET CPU LIMIT

SET FLATTEN MODEL



SET GATE REPORT

SET IMPLEMENTATION

SET LOG FILE

SET MAPPING METHOD

SET NAMING RULE

SET ROOT MODULE

SET SCREEN DISPLAY

SET SYSTEM MODE

SET UNDEFINED CELL

SET UNDRIVEN SIGNAL

SET WIRE RESOLUTION

SET X CONVERSION



REPORT FLOATING SIGNALSREPort FLoating Signals

[-ROot | -Module <name> | -All][-UNDriven | -UNUsed] [ |-Net | -Pin][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays all floating signals in the Golden and Revised designs or in specified modules of adesign. The reported floating signals are either nets or pins and are either undriven orunused. Use the SET UNDRIVEN SIGNAL command to specify the global behavior of theundriven floating signals in the Golden and Revised designs.

Parameters

-ROot Displays all of the floating signals in the root module. This isthe default.

-Module name Displays “all” the floating signals in the specified modulewithin the given defaults.

-All Displays “all” the floating signals in “all” design moduleswithin the given defaults.

-UNDriven Displays only undriven floating signals. This is the default.

-UNUsed Displays only unused floating signals.

-Net Displays only floating nets.

If you do not specify -net or -pin, Conformal displaysboth floating nets and floating pins.

-Pin Displays only floating pins.

If you do not specify -net or -pin, Conformal displaysboth floating nets and floating pins.

-Both Displays floating signals from both the Golden and Reviseddesigns. This is the default.

-Golden Displays floating signals from the Golden design.

-Revised Displays floating signals from the Revised design.



Related Commands

ADD TIED SIGNALS

SET UNDRIVEN SIGNAL



REPORT GATEREPort GAte

[<identifier>[-INStance | -Pin | -Net | -ID][-Golden | -Revised][-SUPport][-FRONTIER][-FANIn <integer>][-FANOut <integer>][-UNReach][-SHORT_list | -NOSHORT_list][-SOURCE][-Collapse][-NODYNamic | -DYNamic][-INDent <integer>]][-Type <PI | 0 | 1 | E | Z | BBOX | DFF | DLAT | CUT | OUT | COMB | PO>][-RETention][-CORRespondence][-SUMmary](Setup / LEC Mode)

Displays flattened gate information. By default, it reports the gate ID, type, name, and itsfanins and fan-outs at the primitive level. After you specify options for the initial report, use theREPORT GATE command without options to generate a report on the same gates, or specifynew options as needed.

Important

ID numbers can differ from one version of Conformal to another. Always use the fullpath in dofiles and any time you rerun a design with a different Conformal version.

Parameters

identifier If you do not specify one of the following options, Conformalautomatically determines if the identifier is a number or a path.In the case of a number, Conformal uses the -id option;otherwise, Conformal searches for the gate with the-instance, -pin, or -net option; in this respective order.

-INStance Instance pathThis is the default.

-Pin Pin path

-Net Net path



-ID Gate identification number



-Golden The identifier is in the Golden design. This is the default.

-Revised The identifier is in the Revised design.

-SUPport Reports the supported key points from the fanin cone.

-FRONTIER Reports the frontier key points from the fan-out cone.

-FANIn integer Reports this number of levels in the fanin cone. The defaultvalue is 0.

-FANOut integer Reports this number of levels in the fan-out cone. The defaultvalue is 0.

-UNReach Displays diagnosis information for unmapped points that wereclassified as unreachable.

-SHORT_list Lists the first and last 20 gates of a long display list. This is thedefault.

-NOSHORT_list Displays the entire display list.

-SOURCE Reports the gate information and the following locationinformation:

■ Module name

■ Instance name

■ Filename

■ Source line

-Collapse Does not report inverters and buffers in the fanin cone. Thedefault is to report all inverters and buffers in thefanin/fan-out cone.

-NODYNamic Use this option in conjunction with the -fanin option.

The fanin cone does not stop at a gate with dynamicconstraints. This is the default.



-DYNamic Use this option in conjunction with the -fanin option. Thefanin cone stops at the gate with dynamic constraints.

-INDent integer Displays this amount of whitespace when reporting the faninand fan-out cones. The default value is 2.

-Type gate_type Reports all gates with the specified gate type. The availablegate types are as follows:

PI Primary inputs

0 TIE-0 gates

1 TIE-1 gates

E TIE-E gates

Z TIE-Z gates

BBOX Blackboxes

DFF D flip-flops

DLAT D-latches


OUT Artificial gates for the multiple outputs ofblackboxes

COMB Combinational gates

PO Primary Outputs

-RETention Note: This is a Conformal Low Power option.

If the gate is a sequential element (DFF or DLAT) and belongsto the Golden Design, this option reports the tag-name (if any)associated with the DFF or DLAT. If the gate is a sequentialelement (DFF or DLAT) and belongs to the Revised Design, thisoption reports the power gating cell attribute (if any) associatedwith the DFF or DLAT. For non-sequential elements, nothing isreported.

-CORRespondence Reports the correspondence gates in the other (Golden orRevised design) netlist. The correspondence gate is potentiallyequivalent with the gate specified in this command. Use thePROVE command to formally prove the equivalence.

-SUMmary Reports gate type statistics. The default is not to report thestatistics.



Related Commands

BACKWARD

CHANGE GATE TYPE

FORWARD

REPORT PATH

SET GATE REPORT



REPORT HIER_COMPARE RESULTREPort HIer_compare Result

[-Summary | -Equivalent | -NONEQuivalent | -Abort| -UNcompared | -FLattened | -DYNamicflattened| -EXTRA_po | -ALL]

[-USage](Setup / LEC Mode)

Displays the results of the hierarchical comparison. If the WRITE HIER_COMPARE DOFILEcommand is used, this command is automatically placed at the end of the hierarchical dofilescript. It lists the summary results and any modules that are nonequivalent, aborted, oruncompared.

Parameters

-Summary Displays a summary table of the hierarchical comparisonresults. This is the default.

-Equivalent Displays only the hierarchical modules that are equivalent.

-NONEQuivalent Displays only the hierarchical modules that are nonequivalent.

-Abort Displays only the hierarchical modules that had abort keypoints.

-UNcompared Displays only the hierarchical modules that are not compared.

-FLattened Displays only the hierarchical modules that were found to benonequivalent and, as a result, were flattened.

Use this option when you have used write hier_comparedofile -conditional

-DYNamicflattened Displays only the hierarchical modules that were either found tobe non-equivalent, or were equivalent but causednon-equivalence at the parent level, and were automaticallyflattened.

Use this option when performing hierarchical comparison withthe RUN HIER_COMPARE command.

-EXTRA_po Displays only the hierarchical modules that have extra(not-mapped) primary outputs.

-ALL Displays the results of all of the modules.

-USage Displays the CPU use time for each module comparison.



Related Commands

RESET HIER_COMPARE RESULT

RUN HIER_COMPARE

SAVE HIER_COMPARE RESULT




REPORT IGNORED INPUTSREPort IGnored Inputs

[-ROot | -Module <name> | -All][-Both | -Golden | -REvised](Setup / LEC Mode)

Displays the input pins, which were added as ignored inputs, in the Golden and Reviseddesigns. These pins were originally specified with the ADD IGNORED INPUTS command.

Parameters

Related Commands

ADD IGNORED INPUTS

DELETE IGNORED INPUTS

-ROot Displays only the input pins in the root module. This is thedefault.

-Module name Displays only the ignored input pins in the named module.

-All Displays “all” ignored input pins in all modules.


-Both Displays both the Golden and Revised added ignoredinputs. This is the default.

-Golden Displays the added ignored inputs from the Golden design.

-REvised Displays the Revised ignored inputs.



REPORT IGNORED OUTPUTSREPort IGnored Outputs


Displays the output or I/O pins, which were added as ignored outputs, in the Golden andRevised designs. These outputs were originally specified with the ADD IGNORED OUTPUTScommand.

Parameters

Related Commands

ADD IGNORED OUTPUTS

DELETE IGNORED OUTPUTS

-ROot Displays only the input pins in the root module. This is thedefault.

-Module name Displays only the ignored output or I/O pins in the specifiedmodule.

-All Displays “all” ignored input pins in all modules.


-Both Displays both the Golden and Revised added ignoredoutputs. This is the default.

-Golden Displays only the Golden added ignored outputs.

-REvised Displays only the Revised ignored outputs.



REPORT INSTANCE ATTRIBUTEREPort INstance Attribute

[-ROot | -Module <name> | -All][-Summary | -Verbose][-Both | -Golden | -REvised](Setup Mode)

Displays the attributes placed on instances in the Golden and Revised designs. Theseattributes were originally specified with the ADD INSTANCE ATTRIBUTE command.

Parameters

Related Commands

ADD INSTANCE ATTRIBUTE

DELETE INSTANCE ATTRIBUTE

-ROot Displays only the added instance attributes in the rootmodule. This is the default.

-Module name Displays only the added instance attributes in the specifiedmodule.

-All Displays “all” added instance attributes within the givendefaults.

-Summary Displays a summary message of the total number of addedinstance attributes. This is the default.

-Verbose Displays all added instance attributes.

-Both Displays the added instance attributes in both the Goldenand Revised designs. This is the default.

-Golden Displays the added instance attributes in the Golden design.

-REvised Displays the added instance attributes in the Reviseddesign.



REPORT INSTANCE CONSTRAINTSREPort INstance Constraints


Displays the constraints placed on instances in the Golden and Revised designs. Theseconstraints were originally specified with the ADD INSTANCE CONSTRAINTS command.

Parameters

Related Commands

ADD INSTANCE CONSTRAINTS

DELETE INSTANCE CONSTRAINTS

-Both Displays the instance constraints in both the Golden andRevised designs. This is the default.

-Golden Displays the instance constraints in the Golden design.

-Revised Displays the instance constraints in the Revised design.



REPORT INSTANCE EQUIVALENCESREPort INstance Equivalences


Displays the equivalences placed on instances in the Golden and Revised designs. Theseequivalences were originally specified with the ADD INSTANCE EQUIVALENCES command.

Parameters

Related Commands


DELETE INSTANCE EQUIVALENCES

-Both Displays the instance equivalences in both the Golden andRevised designs. This is the default.

-Golden Displays the instance equivalences in the Golden design.

-Revised Displays the instance equivalences in the Revised design.



REPORT KEY POINTREPort KEy Point

[[-TYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO> ...| -NOTYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO> ...]| -Mapped | -UNMapped | -UNReached]

[-PROPerty][-DC][-Golden | -REVised](Setup / LEC Mode)

Report key points in the design.

Parameters

-TYpe

-NOTYpe

Displays all key points with the specified type.

Displays all key points except the specified type.

The available types are as follows:

PI Primary inputs

E TIE-E gates

Z TIE-Z gates

DFf D flip-flops

DLat D-latches

CUt Artificial gates for breaking combinationalfeedback loops

BBox Blackboxes

PO Primary Outputs

-Mapped Displays all mapped key points in the design.

-UNMapped Displays all unmapped key points in the design.

-UNReached Displays diagnosis information for unmapped key points thatwere classified as unreachable.

-PROPerty Displays support and fan-out key points for each key point

-DC Displays the number of DC gates in the compare cone

-Golden Specifies that the report applies only to the Golden design.This is the default.



Related Commands

MAP KEY POINTS

-Revised Specifies that the report applies only to the Revised design.



REPORT LIBRARY DATAREPort LIbrary Data

[-Source][-SORT <NAME | REFerence | INStance>][-SKIP_Unref][-Golden | -Revised](Setup / LEC Mode)

Displays the following columns:

■ ID—Specifies the cell ID.

■ Name—Specifies the cell name.

■ Cost—Specifies the cost of each library cell, which is the product of the number ofinstances of primitive gates within each library cell (Ins) and the number of times thelibrary cell is instantiated (Ref).

■ Ins—Displays the number of instances of primitive gates within each library cell.

■ Ref—Displays the number of times the library cell is referenced in the design.

■ TOT—Displays the total number of gates per library cell.

This total is calculated by Ins times Ref. If Ins is 3 and Ref is 3, the total is 9. If Ins is 3and Ref is 0, the total is 0.

■ DFF—Specifies whether the cell contains a D flip-flop.

■ DLAT—Specifies whether the cell contains a D-latch.

■ BUF—Specifies whether the cell contains a buffer.

■ NOT—Specifies whether the cell contains an inverter gate.

■ BBOX—Specifies whether the cell contains a blackbox.

■ UDP—Specifies whether the cell is a UDP.

By default, Conformal reports on the library for the Golden design if you do not specifyoptions.

Note: When you read in a library, you can specify whether it is for the Golden or Reviseddesign.



Parameters

Related Commands

READ LIBRARY

READ DESIGN

REPORT DESIGN DATA

-SOURCE Displays the source filename and line number for each cell.

-SORT Sorts report data as specified:

NAME Sorts report data alphabetically by librarycell name.

REFerence Sorts report data according to the Referencecolumn, in descending order.

INStance Sorts report data according to the Instancecolumn in descending order.

-SKIP_Unref Does not display unreferenced library modules.

-Golden Displays the library data for the Golden design. This is thedefault.

-Revised Displays the library data for the Revised design.



REPORT LOWPOWER CELLSREPort LOwpower Cells

[-Module | -Instance][-Summary](Setup / LEC Mode)


Reports the low power cells used in the design.

Parameters

Related Commands

ADD LOWPOWER CELLS




SET LOWPOWER OPTION

-Module Reports only the modules with low power cells. This is the default.

-Instance Reports only the instances with low power cells.

-Summary Displays a summary of low power cells.



REPORT LOWPOWER DATAREPort LOwpower Data

[-STatus <All | Pass | Fail | Notcheck>][-TYpe [All | Retention_cell_check [ -Rule <rulename>]| Isolation_cell_check| Level_shifter_cell_check| POWER_domain_check]

][-SUMmary | -Verbose](LEC Mode)


Reports the low power data. These are the results of the low power check performed on lowpower cells using the CHECK LOWPOWER CELLS command.


Parameters

-STatus Specifies the status reporting.

For retention-register cell types, the -STatus arguments are describedas follows:

-All Reports all the sequential pairs (LEC mapped points) thatpassed or failed the default rule or user rule. This is thedefault.

-Pass Reports all the sequential pairs that passed the default ruleor user rule.

-Fail Reports all the sequential pairs that failed the default rule oruser rule.

Notcheck

Reports the sequential pairs that were not checked forretention-register consistency

For isolation and level-shifter cell types, the -STatus arguments aredescribed as follows:

-All Reports all the low power cut gates that passed or failed thetechnology mapping check. This is the default.



-Pass Reports all the low power cut gates that passed thetechnology mapping check.

-Fail Reports all the low power cut gates that failed the technologymapping check.

Notcheck

Reports the low power cut gates that were not checked forisolation and level-shifter consistency.

For the power domain consistency check, the -STatus arguments aredescribed as follows:

All Reports all the mapped sequential points that passed andfailed the power domain consistency check

Pass Reports the mapped sequential points that passed the powerdomain consistency check.

Fail Reports the mapped sequential points that failed the powerdomain consistency check.

Notcheck

Reports the mapped sequential points that were not checkedfor power domain consistency

-TYpe Specifies the module type reporting.

-All Reports on all low power cells. This is the default.

-Retention [-Rule <rulename>]

Reports on only the low power state retention cells.

-Rule <rulename> reports all the sequential pairs thatpassed or failed the specified rulename.

-Isolation_cells

Reports on only the low power isolation cells.

-Level_shifter_cells

Reports on only the low power level-shifter cells.

-POWER_domain_check

Reports the results of power domain consistency check forthe mapped sequential points.



Related Commands

ADD LOWPOWER CELLS




SET LOWPOWER OPTION

-SUMmary Displays the status summary of the check performed on low power cells.This is the default.

-Verbose For state retention cells, this reports the sequential pairs (LEC mappedpoints) that passed or failed the default rule or user rule. For each passedor failed sequential pair, the corresponding rule it passed or failed on isalso reported. In addition, this reports any tag-name for the sequentialelement in the Golden Design, and any power gating cell attribute for thesequential element in the Revised Design.

For isolation cells and level-shifter cells, this reports the PASS or FAILstatus of low power cut gates that correspond to the isolation cells andlevel-shifter cells.



REPORT MAPPED POINTSREPort MApped Points

[< gate_id |instance_pathname* | pin_pathname*>…| [ -TYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO>…| [ -NOTYpe < PI | E | Z | DFf | DLat | CUt| BBox | PO>…]

[-INVert_mapped] | -SUMmary][-LOng][-CLass <Full | System | User>][-INput][-OUTput][-GRoup][-REName][-Golden | -REVised][-RETention][-METHOD][-RENAME][-UNReachable](LEC Mode)

Displays the mapped points that were automatically identified or added with the ADD MAPPEDPOINTS command. Each mapped point from the Golden and Revised design is displayedalong with a summary of all Golden and Revised mapped points.

The summary includes the total number of primary inputs, primary outputs, D flip-flops,D-latches, TIE-Es, TIE-Zs, blackboxes, and cut gates.

If no options are entered, the command default is to display both the User and Systemclasses of mapped points.

Wildcard: The wildcard (*) represents any zero or more characters in instance or pin pathsof mapped points.

Parameters

gate_id… Reports the mapped points for the identified gate.


instance_pathname* Reports the mapped points for the named instance path(s).




pin_pathname* Reports the mapped points for the named pin path(s).


-Type mapped_point_type

Displays all mapped points with the specified type. Theavailable types are as follows:

PI Primary Inputs

E TIE-E mapped points

Z TIE-Z mapped points

DFF D flip-flops

DLAT D-latches


BBOX Blackboxes

PO Primary Outputs

-NOType mapped point_type

Does not display mapped points with the specified type. Theavailable types are as follows:

PI Primary Inputs

E TIE-E mapped points

Z TIE-Z mapped points

DFF D flip-flops

DLAT D-latches


BBOX Blackboxes

PO Primary Outputs

-INVert_mapped Displays all mapped points with inverted mapping.

-SUMmary Displays a table summary of the mapped points in the Goldenand Revised designs.

-LOng Displays pairs of mapped points on separate lines.



-INput Displays the input port mapping pairs of the specified DFF,DLAT, or blackbox gate.

-Class Displays the following class of mapped points.

Full Mapped points from both the User andSystem classes. This is the default.

System Mapped points from the original design.

User Mapped points added with the ADD MAPPEDPOINTS command

-OUTput Displays the output port mapping pairs of the specified blackboxgate.

-GRoup Displays the mapping pairs in which either the Golden orRevised key point is a group of equivalent gates rather than asingle gate.

The group can be defined with the ADD INSTANCEEQUIVALENCE command or the -seq_merge option of theSET FLATTEN MODEL command.

A key point group is counted as one key point.

-REName Lists the keypoint with renaming rules applied to the names.

-Golden The mapped points are from the Golden design. This is thedefault.

-REVised The mapped points are from the Revised design.


If the mapped point is a sequential pair (DFF or DLAT pair), thisoption reports the status of the mapped point (Pass, Fail, orUnknown) in accordance with the state retention mapping rules.This also reports the tag-name (if any) associated with theGolden DFF or DLAT and the power gating cell attribute (if any)associated with the Revised DFF or DLAT. For non-sequentialelements, nothing is reported.

-METHOD Shows the method used in mapping the keypoints.

-RENAME Displays the keypoints with renaming rules applied to theirnames.

-UNReachable Lists unreachable keypoints. Unreachable key points are thosethat do not eventually affect the primary output of the design.



Related Commands

ADD MAPPED POINTS


MAP KEY POINTS

REPORT STATISTICS


SET MAPPING METHOD

SET NAMING RULE



REPORT MESSAGESREPort MEssages

[-MOdeling | -MAPping | -Compare][-RUle <rule_name>][-Summary | -Verbose][-NOSORT | -SORT][-Both | -Golden | -REvised](Setup / LEC Mode)

Displays either a summary or complete list of the warning messages that come from themodeling, mapping, or comparison process. (The modeling process occurs when Conformalexits the Setup mode.) A summary of the warning messages is always displayed when themodeling, mapping, or comparison process is in progress; however, this command displayseach individual warning message for the Golden and Revised designs, according to yourspecifications.

See “Modeling Messages” in the Encounter Conformal Equivalence Checking UserGuide for information on the Modeling Messages and the commands/options that triggerthem.

Parameters

-MOdeling Displays only warning messages from the processing andmodeling of the Golden and Revised designs. This is thedefault.

-MAPping Displays warning messages only from the automatic keypoint mapping process.

-Compare Displays warning messages only from the comparisonprocess.

-RUle rule_name Displays only the named rule.

-Summary Displays only a summary message for common warningmessages. This is the default.

-Verbose Displays all warning messages.

-NOSORT Does not sort messages. This is the default.

-SORT Sorts messages alpha-numerically. (Use this option with the-verbose option.)

-Both Displays warning messages that come from both the Goldenand Revised designs and libraries. This is the default.



Related Commands

READ DESIGN

READ LIBRARY

SET FLATTEN MODEL

-Golden Displays warning messages that come from the Goldendesign and library.

-REvised Displays warning messages that come from the Reviseddesign and library.



REPORT MODULE ATTRIBUTEREPort MOdule Attribute

[-ALL | -PIPELINE_Retime | -COMPARE_Effort | -CPU_Limit][-Both | -Golden | -Revised](Setup Mode)

Displays the module attributes in the Golden and Revised designs. These attributes wereoriginally added with the ADD MODULE ATTRIBUTE command.

Parameters

Related Commands


DELETE MODULE ATTRIBUTE

READ DESIGN

READ LIBRARY


-ALL Displays “all” added module attributes within the given defaults.

-PIPELINE_Retime Displays only the modules added for pipeline-retiming.

-COMPARE_Effort Displays only the modules that have specified compare effortlevels.

-CPU_Limit Displays the modules with a specified CPU time limit.

-Both Displays the module attributes for both the Golden and Reviseddesigns. This is the default.

-Golden Displays the module attributes for the Golden design.

-Revised Displays the module attributes for the Revised design.



REPORT MODULESREPort MOdules

[-ROot | module_name [-Up | -Down] | -All | -Top][-Source][-INSTantiation][-USer][-VHDLname][-LEVEL <value>][-Library][-NOINTERLeave |-INTERLeave][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays module information for the Golden and Revised designs. If you specify a module,Conformal displays additional information on modules and library cells up or down thehierarchy of the given module name.

Parameters

-ROot Displays the name of the root module.

module_name Reports module information on the specified module. Anadditional option lets you report on modules and library cellseither up or down the hierarchy of the specified module name.

The default is to report modules and library cells up thehierarchy of the specified module name.

-Up Reports on modules and library cells up thehierarchy of the specified module name.This is the default.

-Down Reports on modules and library cells downthe hierarchy of the specified module name.

-All Displays “all” the modules within the given defaults. The top rootmodule is denoted by (T).

-Top Displays the top modules.

-Source Displays the source-code information identifying where themodule is located.

-Instantiation Displays instances and modules.



Examples

This example shows the difference between running the REPORT MODULES commandwithout any options versus running the command with the -USer option.

The following design file contains only one module named test. ModuleVDW_mult_nbw_u8_u8_16 is internal module which is not defined in this file:

module test(aa, bb, oo);

input [7:0] aa, bb;

output oo;

assign oo = aa * bb;

endmodule

Running the following command:

report modules

the Conformal software reports the test and VDW_mult_nbw_u8_u8_16 modules.However, when running the following command:

report modules -user

-USer Reports only the modules defined in the design files, and skipsthe internal modules which are not defined in the design files.

Note: Some internal modules can be created by the Conformaltools after reading the design files. These internal modules arenot defined in the design files.

-VHDLname Displays the full name, rather than just the entity name.

For example: libname.entityname(architecturename).

-LEVEL value Shows modules in a hierarchical order up to the specified level.

-Library Displays all of the library cells that are in the module hierarchy.

-NOINTERLeave Reports the Golden and Revised module hierarchiesseparately, first list Golden modules, and then list Revisedmodules. This is the default.

-INTERLeave Reports the Golden and Revised module hierarchies together.

-Both Displays information for both the Golden and Revised designs.This is the default.

-Golden Displays module information for the Golden design.

-Revised Displays module information for the Revised design.



the Conformal software reports only the test module.

Related Commands


REPORT PATH



REPORT MOS DIRECTIONREPort MOs Direction

[module_name][-Summary | -Verbose][-BIdirection | -UNidirection ][-Both | -Golden | -Revised](Setup / LEC Mode)


Displays the unidirectional and bidirectional transistor-MOS instances with their source anddrain ports.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE

module_name Reports on the named module.

-Summary Displays a summary message of the total number ofunidirectional and bidirectional transistor-MOS. This is thedefault.

-Verbose Displays all of the unidirectional and bidirectionaltransistor-MOS.

-BIdirection Displays only the bidirectional transistor-MOS instances. Thisis the default.

-UNidirection Displays only the unidirectional transistor-MOS instances.

-Both Displays MOS direction from both the Golden and Reviseddesigns. This is the default.

-Golden Displays MOS direction from the Golden design.

-Revised Displays MOS direction from the Revised design.




DELETE CLOCK



READ PATTERN

REPORT CLOCK



RESOLVE



REPORT MULTIPLIER OPTIONREPort MUltiplier Option

(Setup / LEC Mode)

Displays current multiplier option settings.

Related Commands

ANALYZE DATAPATH

ANALYZE MULTIPLIER


SET DATAPATH OPTION


SET FLATTEN MODEL



REPORT NET ATTRIBUTEREPort NEt Attribute

[-ALL | -VDD | -GND | -CLOCK0 | -CLOCK1 | -DYNSTate][-Module <name>][-Both | -Golden | -Revised]


Displays attributes on transistor-MOS nets. The attributes were originally added with the ADDNET ATTRIBUTE command.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE


-ALL Displays “all” added net attributes within the given defaults.

-VDD Displays only the added VDD net attributes.

-GND Displays only the added GND net attributes.

-CLOCK0 Displays only the added Clock-0 net attributes.

-CLOCK1 Displays only the added Clock-1 net attributes.

-DYNSTate Displays only the added dynamic state net attributes.

-Module name Reports net attributes from the named module.

-Both Displays net attributes from both the Golden and Reviseddesigns. This is the default.

-Golden Displays net attributes from the Golden design.

-Revised Displays net attributes from the Revised design.



DELETE CLOCK



READ PATTERN

REPORT CLOCK



RESOLVE



REPORT NET CONSTRAINTSREPort NEt Constraints


Displays all net constraints in the Golden and Revised designs that were added with the ADDNET CONSTRAINTS command.

Parameters

Related Commands

ADD NET CONSTRAINTS

DELETE NET CONSTRAINTS

-Both Displays added net constraints in both the Golden and Reviseddesigns. This is the default.

-Golden Displays the added net constraints in the Golden design.

-Revised Displays the added net constraints in the Revised design.



REPORT NOBLACK BOXREPort NOblack Box


Displays all of the modules in the Golden and Revised designs that will not be included in thehierarchical dofile script generation. These modules were originally specified with the ADDNOBLACK BOX command.

Parameters

Related Commands

ADD NOBLACK BOX

DELETE NOBLACK BOX


-Both Displays added noblackboxes in both the Golden and Reviseddesigns. This is the default.

-Golden Displays the added noblackboxes in the Golden design.

-Revised Displays the added noblackboxes in the Revised design.



REPORT NOTRANSLATE FILEPATHNAMESREPort NOtranslate Filepathnames

[ | -Library | -Design][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays all of the library and design file pathnames originally added with the ADDNOTRANSLATE FILEPATHNAMES command. The Conformal software will not compile thesemodules defined in libraries and design files.

Parameters

Related Commands

ADD NOTRANSLATE FILEPATHNAMES


DELETE NOTRANSLATE FILEPATHNAMES



-Library Displays only the added library file pathnames.

-Design Displays only the added design file pathnames.

-Both Displays added file pathnames in both the Golden and Reviseddesigns. This is the default.

-Golden Displays the added file pathnames in the Golden design.

-Revised Displays the added file pathnames in the Revised design.



REPORT NOTRANSLATE MODULESREPort NOtranslate Modules

(Setup / LEC Mode)

Displays all of the library and design modules originally added with the ADD NOTRANSLATEMODULES command. Conformal will not compile these modules when reading in libraries anddesigns.

Related Commands



READ DESIGN

READ LIBRARY



REPORT OUTPUT EQUIVALENCESREPort OUtput Equivalences

[-ROot | -Module <name> | -All ][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays the output pin equivalences in the Golden and Revised designs. These output pinequivalences were originally added with the ADD OUTPUT EQUIVALENCES command.

Parameters

Related Commands



-ROot Displays all output pin equivalences from the root module.This is the default.

-Module name Displays the output pin equivalences in the specified module.

-All Displays “all” output pin equivalences in all modules within thegiven defaults.

-Both Displays the output pin equivalences in both the Golden andRevised designs. This is the default.

-Golden Displays the output pin equivalences in the Revised design.

-Revised Displays the output pin equivalences in the Golden design.



REPORT OUTPUT STUCK_ATREPort OUtput Stuck_at

[-ROot |-Module <name> | -All ][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays the output stuck_at values and pin names in the Golden and Revised designs.These output stuck_at values were originally added to pins with the ADD OUTPUTSTUCK_AT command.

Parameters

Related Commands

ADD OUTPUT STUCK_AT

DELETE OUTPUT STUCK_AT

-ROot Displays the output stuck_at values and pin names from theroot module. This is the default.

-Module name Displays the output stuck_at values and pin names from thespecified module.

-All Displays “all” output stuck_at values and pin names in “all”modules within the given defaults.

-Both Displays the output stuck_at values and pin names in boththe Golden and Revised designs. This is the default.

-Golden Displays the output stuck_at values and pin names in theRevised design.

-Revised Displays the output stuck_at values and pin names in theGolden design.



REPORT PARTITION KEY_POINTREPort PArtition Key_point

(Setup / LEC Mode)

Displays the partition key points originally added with the ADD PARTITION KEY_POINTcommand.

Related Commands






REPORT PARTITION POINTSREPort Partition Points

[-Both | -Golden | -Revised][-Verbose | -Summary](LEC Mode)


Displays the partition points that were created with the ADD PARTITION POINTS command.

Parameters

Related Commands

ADD PARTITION POINTS

DELETE PARTITION POINTS

-Both Lists the partition points in both the Golden and Reviseddesigns. This is the default.

-Golden Lists the partition points in the Golden design.

-Revised Lists the partition points in the Revised design.

-Verbose Displays all added partition points. This is the default.

-Summary Displays a summary message of the total number of addedpartition points.



REPORT PARTITION RESULTREPort PArtition Result

(Setup Mode)

Displays the results after running partition dofile.

Related Commands






REPORT PATHREPort PAth

<<source> <destination> | -Feedback | -SELF | -SELF <gate>>[-Source][-NET][-SEQ_ASYNC][-Golden | -Revised](Setup / LEC Mode)

Displays the paths between a source gate and a destination gate. The -feedback optiondisplays all feedback paths for all CUT gates. The source and destination gates can be:

■ Gate ID numbers

■ Instance paths

■ Pin paths

To report the feedback path on one CUT gate, use the same CUT gate ID, instance path, orpin path for both the source and the destination.

Parameters

source Specifies the gate ID number, instance path, or pin path ofthe source gate.

Note: ID numbers can differ from one version of Conformalto another. Always use the full path in dofiles and any timeyou rerun a design with a different Conformal version.

destination Specifies the gate ID number, instance path, or pin path ofthe destination gate.

Note: ID numbers can differ from one version of Conformalto another. Always use the full path in dofiles and any timeyou rerun a design with a different Conformal version.

-Feedback Reports the feedback path of “all” CUT gates.


-SELF [<gate>] Reports all loops to DFF and DLATs. If you specify a gate, itreports only loops to that gate.

-Source Displays the file and line number location of the gate in thepath.



Related Commands

ADD CUT POINT

DELETE CUT POINT

REPORT CUT POINT

REPORT GATE

-NET Displays the corresponding net of the gate in the path.

-SEQ_ASYNC Reports DFF/DLAT to DFF/DLAT paths passing through theasynchronous set or reset of a sequential element.

-Golden Reports the specified path in the Golden design. This is thedefault.

-Revised Reports the specified path in the Revised design.



REPORT PIN CONSTRAINTSREPort PIn Constraints

[-ROot | -Module <name> | -All][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays the constraints placed on primary input pins in the Golden and Revised designs.These constraints were originally specified with the ADD PIN CONSTRAINTS command.

Parameters

Related Commands

ADD PIN CONSTRAINTS

DELETE PIN CONSTRAINTS

-ROot Displays the pin constraints from the root module. This isthe default.

-Module name Displays the pin constraints from the specified module.

-All Displays pin constraints in “all” modules.


-Both Displays the constrained primary input pins from both theGolden and Revised designs. This is the default.

-Golden Displays the constrained primary input pins from the Goldendesign.

-Revised Displays the constrained primary input pins from theRevised design.



REPORT PIN DIRECTIONREPort PIn Direction

[-IO | -IN | -OUT][module_name][-Summary | -Verbose][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays the assigned pin directions for each module. The default is to display only asummary message.

Note: Use the ASSIGN PIN DIRECTION command to assign pin direction to module I/Opins.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE

-IO Reports assigned module I/O pins. This is the default.

-IN Reports assigned module input pins.

-OUT Reports assigned module output pins.

module_name Reports pin direction for the specified module. The defaultis to report pin direction for all modules.

-Summary Displays only a summary message of assigned pindirections. This is the default.

-Verbose Displays all assigned pin directions.

-Both Reports the assigned pin directions in both the Golden andRevised designs. This is the default.

-Golden Reports the assigned pin directions in the Golden design.

-Revised Reports the assigned pin directions in the Revised design.




DELETE CLOCK



READ PATTERN

REPORT CLOCK



RESOLVE



REPORT PIN EQUIVALENCESREPort PIn Equivalences


Displays a list of added pin equivalences and inverted pin equivalences. These pinequivalences were originally added with the ADD PIN EQUIVALENCE command. Invertedpin equivalences are distinguished by a “-” next to the primary input pin name.

Parameters

Related Commands

ADD PIN EQUIVALENCES

DELETE PIN EQUIVALENCES

-ROot Displays pin equivalences from the root module. This is thedefault.

-Module name Displays pin equivalences from the specified module.

-All Displays pin equivalences in “all” modules.


-Both Displays pin equivalences from both the Golden and Reviseddesigns. This is the default.

-Golden Displays pin equivalences from the Golden design.

-REvised Displays pin equivalences from the Revised design.



REPORT PRIMARY INPUTSREPort PRimary Inputs

[-Class <Full | System | User>][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays primary input pins from the Golden and Revised designs.

Parameters

Related Commands

ADD PRIMARY INPUT

DELETE PRIMARY INPUTS

-Class Displays the following class of primary inputs.

Full Primary inputs from both the User andSystem classesThis is the default.

System Primary inputs from the original design

User Primary inputs added with the ADDPRIMARY INPUT command

-Both Displays both the Golden and Revised primary inputs. This isthe default.

-Golden Displays the Golden design primary inputs.

-Revised Displays the Revised design primary inputs.



REPORT PRIMARY OUTPUTSREPort PRimary Outputs

[-Class <Full | User| System>][-Both |-Golden |-Revised](Setup / LEC Mode)

Displays primary output pins from the Golden and Revised designs.

Parameters

Related Commands

ADD PRIMARY OUTPUT

DELETE PRIMARY OUTPUTS

-Class Displays the following class of primary outputs.

Full Primary outputs from both the User andSystem classesThis is the default.

System Primary outputs from the original design

User Primary outputs added with the ADDPRIMARY OUTPUT command

-Both Displays both the Golden and Revised primary outputs. This isthe default.

-Golden Displays Golden design primary outputs.

-Revised Displays Revised design primary outputs.



REPORT PULSE GENERATORREPort PUlse Generator

[-ALL | MODule <module_name>][-Both | -Golden | -Revised](Setup / LEC Mode)


Reports the instances that were transformed with the SET ABSTRACT MODEL-transform_pulse_generator_on command.

Parameters

Related Commands

SET ABSTRACT MODEL

-ALL Displays all instances. This is the default.

-MODule Displays a specified module that was transformed.

-Both Applies to both the Golden and Revised designs. This is thedefault.

-Golden Applies to the Golden design.




REPORT REMOVED INSTANCEREPort REMoved Instance

[-Golden | -Revised](Setup / LEC Mode)

Report instances removed with the REMOVE command.

Parameters

Related Command

REMOVE

-Golden Reports instances removed from the Golden design. This isthe default.

-Revised Reports instances removed from the Revised design.



REPORT RENAMING RULEREPort REnaming Rule

[ |-MAp | -MOdule | -PIn][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays the list of renaming rules for mapping, module, and pin renaming. These rules wereoriginally added with the ADD RENAMING RULE command. The list displays a rule numberalong with a renaming rule. If you do not enter options, Conformal displays all renaming rules.

Parameters

Related Commands

ADD RENAMING RULE


READ DESIGN

READ LIBRARY

SET MAPPING METHOD

SET NAMING RULE

TEST RENAMING RULE

-MAp Displays only mapping renaming rules. If you do not specify-map, -module, or -pin, Conformal reports all renamingrules.

-MOdule Displays only module renaming rules.

-PIn Displays only pin renaming rules.

-Both Displays the renaming rules applied to both the Golden andRevised designs. This is the default.

-Golden Displays the Golden design renaming rules.

-Revised Displays the Revised design renaming rules.



REPORT RETENTION MAPPINGREPort REtention Mapping

(Setup / LEC Mode)


Reports the retention mapping rules. The set of rules reported include the user rules addedusing the ADD RETENTION MAPPING command and the default rule added by the system.


Note: The default rule is always reported even if no user rule is added using the ADDRETENTION MAPPING command.

Related Commands


DELETE RETENTION MAPPING



REPORT RULE CHECKREPort RUle Check

[-All | -MODIfied | rule_name*… [-SETTING] ][-File <filename> [linenumber]][-MODUle <modname>][-Summary | -Verbose][-HELP][ | -Design | -Library][-Ignore][-Note][-Warning][-Error][-Both | -Golden | -REvised](Setup / LEC Mode)

Displays the list of rule violations after the designs and libraries have been read in. Use the-summary option to display all of the violated rules.

Use the SET RULE HANDLING command to change the handling of any of these reportedrule violations.

See the Encounter Conformal Equivalence Checking User Guide for rule definitions andsample cases.

Rules with a severity of “Ignore” are not reported except with the rule_name or -ignoreoptions.

Parameters

-All Reports “all” rule violations encountered in the designs andlibraries.



-MODIfied Reports all the rule check violations that have a differentseverity level than the original default.

rule_name… Reports specified rule violations. Wildcards are supported.

-SETTING Displays the current severity level for the rule.



Related Commands

READ DESIGN

READ LIBRARY

SET RULE HANDLING

-File filename [linenumber]

Reports all rule check messages in a file. With thelinenumber option, you can report all rule check messagesfor a specific line number.

-Module modname Reports the rule checks that are specific to the specifiedmodule.

-Summary Display a summary of the rule violations. This is the default.

-Verbose Displays each instance of the rule violation.

-HELP Lists the names and numbers of all HDL rules.

-Design Reports the design rule violations.

If you do not specify -design or -library, the Conformalsoftware reports rule violations from both designs and libraries.

-Library Reports the library rule violations.

If you do not specify -design or -library, the Conformalsoftware reports rule violations from both designs and libraries.

-Ignore Reports violations that have a severity level of Ignore.

-Note Reports violations that have a severity level of Note.

-Warning Reports violations that have a severity level of Warning.

-Error Reports violations that have a severity level of Error.

Note: By default, rules with severity levels other than Ignore will be reported

-Both Reports the rule violations from Golden and Revised designsand libraries. This is the default.

-Golden Reports the Golden design and library rule violations.

-Revised Reports the Revised design and library rules violations.



REPORT SEARCH PATHREPort SEarch Path

[ | -Design | -Library][-Both | -Golden | -Revised](Setup / LEC Mode)

Displays the paths Conformal searches to locate filenames included in the READ DESIGNand READ LIBRARY commands.

Parameters

Related Commands

ADD SEARCH PATH

DELETE SEARCH PATH

READ DESIGN

READ LIBRARY

-Design Reports the search path used by the READ DESIGN command.

If you do not specify -design or -library, Conformalreports the search path used by both the READ DESIGNcommand and the READ LIBRARY command.

-Library Reports the search path used by the READ LIBRARYcommand.

If you do not specify -design or -library, Conformalreports the search path used by both the READ DESIGNcommand and the READ LIBRARY command.

-Both Reports the search path used by both the Golden and Reviseddesigns. This is the default.

-Golden Reports the search path used by the Golden design and library.

-Revised Reports the search path used by the Revised design andlibrary.



REPORT STATISTICSREPort STatistics

(LEC Mode)

Summarizes the mapping and comparison statistics for the Golden and Revised designs in atable.

Related Commands

REPORT COMPARE DATA






REPORT TESTCASEREPort TEstcase

< [-NONEQ][-ABORT][-Golden <<gate_id> | <instance_pathname> ...> ][-Revised <<gate_id> | <instance_pathname> ...> ]

>[-DIR_name <directory_name>][-NAME | -NONAME][-KEYPOINT_DEPTH <number>][-REPlace](LEC Mode)

Automatically extracts testcases for selected key points and generates a dofile and a filecontaining mapping information. Running the generated dofile can reproduce the problem inoriginal design, such as non-equivalences and aborts.

Parameters

-NONEQ Specifies that all non-equivalent points will be selected forthe generated testcase.

-ABORT Specifies that all abort points will be selected for thegenerated testcase.

-GOlden Applies the testcase extraction to the Golden design.

-Revised Applies the testcase extraction to the Revised design.

<gate_id> Specifies the gate ID of the testcase. You can specifymultiple gate IDs.

<instance_pathname> Specifies the instance pathname of the testcase. You canspecify multiple instance pathnames.

-DIR_name <directory_name>

Specifies the name of the testcase directory.

-NAME Includes the names of design objects (nets, instances,ports) in the generated testcase. This is the default.

-NONAME Does not includes the names of design objects (nets,instances, ports) in the generated testcase.

-KEYPOINT_DEPTH <number>



Examples

■ The following command selects all non-equivalent points, all abort points, and key pointswith gate id 10, with instance dlat in the Golden design netlist and the key point withinstance dff in the Revised design netlist, allowing the names of design objects to beincluded in the generated testcase:

report testcase -noneq -abort -golden 10 dlat -revised dff

■ The following command will select key point with gate id 10 in Revised design netlist fortestcase extraction. The names of design objects will use generic names (gate type anda serial number)

report testcase -revised 10 -noname

■ The following command will select all non-equivalent points for testcase extraction, usingkeypoint depth:

report testcase -noneq -keypoint_depth 1

Specifies the depth of the key points to report. Starting fromthe selected key point, the closest key point in its fanin orfan-out cone is a depth of 1. The default is 3.

-REPlace Overwrites the existing testcase directory.



REPORT TEST VECTORREPort TEst Vector

< gate_id | instance_pathname | pin_pathname>[<gate_id | instance_pathname | pin_pathname> [-Index <integer>]][-Golden |-Revised]| [-NONEQ]

(LEC Mode)

Displays error patterns for a specific nonequivalent compared point.

■ The first argument is the nonequivalent compared point.This point can be identified with a gate identification number, instance path, or a pin path.

■ The second argument, which is optional, is the diagnosis input point. These points aregates that connect directly to the input ports of the nonequivalent compared point wherethe logic cones are different. The display shows the diagnosis input point to thenonequivalent compared point; corresponding and non corresponding support keypoints with their simulation values; and final simulation result of the diagnosis input point

■ The Index option is used to specify which error pattern is displayed after you use thecommand. If you do not specify an index number, Conformal displays the first errorpattern.

You can also use this command with the -noneq option to report error patterns for everynonequivalent compared key point.

Parameters

gate_id | instance_pathname | pin_pathname

Specifies the gate identification number, instance path, or pinpath of the nonequivalent compared point.


gate_id |instance_pathname | pin_pathname



Related Command

DIAGNOSE

Specifies the gate identification number, instance path, or pinpath of the diagnosis input point to the nonequivalent comparedpoint.

Note: These options apply only to diagnosis points for DFF,DLAT, and BBOX. If you enter a point that is not a diagnosispoint, Conformal will error out.


-Index integer Displays the specified error pattern. The default is to displaythe first error pattern.

-Golden Specifies that the nonequivalent compared point is from theGolden design. This is the default.

-Revised Specifies that the nonequivalent compared point is from theRevised design.

-NONEQ Displays the error pattern for every nonequivalent point.



REPORT TIED SIGNALSREPort TIed Signals

[-ROot | -Module <name>][ | -TIE0 | -TIE1 | -TIEZ | -TIEX][ | -Net | -Pin][-Class <Full | System | User>][-Both | -Golden | -REvised](Setup / LEC Mode)

Displays tied signals from the Golden and Revised designs.

Parameters

-ROot Displays tied signals in the root module. This is thedefault.

-Module name Displays tied signals in the specified module.

-TIE0 Displays signals tied to logic 0.

If you do not specify the logic, Conformal displays signalstied to logic 0, 1, Z, and X.

-TIE1 Displays signals tied to logic 1.


-TIEZ Displays signals tied to logic Z.


-TIEX Displays signals tied to logic X.


-All Displays “all” net and instance names that have tied signalsassigned to them.



-Net Displays net names that have tied signals assigned to them.

-Pin Displays pin names that have tied signals assigned to them.



Related Commands

ADD TIED SIGNALS

DELETE TIED SIGNALS

-Class Displays this class of tied signals:

Full Tied signals from both the User andSystem classes


System Tied signals from the original design.

User Tied signals added with the ADD TIEDSIGNALS command.

-Both Displays tied signals from both the Golden and Reviseddesigns. This is the default.

-Golden Displays tied signals from the Golden design.

-REvised Displays tied signals from the Revised design.



REPORT UNMAPPED POINTSREPort UNmapped Points

[-SUMmary| -Extra | -UNReachable | -NOTmapped| [ -TYpe <PI | E | Z | DFf | DLat |CUt | BBox | PO>…

|-NOTYpe <PI | E |Z | DFf | DLat |CUt |BBox | PO>…]][-GRoup][-LIBName | -NOLIBName][-RETention][-NODLAT_GATED_CLOCK][-GOlden | -Revised](LEC Mode)

This report lists unmapped points, along with a summary of all of the unmapped points in theGolden and Revised designs.

Note: If you do not specify options, Conformal identifies all unmapped points and displays asummary. Furthermore, if you do not specify either Golden or Revised, Conformal reportsunmapped points for both designs.

Parameters

-SUMmary Lists a summary report of all of the unmapped points in theGolden and Revised designs. This is the default.

-Extra Lists extra points. These points are unmapped because they donot map with a counterpart in the comparison design. Extrapoints do not affect the circuit.

-UNReachable Lists unreachable unmapped points. Unreachable key pointsare those that do not eventually affect the primary output of thedesign.

-NOTmapped Lists “Not-mapped” unmapped key points.

Not-mapped key points are those that failed to be mapped.

-Type Lists unmapped points of the specified type. Available types areas follows:

PI Primary input

E TIE-E

Z TIE-Z

DFf D flip-flop



DLat D-latch

CUt All unmapped points for artificial gates thatbreak combinational loops

BBox Blackbox

PO Primary output

-NOType Does not list unmapped points of the specified type.

-GRoup Displays the unmapped groups in which either the Golden orRevised key point is a group of equivalent gates rather than asingle gate.

The group can be defined with the ADD INSTANCEEQUIVALENCE command or the -seq_merge option of theSET FLATTEN MODEL command.

A key point group is counted as one key point.

-LIBName When displaying unmapped points, includes suffixes. This isthe default.

-NOLIBName When displaying unmapped points, does not include suffixes.


If the unmapped point is a sequential element (DFF or DLAT)and belongs to the Golden Design, this option reports thetag-name (if any) associated with the DFF or DLAT. If theunmapped point is a sequential element (DFF or DLAT) andbelongs to the Revised Design, this option reports the powergating cell attribute (if any) associated with the DFF or DLAT.For non-sequential elements, nothing is reported.

The sequential unmapped points are not written out during theCHECK RETENTION MAPPING command, but if present, theyare reported as ’Not-Checked’ in the summary section.

-NODLAT_GATED_CLOCK Does not report deglitching clock-gating DLATs under theUnreachable category.

-GOlden Lists only the Golden unmapped points. This is the default.

-Revised Lists only the Revised unmapped points.



Related Commands

ADD MAPPED POINTS


MAP KEY POINTS


REPORT STATISTICS

SET MAPPING METHOD

SET NAMING RULE



REPORT VERIFICATIONREPort VErification

[-Verbose][-Summary](LEC Mode)

Reports a table of all violated checklist items for the following categories:

1. Non-standard modeling options used:

❑ Tristated output: checked/not checked

❑ Revised X signals set to E: yes|no

❑ Floating signals tied to Z: yes|no

❑ Command add clock for clock-gating used: yes|no

2. Incomplete verification:

❑ All primary outputs are mapped: yes|no

❑ All mapped points added as compare points: yes|no

❑ All compare points compared: yes|no

❑ User added black box: yes|no

❑ Black box mapped with different module name: yes|no

❑ Command add ignore outputs used: yes|no

3. Modification to design:

❑ Change gate type: yes|no

❑ Change wire: yes|no

❑ Primary inputs added: yes|no

4. Conformal extended checks recommended:

❑ FSM encoding: used|not used

❑ RTL5.1 Overlapped case items in parallel case statement: used|not used

❑ RTL5.4 Partial case items in full case statement: used|not used

❑ Multiple clocks in the design: yes|no



5. Design ambiguity:

❑ Duplicate module definition: yes|no

❑ Black box due to undefined cells: yes|no

6. Compare results: FAIL|ABORT|INCOMPLETE|<number> EQ|NOT_COMPARED

❑ Number of EQ compare points: <number>

❑ Number of NON-EQ compare points: <number>

❑ Number of Aborted compare points: <number>

❑ Number of Uncompared compare points: <number>

Parameters

Related Command

COMPARE

-Verbose Prints out each category and the count of violations.

-Summary Prints all items for each category and the violated items aremarked with an asterisk (*).



RESETRESET

(Setup / LEC Mode)

Resets the system to the initial state. All existing designs and libraries are deleted, and allpreviously issued commands are cancelled.

Related Commands


EXIT



RESET ABSTRACT MODELREset ABSTract Model

[-ALL | -MODule <module_name>][-Both | -Golden | -Revised](Setup / LEC Mode)


Resets the abstraction conditions that you set using the SET ABSTRACT MODEL command.

Parameters

Related Commands

ABSTRACT LOGIC


SET ABSTRACT MODEL

-All Resets abstraction conditions for all modules.


Resets abstraction conditions for the specified modules.

-Both Resets abstraction conditions for both the Golden and Reviseddesigns. This is the default.

-Golden Resets abstraction conditions for the Golden design.

-Revised Resets abstraction conditions for the Revised design.



RESET HIER_COMPARE RESULTRESet HIer_compare Result

(Setup / LEC Mode)

Resets the results of the hierarchical comparison. It is useful when you do multiplehierarchical compare runs and you wish to display the results of each hierarchical compareseparately.

Related Commands

RUN HIER_COMPARE

REPORT HIER_COMPARE RESULT

RESET





RESOLVERESolve

<module_name>[-All][-Golden | -Revised](Setup Mode)


Ungroups a module in the Golden or Revised design hierarchy. Resolving or ungrouping isthe process of eliminating a module and promoting its content up one level of the hierarchy.

Parameters

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD MOS DIRECTION

ADD NET ATTRIBUTE


DELETE CLOCK



READ PATTERN

REPORT CLOCK

module_name Resolves hierarchy for the specified module.

-All Resolves the specified module within all hierarchies of thespecified design.

-Golden Resolves hierarchy in the Golden design. This is the default.

-Revised Resolves hierarchy in the Revised design.






UNIQUIFY



RESTORE SESSIONREStore SEssion

<session_name>(Setup / LEC Mode)

Restores a session you previously initiated and saved using the SAVE SESSION command.

Before entering this command, Conformal must be in its initial state. Therefore, you musteither use the RESET command, or exit Conformal and restart it.

Important

You must run this restarted session on the same platform and same Conformalversion.

Parameters

Related Commands

RESET

SAVE SESSION

session_name Restores the specified session.



RUN HIER_COMPARERUN HIer_compare

<dofile_name>[-ROOT_module <golden_module> <revised_module>][-DYNamic_hierarchy | -NODYNamic_hierarchy][-NOREStart | -REStart][-ANALYZE_abort][-RETIMED_modules [-TOP | -NOTOP]][-BREAK_NONEQ][-BREAK_ABORT][-ANALYZE_BOUNDARY_conditions | -NOANALYZE_BOUNDARY_conditions][-VERBOSE](Setup Mode)


Runs dynamic hierarchical comparison. This command on completion produces one of thefollowing three statuses:

■ Equivalent—all the compared modules are equivalent.

■ Non-Equivalent—at least one of the compared module is non-equivalent.

■ Inconclusive—indicates one of the following conditions:

❑ at least one of the compared module has abort points

❑ at least one module is not-compared (for example, due to running the add moduleattribute -compare_effort none command)

❑ at least one module has incomplete compare result (for example, due to extraprimary outputs)

Note: When the status is Inconclusive the number of abort modules, not-comparedmodules, or modules that have incomplete compare result are reported.

For more information, see Dynamic Hierarchical Comparison in the Encounter ConformalEquivalence Checking User Guide.

<dofile_name> Specifies the name of the hierarchical dofile that was generatedwith the WRITE HIER_COMPARE DOFILE command.

Note: Cadence does not recommend manually editing ormodifying this hierarchical dofile prior to running the RUNHIER_COMPARE command. This might lead to unexpectedresults. If you want to edit or modify the hierarchical dofile, usethe static hierarchical comparison (dofile hier.do).



-ROOT_module <golden_module> <revised_module>

Uses the specified modules as the root modules. This is similarto the -Module option with the WRITE HIER_COMPAREDOFILE command without having to the regenerate the dofile.

-DYNamic_hierarchy

Auto-flattens the submodules to propagate any design errors tothe top level. The flattened modules are merged to the nextlevel in the hierarchy and compared at that level. This is thedefault.

-NODYNamic_hierarchy

Runs static hierarchical comparison without auto-flattening thesubmodules.

Note: Do not use this option if the hierarchical dofile isgenerated using the WRITE HIER_COMPARE DOFILE-run_hier_compare command.

-NOREStart Continues an interrupted session, preserving the previouscompare results. This is the default.

You can interrupt dynamic hierarchical comparison by pressingCtrl-c.

-REStart Deletes the previous comparison results.

-ANALYZE_abort Inserts the ANALYZE ABORT -compare command into eachuncompared and aborted module’s compare script.



Examples

■ The following command uses the hier.do dofile for hierarchical comparison:

run hier_compare hier.do

If the previous comparison run of the hier.do dofile resulted in three aborted modules,you can run a second comparison using the following command:

-RETIMED_modules [-TOP | -NOTOP]

Compares and blackboxes the submodules with thePIPELINE_Retime attribute. The PIPELINE_Retimeattribute can be attached to a module using the ADD MODULEATTRIBUTE command. For this option to work correctly,modules with PIPELINE_Retime attribute should exist in thehierarchical dofile script.

-TOP runs the comparison of the top module such thatsubmodules without the PIPELINE_Retime attribute are fullyflattened. This is the default for -RETIMED_module.

-NOTOP specifies that comparison stops after the modules withthe PIPELINE_Retime attribute have been compared andblackboxed. The hierarchical result is reported as ‘Inconclusive’because the entire design is not compared.

-BREAK_NONEQ The comparison stops when it encounters a non-equivalentmodule. To continue comparing from the next module in thehierarchy, use the RUN HIER_COMPARE command.

-BREAK_ABORT The comparison stops when it encounters an abort module. Tocontinue comparing from the next module in the hierarchy, runthe RUN HIER_COMPARE command.

-ANALYZE_BOUNDARY_conditions

Reduces the number of flattened modules by resolvingboundary constraints. This is the default.

-NOANALYZE_BOUNDARY_conditions

Does not perform resolution on boundary constraints.

Note: Do not use this option if the hierarchical dofile isgenerated using the WRITE HIER_COMPARE DOFILE-run_hier_compare command.

-VERBOSE Lists all the hierarchical constraints and additional information.



run hier_compare hier.do -analyze_abort

This command only operates on aborted modules from the previous run, andautomatically runs the ANALYZE ABORT -compare command after the defaultCOMPARE command.

■ The following command uses m4 as the root module for both the Golden and Reviseddesigns, deleting the previous comparison results:

run hier_compare hrcmod.do -root_module m4 m4 -restart

■ The following command runs hierarchical comparison on modules with thePIPELINE_Retime attribute attached:

run hier_compare hier.do -retimed_modules

Related Commands

ANALYZE ABORT

COMPARE







RUN PARALLEL COMPARERUN PArallel Compare

[-NONEQ_Stop <integer>][-ABORT_Stop <integer>][-NONEQ_Print][-ABORT_Print][-GATE_TO_GATE][-TEST][-SUBMIT_OPTIONs <string>][-DPL](LEC Mode)


Runs equivalency checking comparison between the Golden and Revised designs on theadded compared points using parallel processing. During the comparison, the Conformalsoftware displays following information:

■ A progress percentile number that shows the completion rate

■ A running count that shows the number of key points that have been compared alongwith the total number of non-equivalent key points

Parameters

-NONEQ_Stop Stops the comparison after finding the specified number ofnon-equivalent points.

-ABORT_Stop Stops the comparison after finding the specified number ofabort points.

-NONEQ_Print Displays the non-equivalent points as they are found.

-ABORT_Print Displays the abort points as they are found.

-GATE_TO_GATE Enables an algorithm that might improve the run time of largegate-to-gate netlist comparisons.

-TEST Launches qualification run to test if the environment is suitablefor parallel processing.

-SUBMIT_OPTIONs Specifies the options which will replace the keyword<submit_options> in the submit command line (see the SETPARALLEL OPTION -SUBMIT_COMMAND_LINE command).



Examples

The following commands run the first parallel job in queue q1, and the second parallel run inqueue q2.

run parallel compare -submit_options "-q q1"

run parallel compare -submit_options "-q q2"

Related Commands

COMPARE

SET PARALLEL OPTION

-DPL Uses the Cadence Distributed Processing Library (DPL) tointerface to the Load Sharing Facility (LSF) daemon. Refer tothe Cadence DPL User Guide for more information.



RUN PARTITION_COMPARERUN PArtition_compare

[-Keypoint <identifier...>][-Number <number>][-VERBOSE](LEC Mode)


Runs comparisons with functional partitioning. You can specify partitioned key points in theGolden design and the number of key points for a partition. If no key points are specified, thiscommand will automatically choose appropriate key points for the partition.

Note: You do not need to switch to Setup mode to flatten the netlist in each partition iteration.With the constants assigned on the selected key points, comparison can become easier ineach partition iteration.

For example, when abort points are encountered in comparison, you can run this commandto do functional partitioning for the abort points.

Related Commands

COMPARE

-Keypoint Specifies the partition key point in the Golden design. The keypoint can be specified by gate instance pathname or gate ID. Ifno key points are specified, this command will automaticallychoose appropriate key points for the partition.

-Number Specifies the number of key points for a partition. The maximumnumber of compare iterations is the base-2 exponent of thepartitioned key point number. The default partitioned key pointnumber is 8.

-VERBOSE Provides additional information in the functional partition.



SAVE DOFILESAVe DOfile

<filename>[-Replace](Setup / LEC Mode)

Saves the commands entered during the current session to a file. Use the saved dofile lateras a batch file to repeat the Conformal session.

When running a Conformal session from a dofile, this command does not save individualcommands included in a separate dofile (that is, Conformal saves the manually enteredcommands, which can include a dofile <filename> command).

Note: If the filename you specify already exists, you must use either the -replace or-append option.

Related Commands

DOFILE

SET COMMAND PROFILE

SET LOG FILE

filename Writes the dofile to the specified file.

-Replace Replaces the contents of the specified preexisting file.



SAVE HIER_COMPARE RESULTSAVe HIer_compare Result

(LEC Mode)

Saves the hierarchical comparison results of the module comparison. If the WRITEHIER_COMPARE DOFILE command is used, this command is placed after every modulecompared.

After the hierarchical comparison of all modules is complete, use the REPORTHIER_COMPARE RESULT command to display the results of the hierarchical comparison.

Related Commands



RUN HIER_COMPARE




SAVE SESSIONSAVe SEssion

[-REPlace]<session_name>(Setup / LEC Mode)

Saves your session up to a current point and outputs the session file in gzip format. You canthen restore the session later using the RESTORE SESSION command. You can use thiscommand if priorities demand that another session preempt your session.

Important

When you use the RESTORE SESSION command, you must run the restartedsession on the same platform and same Conformal version.

Parameters

Related Command

RESTORE SESSION

-REPlace Replaces the existing session. If the session already exists, itwill be overwritten and no backup copy will be created.

By default, backup copies are created automatically.

This option is useful if you want to save disk space and onlyneed to save your session occasionally.

session_name Attaches this session name to the saved session.



SEARCHSEArch

[-USage] <string1> [<string2>]…(Setup / LEC Mode)

Searches the database of commands and parameters, and displays those commands thatmatch all of the specified strings. Strings can be specified in any order; however, everyspecified string must match.

Parameters

Related Command

HELP

-USage Displays the commands that have parameters that match thesearch string. This outputs the entire command syntax for eachcommand.

string1 Displays commands that match the specified string.

string2… Displays commands that match additional specified strings.



SET ABSTRACT MODELSET ABSTract Model

[-ALL |-MODule <module_name…>][-NOKEEPER2PUllup | -KEEPER2PUllup ][-NOWEAKPULLUP | -WEAKPULLUP ][-NOWEAKPULLDOWN | -WEAKPULLDOWN ][-NOKEEPERSTate | -KEEPERSTate ][-NODYNSTate | -DYNSTate ][-NOPRE_CHARGE_KEEP_Clock | -PRE_CHARGE_KEEP_Clock ][-NODOMINOLATch | -DOMINOLATch ][-Bulk | -NOBulk ][-NOMEM_BL_EQualizer | -MEM_BL_EQualizer][-NOBUF_AMP | -BUF_AMP][-NOMULTICLOCKPRECHARGE | -MULTICLOCKPRECHARGE][-REPHASE_BY_NAME_POSitive <name>] [-REPHASE_BY_NAME_NEGative <name>][-TRANSFORM_PULSE_GENERATOR_ON][-NOIGNORE_DLAT_CONTENTION | -IGNORE_DLAT_CONTENTION][-Both | -Golden | -Revised ](Setup Mode)


Specify certain conditions for abstracting transistor logic.

Refer to the Encounter Conformal Equivalence Checking User Guide for additionalinformation about using this command in the Conformal Custom flow.

Parameters

-ALL Abstracts transistor logic from all modules within the givendefaults. This option is the default.


Abstracts transistor logic from the specified modules.

-NOKEEPER2PUllup Does not regard charge keepers as weak pull-up devices.This is the default.

-KEEPER2PUllup Regards charge keepers as weak pull-up devices.

-NOWEAKPULLUP Does not regard devices that are tied to PMOS as weakdevices. This is the default.

-WEAKPULLUP Regards devices that are tied to PMOS as weak devices.

-NOWEAKPULLDOWN Does not regard devices that are tied to NMOS as weakdevices. This is the default.



-WEAKPULLDOWN Regards devices that are tied to NMOS as weak devices.

-NOKEEPERSTate Does not regard charge keepers as latches. This is thedefault.

-KEEPERSTate Regards charge keepers as latches.

-NODYNSTate Does not regard tristate table nets as latches. This is thedefault.

-DYNSTate Regards tri-statetable nets as latches.

-NOPRE_CHARGE_KEEP_Clock

In domino logic, does not regard pre-charge clocks as part ofthe logic function. This is the default.

-PRE_CHARGE_KEEP_Clock

For domino logic, regards pre-charge clocks as part of thelogic function.

This option includes the defined pre-charge clock in theabstracted logic function (the default behavior removes thedefined pre-charge clock from the abstracted logic). This isindicated when you define a precharge clock with one of thefollowing commands:

add net attribute CLOCK0 | CLOCK1

add clock 0 | 1

When you use -pre_charge_keep_clock, the resultinglogic is equivalent to RTL that explicitly models the pre-chargecondition, rather than RTL that models only the evaluatefunction. In the latter, the output function is not defined duringpre-charging.

-NODOMINOLATch Does not abstract pre-charge logic functions as a latch. Thisis the default.

-DOMINOLATch Abstracts pre-charge logic functions as a latch. This assumesthat data input is stable in active clocks.

-BULK Identifies nets connected to PMOS bulk terminals as powerand nets connected to NMOS bulk terminals as ground. Thisis the default.



-NOBULK By default, Conformal Custom identifies nets connected toPMOS bulk terminals as power and nets connected to NMOSbulk terminals as ground. However, this option removes thatassumption and you will need to specify power and groundpins/nets by using *.GLOBAL <name>:P for power nets and*.GLOBAL <name>:G for ground nets or use Conformalcommands to add constraints, tied signals (pins), or netattributes.

Important

You must use SET ABSTRACT MODEL -NOBulkbefore reading in the SPICE file.

-NOMEM_BL_EQualizer

Does not handle bit-line pre-charge, and equalization. This isthe default.

-MEM_BL_EQualizer Handles circuits that include bit-line pre-charge, andequalization.

-NOBUF_AMP Does not handle buffered-type sense amplifiers, level shifters,pre-charge, and equalization. This is the default.

-BUF_AMP Handles the following portions of a circuit: buffered-type senseamplifiers, level shifters, pre-charge, and equalization.

-NOMULTICLOCKPRECHARGE

Does not propagate clocks through logic gates which havemore than one clock input. This is the default.

-MULTICLOCKPRECHARGE

Propagates clocks through logic gates which have more thanone clock input.



-REPHASE_BY_NAME_POSitive <name>

Gives abstract logic a hint about the desired phase ofstate elements, such as D-latches and DFFs. Whenabstracting state elements, abstract logic will choose aphase for each state element, where <name> specifies the netwhich will be driven by the ’Q’ pin, if possible.

If this is not possible, then abstraction will try to choose a netfor the ’Qn’ pin which has a name specified by the-REPHASE_BY_NAME_NEGative option.

Note: The set mapping method command’s -phase optionwill allow mapping and comparison of state elements withdifferent phases in the Golden and Revised designs. Considerrunning set mapping method -phase before using thisoption, as it requires less effort.

-REPHASE_BY_NAME_NEGative <name>

Specifies the net which will be driven by the ’Qn’ pin, ifpossible.

-TRANSFORM_PULSE_GENERATOR_ON

Enables pulse transformation.

-NOIGNORE_DLAT_CONTENTION

Stops forming the D-Latch when contention on a net isdetected. This is the default.

-IGNORE_DLAT_CONTENTION

Continues to form the D-Latch, even if contention on a net isdetected.

By default, the SET ABSTRACT MODEL command stops theexecution of abstraction of latches and flip-flips (stateelements) when a power to ground through a stack of activeON transistors is possible. Use this option to report the shortand continue to abstract the state element.

-Both Specifies abstraction conditions for both the Golden andRevised designs. This is the default.

-Golden Specifies abstraction conditions for the Golden design.

-Revised Specifies abstraction conditions for the Revised design.



Examples

Sample Dofile:

read design test.v -golden

set abstract model -keeper2pullup -weakpullup -golden

report abstract model -golden

abstract logic

Related Commands

ABSTRACT LOGIC

ADD CLOCK

ADD NET ATTRIBUTE


REPORT PULSE GENERATOR




SET ANALYZE OPTIONSET ANalyze Option

[-NOAUTO| -AUTO [-ANALYZE_SETUP | -NOANALYZE_SETUP][-ANALYZE_ABORT | -NOANALYZE_ABORT]

](Setup Mode)


Automatically determines the best place to run the ANALYZE SETUP command. In addition,the Conformal software automatically runs the ANALYZE ABORT command whenever thecomparison returns abort points but no non-equivalent points.

Parameters

Related Command

ANALYZE ABORT

ANALYZE SETUP

-NOAUTO Disables automatic analysis. This is the default.

-AUTO Enables automatic analysis.

-ANALYZE_SETUP Enables automatic setup analysis. This is the default whenrunning this command with the -AUTO option.

-NOANALYZE_SETUP Disables automatic setup analysis.

-ANALYZE_ABORT Enables automatic abort point analysis. This is the default.

-NOANALYZE_ABORT Disables automatic abort point analysis.



SET_ATTR INPUT_PRAGMA_KEYWORDSET_ATtr INPUT_PRAGMA_Keyword

<string>(Setup Mode)

Specifies a keyword that the Conformal software must consider as an input pragma when itencounters it as the first word in a Verilog or VHDL source comment.

A pragma is a comment in the Verilog or VHDL source and is set off from ordinary commentsby the pragma keyword. The pragma keyword is the first word listed in a pragma, and itnotifies the Conformal software that the remainder of the comment is a command and not acomment. Changing this keyword allows you to set up compatibility with other tools.

Parameters

Examples

Sample Dofile:

set_attr input_pragma_keyword rtl

set synthesis_off_command turn_off

set synthesis_on_command turn_on

After running these three commands, the Conformal and VHDL parsers will recognize thepragmas in the VHDL and Verilog Source files.

In a VHDL file, the code between -- rtl turn_off and -- rtl turn_on will not besynthesized.

In a Verilog file, the code between // rtl turn_off and // rtl turn_on will not besynthesized.

Related Commands

SET SYNTHESIS_OFF_COMMAND

SET SYNTHESIS_ON_COMMAND

string Specifies the name of the keyword for a tool vendor.

Default: pragma, synthesis, synopsys, cadence, ambit,verplex, conformal



SET CASE SENSITIVITYSET CAse Sensitivity

<ON | OFf>(Setup Mode)

Specifies whether names you enter are case sensitive. The system default is no casesensitivity for both the Golden and Revised designs.

Execute this command before READ LIBRARY and READ DESIGN. Use the REPORTENVIRONMENT command to display the case sensitivity setting.

Parameters

Related Command

REPORT ENVIRONMENT

ON Names that are entered are case sensitive.

OFf Names that are entered are not case sensitive. This is thesystem default.



SET COMMAND PROFILESET COmmand PRofile

[OFF | ON](Setup / LEC Mode)

Starts or stops recording a profile of commands executed in Conformal. This commandrecords the order of command execution and the memory use. The profile includescommands used in the GUI mode.

Use the REPORT COMMAND PROFILE command to view the profile.

Parameters

Related Commands

REPORT COMMAND PROFILE

SET LOG FILE

OFF Stops tracking executed commands. This is the default.

ON Starts tracking executed commands.



SET COMPARE EFFORTSET COmpare Effort

<Low | Medium | High | Auto>(Setup / LEC Mode)

Specifies the amount of effort equivalency checking applies to the key points comparison. Ifyou know your designs have many complex key points, increase the effort level. However,when you raise the effort level, you also increase the amount of time involved in checking.Hence, you increase the total CPU time.

Use the REPORT ENVIRONMENT command to display the compare effort setting. Thesystem default is set to low compare effort.

Parameters

Related Commands

COMPARE

REPORT ENVIRONMENT

Low Applies minimal effort to equivalency checking for each gate.This is the default.

Medium Applies greater effort to equivalency checking for each gate.

High Applies the maximum effort to equivalency checking for eachgate.

Auto Starts with low effort and automatically increases the compareeffort when abort points are present in the design.



SET COMPARE OPTIONSSET COmpare Options

[-GENLATCH | -NOGENLATCH][-NOALLGENLATCH | -ALLGENLATCH][-VERIFY_Disabled_ports](Setup / LEC Mode)

Turns on options to the comparison process.

Parameters

-GENLATCH Compares latches as generic latches by analyzing all logiccones simultaneously. The software automatically determineswhich latches are to be compared as generic latch, and thereset are compared by individual logic cones. This is thedefault.

With this option, you can compare latches that are trulyfunctionally equivalent, even though the logic cones of theseparate input pins are not.

-NOGENLATCH Specifies that no latch is compared as a generic latch. Alllatches are compared by individual logic cones.

-NOALLGENLATCH Does not compare all latches as generic latches. This is thedefault.

This option has no effect when using -NOGENLATCH.

Note: The input cones compared are set cones, reset cones,clock cones, and data cones.

-ALLGENLATCH Compares all latches as generic latches.

This option has no effect when using -NOGENLATCH.

-VERIFY_Disabled_ports

Compares data cones even if their clocks are disabled. Bydefault, a data cone will not be compared if its correspondingclock port is tied to a constant (for DFFs) or to zero (for latches).

Note: You should use this command option before running thefirst COMPARE command. If you use this after running COMPARE,this option has no effect.



Related Command

COMPARE



SET CPU LIMITSET CPu Limit

<integer> <-Days | -Hours | -Minutes>[-NOKill][-WALLTIME](Setup / LEC Mode)

Specifies the time limit for the compare effort. The system default is 525,600 minutes. Set thetime limit for minutes, hours, or days.

Use the REPORT ENVIRONMENT command to display the setting for the CPU time limit.

Note: When the Conformal software reaches the specified CPU limit, it stops all processingand exits.

Parameters

Example

The following commands show an example of using the SET CPU LIMIT command with andwithout the -WALLTIME option.

The time is 11:00 am and you start two Conformal sessions on the same machine, executingthe same dofile, that will run more than 20 minutes. You set the time limit for session 1 in realclock time with the following command:

set cpu limit 10 -minutes -walltime

You set the time for session 2 at the same limit but without using the real clock time with thefollowing command:

set cpu limit 10 -minutes.

integer Specifies a positive integer for the CPU time limit.

-Days Specifies that the CPU time limit refers to days.

-Hours Specifies that the CPU time limit refers to hours.

-Minutes Specifies that the CPU time limit refers to minutes.

-NOKill Prevents the software from exiting. This returns the commandprompt.

-WALLTIME Specifies that the time limit is in real clock time.



At 11:10, session 1 will terminate because the real clock time has elapsed 10 minutes.However, session 2 might not terminate because the real time it consumed during this 10minutes is less than 10 minutes if some of the time is consumed by other processes runningon the machine.

Related Command

REPORT ENVIRONMENT



SET DATAPATH OPTIONSET DAtapath Option

[-MERGE |-NOMERGE][-NOAUTO |-AUTO [-MODULE [-RESOURCEFILE <filename>]]][-NOSHARE | -SHARE][-NOADDERTREE | -ADDERTREE][-EFFort <MEDium | HIgh>][-Verbose](Setup / LEC Mode)

Specifies whether Conformal automatically analyzes data paths on switching from Setup toLEC mode and whether to apply operator merging. The results of the analysis enableConformal Ultra to automatically resolve multipliers, operator merging, and resource sharingproblems.

Note: You cannot run datapath analysis without first mapping the Revised design keypointsto the Golden design keypoints.

Parameters

-MERGE Automatically applies the operator merging technique whenswitching from Setup to LEC mode. This is the default.

-NOMERGE Does not automatically apply the operator merging techniquewhen switching from Setup to LEC mode.

-NOAUTO Does not automatically analyze data paths when switching fromSetup to LEC mode. This is the default.

-AUTO Automatically analyzes data paths when switching from Setupto LEC mode. This also performs additional carry-save adder(CSA) analysis.

-MODULE Automatically applies analysis on the datapath modules in theRevised design netlist.

-RESOURCEFILE <filename>

Specifies the resource filename to analyze the datapathmodules.

-NOSHARE Does not apply the resource sharing technique. This is thedefault.

-SHARE Analyzes the design for datapath resource sharing.



Examples

■ The following command applies module-based datapath analysis followed by theoperator-level datapath analysis when switching from Setup to LEC mode:

set datapath option -auto -module -verbose

set system mode lec

■ The following command applies operator-level datapath analysis when switching fromSetup to LEC mode:

set datapath option -auto

set system mode lec

Related Commands

ANALYZE DATAPATH

ANALYZE MULTIPLIER




SET FLATTEN MODEL

-NOADDERTREE Does not automatically add parentheses to the input operandsof adder trees when switching from Setup to LEC mode. This isthe default.

-ADDERTREE Automatically adds parentheses to the input operands of addertrees when switching from Setup to LEC mode.

-EFFort <MEDium | HIgh>

Specifies the effort level. Choose MEDium (the default), or HIghto help provide better analysis of some multipliers, but canincrease the analysis runtime.




SET DIRECTIVESET DIrective

<ON | OFf>[[synthesis | vendor_name] directives][-file <file_name*>](Setup Mode)

Specifies whether to enable or disable the effects of the specified synthesis directives whenreading in a Verilog or VHDL file. If you enter this command and do not specify any directives,this command enables (or disables) all of the directive effects. The system default enablesall directives. (Thus, if you want Conformal to enable all directives, no action is necessaryon your part.)

Execute this command before READ LIBRARY and READ DESIGN.

For each disabled directive used in the HDL source code, Conformal responds as follows:

■ If the directive is supported but disabled, Conformal returns a message stating thedirective is disabled.

■ If the directive is unsupported and disabled, Conformal returns a message stating thatthe directive is unsupported.

Conformal Directives

The following information includes short descriptions and examples of four supportedConformal directives.

■ clock_hold “<name>…”

This directive instructs Conformal to synthesize latch arrays so that the array address isplaced into the clock cone of the synthesized logic.

Example:

// conformal clock_hold “memory_array”

always @(clk or we or addr or din) begin

if (clk && we) memory_array[addr] = din;

end

Without this directive, the above always process results in a latch array with both clkand we in the clock logic. And addr is used to mux between din and the old state.Thus, with this directive, we move the addr into the clock logic of the array. Thisdirective is useful for register files and memory arrays.



■ infer_latch

This directive instructs Conformal to use a D-latch instead of a DFF when there is analways statement with an edge-triggered clock. The default is to use a DFF.

Example:

always @(posedge clk) begin // conformal infer_latch

qstate = din;

end

In this example, the infer_latch directive tells Conformal to synthesize a latchenabled with a high clock (rather than a D flip-flop with a positive edge triggered clock)for the always process. It is similar to writing the following RTL:

always @(clk or din) begin

if (clk) qstate = din;

end

■ multi_port

This directive instructs Conformal to synthesize a multi-port latch or register whenmultiple, simultaneous definitions exist for the same state variable.

Example:

always @(clk1 or din1) if (clk1) qstate = din1;

always @(clk2 or din2) if (clk2) qstate = din2;

…

always @(clkn or dinn) if (clkn) qstate = dinn;

This sample case results in n number of latches, each with separate clocks and datainputs and all outputs wired together. However, the implementation of a multiport cannotbe compared with an n port latch. Thus, you would use the // conformalmultiport “qstate” directive to synthesize an n port latch with one Q output.Internally, a primitive UDP model represents the valid function. If a simultaneous writeoccurs on multiple ports and the input data on those ports is not equal, the statebecomes an X. This directive is generally used for multi-port memory arrays and customdesigns.

■ mem_rowselect

This directive supersedes the clock_hold directive. It guides memory array RTLmodel synthesis so that it includes the same logic in the clock and data cones as in theimplementation. Thus, Conformal can complete equivalence checking.

Example:

// conformal mem_rowselect “mem clk addr[7:5] addr[2:0]”



always @(clk or we or addr or din) begin

if (clk && we) mem[addr] = din;

end

The synthesized result creates a row decoder with address bits 7, 6, 5, and 2, 1,0, and used clk as an enable. The addr bits 3 and 4 are used to column multiplexinput data when we is active. However, when we is not active or a column is selected,the array data input is in a high Z state, which is representative of memoryimplementation.

■ one_hot/one_cold/zero_one_hot/zero_one_cold "<name>..."

This directive instructs Conformal to adds one-hot constraints on specified net path. Theone_hot and zero_one_hot constraints let only zero or one net be at a 1-state andthe remaining nets be at a 0-state. The one_cold and zero_one_cold constraints letonly zero or one net be at a 0-state, and the remaining nets be at a 1-state.

In the following example, only zero or one of net ’aa’ and ’bb’ is constrainted to be1-state, and the other one is constrainted to be at 0-state:

// pragma one_hot "aa, bb"

Note: The wildcard (*) represents any zero or more characters in filenames.

Parameters

ON Enables the specified directives. (The initial system defaultenables all directives.)

OFf Disables the specified directives. If you do not specifydirectives, all directives are disabled.

synthesis Enables (or disable) the specified Synplicity synthesisdirectives.



vendor_name Enables (or disable) the specified synthesis directives whenthey are used with the specified vendor_name prefix.Supported vendor_names are listed below:

■ cadence

■ synopsys

■ ambit

■ quickturn

■ verplex

■ conformal



directives Enables (or disables) the specified synthesis directives. If youdo not specify any directives, all directives are enabled (ordisabled), accordingly. Supported directives are listed below.

■ assertion_library

■ black_box

■ built_in

■ clock_hold

■ compile_off

■ compile_on

■ dc_script_begin

■ dc_script_end

■ divider

■ enum

■ full_case

■ infer_latch

■ mem_rowselect

■ multi_port

■ multiplier

■ operand

■ parallel_case

■ pragma

■ state_vector

■ synthesis_off

■ synthesis_on

■ template

■ translate_off

■ translate_on

-File file_name* Enables (or disables) a list of directives that are specified in aRTL file. This option supports wildcards.



Examples

Enabling Directives

The Conformal, Synopsys, and Ambit directives are enabled by default. The Quickturndirectives are disabled by default. To recognize the Quickturn directives, you must first turnon all of the directives for Quickturn using the following command:

set directive on quickturn

Enabling One Directive

When you employ the SET DIRECTIVE command and you do not specify a directive, thecommand applies to all directives. In the following example, the objective is to enable only theparallel_case directive. To do so, first disable all directives, then enable the specifieddirective (parallel_case).

//disable all directivesset directive off

//enable parallel_caseset directive on parallel_case

Disabling All Directives for One Vendor

In the following example, the objective is to disable all Synopsys directives (synopsystranslate_off, synopsys translate_on, synopsys full_case…).

//disable all synopsys directivesset directive off synopsys

Disabling Specified Directives for One Vendor

In the following example, the objective is to disable synopsys translate_off andsynopsys translate_on. This command has no effect on conformaltranslate_off and conformal translate_on.

//disable synopsys translate_off and synopsys translate_onset directive off synopsys translate_off translate_on

Enabling a List of Directives from an RTL File

In the following examples, we have 2 RTL files: test.v and test1.v.

■ In the following command, the synthesis directive parallel_case is on (enabled) in filetest.v:



set directive on parallel_case -file test.v

■ In the following command, the synthesis directive parallel_case is on (enabled) in filetest.v and test1.v:

set directive on parallel_case -file *.v

Related Commands

READ DESIGN

READ LIBRARY



SET DOFILE ABORTSET DOfile Abort

<ON | OFf | Exit>(Setup / LEC Mode)

Specifies how Conformal handles the dofile when an error message occurs.

■ If the dofile abort handling is set to On, the dofile terminates when an error messageoccurs. This is the default.

■ If the dofile abort handling is set to Off, the dofile continues even if an error messageoccurs.

■ If the dofile abort handling is set to Exit, the session exits when an error message occurs.

Parameters

Related Commands

BREAK

CONTINUE

DOFILE

ON Terminates the dofile if an error message occurs. This is thedefault.

OFf Continues the dofile even if an error message occurs.

Exit Exits the session if an error message occurs.



SET EXIT CODESET EXit Code

[-CLEAR][-VERBOSE][ | -INTERNAL_ERROR | -NOINTERNAL_ERROR][ | -COMMAND_ERROR | -NOCOMMAND_ERROR](Setup / LEC Mode)

Controls and displays the exit code for the Conformal session. This command is useful whenrunning a complex flow, such as hierarchical comparison and iterative comparison.

Parameters

Examples

■ The following command displays current exit code:

set exit code

■ If a failing comparison was followed by a passing comparison (after fixing someconstraints), bit 4 in the exit code is still non-zero. However, the following commandclears the exit code and displays a table listing the status codes and decimal exit code:

set exit code -clear -verbose

■ The following command set command error bit to 1:

set exit code -command_error

-CLEAR Clears the exit code to only reflect most current running status.

-VERBOSE Displays a table listing the status codes.

-INTERNAL_ERROR Sets the internal error bit.

-NOINTERNAL_ERROR Clears the internal error bit.

-COMMAND_ERROR Sets the command error bit.

-NOCOMMAND_ERROR Clears the command error bit.



SET FLATTEN MODELSET FLatten Model

[-Map | -NOMap][-NOPin_keep | -PIN_keep][-NOLATCH_Fold | -LATCH_Fold][-NOLATCH_Transparent | -LATCH_Transparent][-NOLATCH_FOLD_Master | -LATCH_FOLD_Master][-NOLATCH_MERGE_PORT | -LATCH_MERGE_PORT][-NOALL_SEQ_Merge | -ALL_SEQ_Merge][-NOSEQ_Merge | -SEQ_Merge][-NOALL_INV_SEQ_Merge | -ALL_INV_SEQ_Merge][-NOSEQ_Redundant | -SEQ_Redundant][-NOLIB_SEQ_Redundant | -LIB_SEQ_Redundant][-NOSEQ_SIMPLIFY_Clock | -SEQ_SIMPLIFY_Clock][-NOSEQ_Constant | -SEQ_Constant][-NOGATED_Clock | -GATED_Clock][-DFF_TO_DLAT_ZERO | -NODFF_TO_DLAT_ZERO][-DFF_TO_DLAT_FEEDBACK | -NODFF_TO_DLAT_FEEDBACK][-NOLOOP_AS_DLAT | -LOOP_AS_DLAT][-SEQ_CONSTANT_FEEDBACK | -NOSEQ_CONSTANT_FEEDBACK][-SEQ_CONSTANT_X_TO < 0 | 1 >][-AUTO_MODELING | -NOAUTO_MODELING][-OUTPUT_Z | -NOOUTPUT_Z][-NOBBOX_MERGE | -BBOX_MERGE][-SHOW_MESSAGE_NAME][-NOKEEP_IGnored_PO | -KEEP_IGnored_PO][-CUT_REMOVE REDUNDANT][-NOECO | -ECO](Setup Mode)

Specifies certain conditions for the flattened model. Refer to the arguments table for acomplete list of options and their effects.

Use the REPORT ENVIRONMENT command to display the settings for the flattened model, oryou can run this command without any options (in either Setup or LEC mode) to report acomplete list of flattened modeling options.

Parameters

-Map Does automatic key point mapping. This is thedefault.

-NOMap Skips the automatic key point mapping when thesystem mode is changed from Setup to LEC.



-NOPin_keep In an effort to reduce memory use, Conformal does notkeep certain gate pins. This is the default.

-PIN_keep Keeps all gate pin information for gate reporting. Usethis option when reporting gate information at thedesign level. It will increase memory use.

-NOLatch_fold Does not fold a master-slave latch into a D flip-flop.This is the default.

-Latch_fold Folds a master-slave latch into a D flip-flop.

-NOLATCH_Transparent Does not treat latches that are always enabled astransparent. This is the default.

-LATCH_Transparent Converts D-Latches into buffers if the clock ports of theD-latches are always enabled.

-NOLATCH_FOLD_Master Does not convert two latches in an LSSD format into aDFF gate when the reset signal is connected only tothe master.

-LATCH_FOLD_Master Converts two latches in an LSSD format into a DFFgate when the reset signal is connected only to themaster.

-NOLATCH_Merge_port Does not collapse multi-port latches into a single-portlatch. This is the default.

-LATCH_Merge_port Collapses multi-port latches into a single-port latch.

-NOALL_SEQ_Merge Does not merge state elements that are functionallyequivalent. This is the default.

-ALL_SEQ_Merge Merges state elements that are functionally equivalent.

-NOSEQ_Merge Does not merge sequential elements in the clock coneof a DFF or D-latch. This is the default.

-SEQ_Merge Merges common groups of sequential elements intoone sequential element in the clock cone of a DFF orD-latch.

-NOALL_INV_SEQ_Merge Does not merge state elements that are functionallyinverted. This is the default.

-ALL_INV_SEQ_Merge Merges state elements that are functionally inverted.

-NOSEQ_Redundant Does not remove redundant fan-out gates from DFFsand DLATs. This is the default.



-SEQ_Redundant Removes redundant fan-out gates from DFFs andD-Latches.

-NOLIB_SEQ_Redundant Retains redundant fan-out gates from DFFs andDLATs in the Library. This is the default.

-LIB_SEQ_Redundant Removes redundant fan-out gates from DFFs andDLATs in the Library.

-NOSEQ_SIMPLIFY_Clock Does not fold master and slave latches when there is aredundant interaction between the clock and resetsignals. This is the default.

-SEQ_SIMPLIFY_Clock Folds master and slave latches when there is aredundant interaction between the clock and resetsignals.

-NOSEQ_Constant Does not propagate constant data through latches andregisters. This is the default.

-SEQ_Constant Propagates constant data through latches andregisters.

-NOGATED_Clock Does not remodel gated-clock sequential instances.This is the default.

-GATED_Clock Remodels the gated-clock logic of the clock port of aDFF. If the clock pin cannot be automaticallydetermined, use the ADD CLOCK command to definethe clock pin.

-DFF_TO_DLAT_ZERO Converts a DFF to a DLAT if the clock port is zero.This is the default.

-NODFF_TO_DLAT_ZERO Does not convert a DFF to a DLAT if the clock port iszero.

-DFF_TO_DLAT_FEEDBACK Converts a DFF to a DLAT if the Q output feeds backto the D input. This is the default.

-NODFF_TO_DLAT_FEEDBACK Does not convert a DFF to a DLAT if the Q output hasfeedbacks to the D input.

-NOLOOP_AS_DLAT Does not use a DLAT to model a combinational loop.This is the default.

-LOOP_AS_DLAT Uses a DLAT to model a combinational loop.



-SEQ_CONSTANT_FEEDBACK Remodels registers that also have feedback toconstants. Use this option with -seq_constant. Thisis the default.

-NOSEQ_CONSTANT_FEEDBACK Does not remodel registers that also have feedback toconstants. Use this option with -seq_constant.

-SEQ_CONSTANT_X_TO Optimizes a flop to a constant value (either zero orone) when the flop is always in a don’t care (X) state.Use this with the -seq_constant switch.

0: Optimizes a flop to a constant zero.

1: Optimizes a flop to a constant one.

-AUTO_MODELING Enables selective modeling for designs that can bemapped mostly by name. This option applies only tosequential constants. This is the default.

-NOAUTO_MODELING Disables the auto modeling feature.

-OUTPUT_Z Checks for floating conditions at top-level output portsand inputs to blackboxes. This is the default.

-NOOUTPUT_Z Does not check for floating conditions at top-leveloutput ports and inputs to blackboxes.

-NOBBOX_MERGE Does not perform automatic blackbox merging. This isthe default.

-BBOX_MERGE Performs automatic blackbox merging.

-SHOW_MESSAGE_NAME Prints message names to the log as they occur.

-NOKEEP_IGnored_PO Does not retain the ignored primary outputs (addedwith the ADD IGNORED OUTPUTS command) in theflattened netlist. This is the default.

-KEEP_IGnored_PO Retains the ignored primary outputs (added with theADD IGNORED OUTPUTS command) in the flattenednetlist. These ignored primary outputs appear asunreachable unmapped points in the design.

-CUT_REMOVE_REDUNDANT Removes as many redundant cuts as possible. Usethis option if you suspect that the software insertedmore cuts than necessary.



Examplesset flatten model -latch_fold

set flatten model -pin

set flatten model -latch_transparent

set flatten model -nomap


set flatten model -nodff_to_dlat_zero

set flatten model -seq_constant -noseq_constant_feedback

set flatten model -gated_clock

set flatten model -seq_redundant

set flatten model -all_seq_merge

set flatten model -nodff_to_dlat_feedback

Related Commands

READ MAPPED POINTS

REMODEL

REPORT ENVIRONMENT

REPORT MESSAGES

SET GATE REPORT

-NOECO Does not preserve extra circuit information for modelflattening. This is the default.

-ECO Preserves extra circuit information during modelflattening for subsequent ANALYZE ECO commandruns in the Conformal ECO flow.



SET FPGA TECHNOLOGYSET FPga Technology

[NONE | VIRTEX | VIRTEX2](Setup Mode)

Note: This command is an FPGA command.

Turns on FPGA-specific processing. It is included in the fpgaR2G.do dofile.

Parameters

NONE Does not turn on any FPGA-specific processing. This is thedefault.

VIRTEX Turns on the Xilinx Virtex processing.

VIRTEX2 Turns on Virtex2 processing.



SET GATE REPORTSET GAte Report

[-PRImitive | -DESign][-DYNamic | -NODYNamic][-FUNction | -STRucture](Setup / LEC Mode)

Specifies the detail level of gate reports in the Conformal gate information display. Gate reportfeatures include the following:

■ Returns information at the design or primitive level

■ Displays the dynamic constraints

■ Displays the fanin cone of the zero/one gates

By default, this command reports gate information at the primitive level, displays the dynamicconstraints, and does not display the fanin cone of the zero or one gates.

Use the REPORT ENVIRONMENT command to display the gate report level settings.

Note: If the gate report is set to “Design”, you must use the SET FLATTEN MODEL commandwith the -pin_keep option in the Setup system mode. The gate information is reported inthe LEC system mode.

Parameters

-PRImitive Displays the gate report information at the primitive level. Thisis the default.

-DESign Displays the gate report information at the design level.

-DYNamic Displays the dynamic constraints in the gate report information.This is the default.

-NODYNamic Does not display the dynamic constraints in the gate reportinformation.

-FUNction Does not display the fanin cone of the zero/one gates in thegate report information. This is the default.

-STRucture Displays the fanin cone of the zero/one gates in the gate reportinformation.



Related Commands

REPORT ENVIRONMENT

REPORT GATE

SET FLATTEN MODEL



SET GUISET GUi

[ON | OFf](Setup / LEC Mode)

Switches Conformal to the GUI mode from the non-GUI mode or to the non-GUI mode fromthe GUI mode.

Parameters

ON Switches to the GUI mode. This option is the initial systemdefault.

OFf Switches to the non-GUI mode.



SET HDL DIAGNOSISSET HDl Diagnosis

<OFf | ON>(Setup Mode)

Enables the debugging features before reading design and libraries. By default, the sourcecode debugging features (such as tracing drivers and loads) are off. Execute this commandbefore READ LIBRARY and READ DESIGN.

Parameters

Related Commands

DIAGNOSE

REPORT TEST VECTOR

OFf Disables the Source Code Manager’s debugging features. Thisoption is the initial system default.

ON Enables the Source Code Manager’s debugging features.



SET HDL OPTIONSET HDl Option

[-VERILOG_OUTOFBOUNDWrite <Noeffect | X>][-VHDL_OUTOFBOUNDWrite <X | Noeffect>][-VERILOG_OUTOFBOUNDRead <PARTIAL_X | ALL_X>][-VHDL_OUTOFBOUNDRead <ALL_X | PARTIAL_X>][-VERILOG_TRIMINDex <OFF | ON>][-VHDL_TRIMINDex <OFF | ON>](Setup Mode)

Controls the interpretation of some RTL semantics.

Parameters

-VERILOG_OUTOFBOUNDWrite <Noeffect | X>

Controls the interpretation of Verilog bit (or part)-select of vectortyped variable/signal when index is out of the defined indexrange.

Noeffect specifies that out-of-bound writing will have noeffect. This is the default.

X specifies that when there is out-of-bound writing, the relatedpart of the variable/signal is assigned value ’x’.

-VHDL_OUTOFBOUNDWrite <X | Noeffect>

Controls the interpretation of VHDL bit (or part)-select of vectortyped variable/signal when index is out of the defined indexrange.

X specifies that when there is out-of-bound writing, the relatedpart of the variable/signal is assigned value ’x’. This is thedefault.

Noeffect specifies that out-of-bound writing will have noeffect.



-VERILOG_OUTOFBOUNDRead <PARTIAL_X | ALL_X>

Controls the interpretation of Verilog bit (or part)-select of vectortyped variable/signal when index is out of the defined indexrange.

PARTIAL_X specifies that out-of-bound reading will havevalues from the valid index locations of the vector, and will have’x’ value from the invalid (i.e. out of bound) locations of thevector. This is the default.

ALL_X specifies that when there is out-of-bound reading, theselected portion of the vector will be treated as all ’x’ values.

-VHDL_OUTOFBOUNDRead <ALL_X | PARTIAL_X>

Controls the interpretation of VHDL bit (or part)-select of vectortyped variable/signal when index is out of the defined indexrange.

ALL_X specifies that when there is out-of-bound reading, theselected portion of the vector will be treated as all ’x’ values.This is the default.

PARTIAL_X specifies that out-of-bound reading will havevalues from the valid index locations of the vector, and will have’x’ value from the invalid (i.e. out of bound) locations of thevector.

-VERILOG_TRIMINDex <OFF | ON>

ON controls to trim the index to necessary bits for the Verilogfiles. OFF is the command default.

Note: This option might be used to verify implementations inwhich indexes are intentionally trimmed.

-VHDL_TRIMINDex <OFF | ON>

ON controls to trim the index to necessary bits for the VHDLfiles. OFF is the command default.

Note: This option might be used to verify implementations inwhich indexes are intentionally trimmed.



Examples

The following examples use the Verilog language to show how to control index out of boundhandling. You can use similar VHDL command options to control the interpretations for theVHDL language designs.

In the following RTL-1 example, the index range of variable mem is 0 to 2.

RTL-1wire a;reg [2:0] index;reg [2:0] mem;always @(*) mem[index] = a;

If index is greater than 2, it is out of the index range. Some synthesis tools might intentionallyinterpret the RTL the same as with the following RTL-2 example:

RTL-2wire a;reg[2:0] index;reg[2:0] mem;always @(*) mem[index[1:0]] = a;

But with simulation, RTL-1 and RTL-2 behave differently.

With the Conformal Equivalence Checking software, when running the command:

set hdl option -verilog_outofboundwrite x

then

■ index=0 : mem[0] is assigned to the value of a



■ index=3,4,5,6,7 : mem[0], mem[1], and mem[2]are assigned to the value of 1’bx.

This interpretation assumes that out-of-bound writing will not happen, and consequentlyignores the behavior difference when index is greater than 2.



When running the command:

set hdl option -verilog_outofboundwrite noeffect

then




■ index=3,4,5,6,7 : mem[0], mem[1], and mem[2]will not be affected with theircurrent value.

Based on this interpretation, RTL-1 and RTL-2 are considered functional non-equivalent, andconsequently the implementation from RTL-2 will be non-equivalent to RTL-1.

Using the same RTL-1 and RTL-2 examples, when running the command:

set hdl option -verilog_trimindex on

The Conformal Equivalence Checking software will interpret RTL-1 as RTL-2 by ignoringindex[2] in the expression mem[index] (RTL-1). With the -verilog_trimindex onoption, RTL-1 and RTL-2 are considered equivalent.

Related Commands

ELABORATE DESIGN

READ DESIGN



SET IMPLEMENTATIONSET IMPlementation

<MULtiplier [-AUTO | -CSA | -WALL | -RCA | -NBW | -BKA] |DIVider [-RPL | -BLA]

[-CLA | -CLA2][-OVERFLOW_TRUNCATE | -OVERFLOW_SATURATE | -OVERFLOW_DONTCARE][-ALL_div | -RTL_div | -DW_div]>

[-Both | -Golden | -Revised](Setup Mode)

Specifies the multiplier and divider implementations in the Golden and Revised designs.Execute this command before READ LIBRARY and READ DESIGN.

The types of multipliers supported are:

■ Carry Save Adder (CSA)

■ Ripple Carry Adder (RCA)

■ Booth Encoded-Wallace tree (WALL)

■ Non-Booth Encoded-Wallace tree (NBW)

■ Brent-Kung Adder (BKA)

Default Multiplier Implementation Is Automatically Determined

By default, Conformal automatically determines the multiplier implementation as follows:

If a_width + b_width <42, Conformal chooses NBW.

If a_width + b_width >=42, Conformal chooses WALL.

The -auto default setting is best suited when you are using Synopsys Design Compiler withDesignWare Foundation. If you are not using DesignWare Foundation, it is probably best tospecify -csa.

The types of dividers supported are:

■ Ripple Borrow (RPL)

■ Borrow Look-Ahead

■ Carry Look-Ahead

■ Carry Look-Ahead, 2-Way



Required Options

With this command, you must include either the multiplier or divider option;however, Conformal permits both options, as shown below:

set implementation multiplier -csa divider -bla

Specifying Multiplier Implementations with Directives

Specify the multiplier implementation with a Synopsys or Conformal directive in the design.(See the Set Implementation examples below and in the Examples section of this command.)

■ Synopsys Directive:

// synopsys dc_script_begin

// set_implementation <csa | rca | wall | nbw | bka> [instance_name]

// synopsys dc_script_end

■ Conformal Directive:

// conformal multiplier <csa | rca | wall | nbw | bka>

Note: Use either directive for multipliers specified with operational assignments. ForDesignWare instances, use only the Synopsys directive along with the instance name.

Parameters

MULtiplier By default, Conformal automatically determines the multiplierimplementation as follows:

If a_width + b_width < = 52, Conformal chooses NBW.If a_width + b_width > 52, Conformal chooses WALL.

The multiplier type is one of the following:

-AUTO The -auto default setting is best suitedwhen you are using Synopsys DesignCompiler with DesignWare Foundation. Ifyou are not using DesignWare Foundation,it is probably best to specify -csa. This isthe default.

-CSA Carry Save Adder

-WALL Booth Encoded, Wallace tree

-RCA Ripple Carry Adder



-NBW Non-Booth Encoded, Wallace tree

-BKA Brent-Kung Adder

DIVider The divider type is one of the following:

-RPL Ripple Borrow, which is the initial default

-BLA Borrow Look-Ahead

-CLA Carry Look-Ahead

-CLA2 Carry Look-Ahead, 2-Way

The following options specify how to treat over signed divisionoverflow, which is when a minimum negative value is divided by -1.

-OVERFLOW_TRUNCATE Truncates results as defined bytwos-complement arithmetic. This is thedefault.

-OVERFLOW_SATURATE Saturates results to the largest positivevalue.

-OVERFLOW_DONTCARE Treats overflow results as don’t cares.

DIVider can be inferred from either DW_div instantation or RTLarithmetic operation (for example, ‘/’ in Verilog). The following optionsspecify the divider class for the preceeding settings.

-ALL_div Specifies that dividers are inferred fromboth RTL and DW. This is the default.

-RTL_div Specifies that dividers are only inferred fromRTL operation.

-DW_div Specifies that dividers are only inferred fromDW_div instantiation.

-Both Specifies the implementation type for both the Golden and Reviseddesigns. This is the default.

-Golden Specifies the implementation type for the Golden design.

-Revised Specifies the implementation type for the Revised design.



Examples

Synopsys Directive

The following examples illustrate Conformal-supported use of the Synopsys directive:


// set_implementation wall


assign out = in1 * in2;


// set_implementation wall U1


DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1’b0), .PRODUCT (out));


// set_implementation wall cla2 U1


DW_div #(A_width, B_width, TC_mode, REM_mode) U1 (...);

Conformal Directive

The following example illustrates the Conformal directive.

Note: The directive applies to only the statement on the following line. In this example, it doesnot apply to assign out2…:

// conformal multiplier wall

assign out1 = in1 * in2;


Related Command

READ DESIGN



SET LOG FILESET LOg File

[<filename>[-Replace | -Append][-PROGRESS | -NOPROGRESS][-NOBACkup]](Setup / LEC Mode)

Writes the transcript to a specified file. The commands and any output information write tothis file. As you review the file, identify commands by the keyword:

//Command:

When you want the Conformal software to stop writing to the log file, enter the commandwithout any options.

Note: If the filename you specify already exists, you must use either the -replace or-append option. If you do not include an option, the Conformal software generates an errormessage that the file exists. If you receive this message, reenter the command with either anew filename or the appropriate option. If the filename is not writable, the software writes it tothe /tmp directory.

If you are writing the transcript to a file, you might want to turn off the screen transcript displaywith the SET SCREEN DISPLAY command. (If you do not specify otherwise, the transcriptprints to the screen.)

To store log files based on the software version, use the LEC_VERSION environment variable.For example:

set log file lec.$LEC_VERSION.log -replace

To verify the current log file setting, use the REPORT ENVIRONMENT command.

Parameters

<filename> Writes the transcript run to this file.

-Replace If the specified filename already exists, overwrites the contentsof that file.

-Append Appends the transcript run to the end of the specified filename.

-PROGRESS Writes the percentage completion progress to the log file. Thisis the default.

-NOPROGRESS Does not write the percentage completion progress to the logfile.



Related Commands

REPORT ENVIRONMENT

REPORT COMMAND PROFILE

SET COMMAND PROFILE

SET SCREEN DISPLAY

-NOBACkup Does not create a backup file.

Note: If you do not specify this option, it will create a backup filewhen you replace or append a file.



SET LOWPOWER OPTIONSET LOwpower Option

[-NOauto | -Auto |[-Retention_cells_check][-Isolation_cells_check][-Level_shifter_cells_check][-POWER_domain_check

[-GOLDen_power_domain [CPF | PHYsical | HYbrid]][-REVised_power_domain [PHYsical | CPF | HYbrid]]

][-MERge](Setup Mode)


Enables the low power check for different types of low power cells. Low power checkingincludes either the technology mapping check or the equivalence check (EC), or both,depending on the low power cell type.

For retention-register cells, only the technology mapping check is performed. For isolationcells and level-shifter cells, both technology mapping check and EC is performed. For moreinformation on these low power checks and cell types, see CHECK LOWPOWER CELLS.

Parameters

-NOauto Does not automatically enable the low power check. This isthe default.

-Auto Enables the low power check for the isolation cells, level-shiftercells, and state retention cells.

-Retention_cells_check

Enables the low power check for state retention cells only.

-Isolation_cells_check

Enables the low power check for isolation cells only.

-Level_shifter_cells_check

Enables the low power check for level-shifter cells only.

-POWER_domain_check

Enables the power domain consistency check for the sequentialcompare points.



Examples

The following commands perform low power checking that includes both the technologymapping check and the equivalence check:

set lowpower option -auto

set lowpower option -retention -level_shifter

-GOLDen_power_domain [CPF | PHYsical | HYbrid]

Specifies the mechanism for obtaining the power domains inthe Golden design to do the power domain consistency check.

■ CPF—obtains the power domain from the CPFspecification. This is default for the Golden design.

■ PHYsical—extracts the power domains by tracing thepower and the ground pins.

■ HYbrid—extracts the power domains by tracing the powerand the ground pins. If the power domain cannot beobtained by tracing the power and ground pins, the softwareobtains the power domain from the CPF specification.

-REVised_power_domain [PHYsical | CPF | HYbrid]

Specifies the mechanism for obtaining the power domains inthe Revised design to do the power domain consistency check.

■ PHYsical—extracts the power domains by tracing thepower and the ground pins. This is default for the Reviseddesign.

■ CPF—obtains the power domain from the CPFspecification.

■ HYbrid—extracts the power domains by tracing the powerand the ground pins. If the power domain cannot beobtained by tracing the power and ground pins, the softwareobtains the power domain from the CPF specification.

-MERge Merges the equivalent outputs of the low power cells. This isenabled only for isolation and level-shifter cells.



Related Commands

ADD LOWPOWER CELLS







SET MAPPING METHODSET MApping Method

< [-NAme < First | Guide | Only> |-NOName][-NOPhase | -Phase][-NOSensitive | -Sensitive]>

[-NOUNREACH | -UNREACH][-REPORT_UNREACH | -NOREPORT_UNREACH][-NAME_EFFORT <HI | LOW>][-NONETS | -NETS][-BBOX_NAme_match | -NOBBOX_NAme_match][-REPORT_SUMMARY_SHOW_ZERO_COUNT][-TIMEOUT_minutes <number>][-PHASEMAPMODEL](Setup / LEC Mode)

Specifies the mapping method, phase, case sensitivity, and handling for unreachable pointsand blackboxes when Conformal maps the key points. With the -name option, paths of thegates indicate some type of starting point to map key points. The system default is namefirst. This default lets Conformal first map key points with the same paths, then map theremaining unresolved key points with a mapping algorithm. All remaining unresolved keypoints become unmapped points.

Use the REPORT ENVIRONMENT command to display the setting of the mapping method andphase.

Parameters

-NAme The mapping method operates under the modes described asfollows:

First Conformal maps the key points with thepaths of the gates first. Then, Conformaluses the mapping algorithm to map the restof the key points. This option is thesystem default.

Guide Conformal maps key points with a mappingalgorithm first.

Only Conformal only maps the key points basedon the paths of the gates

-NOName Does not map key points based on the paths of the gates. If themapping algorithm cannot map a key point, it remainsunmapped.



-NOPhase Does not map key points with an inverted phase. This is thedefault.

These key points are represented with the symbol “+”.Comparison results are either equivalent or nonequivalent.

-Phase Maps key points with an inverted phase.

These key points are represented with the symbol “-”.

Comparison results are either inverted-equivalent ornonequivalent.

-NOSensitive Specifies that key point names are not case sensitive. This isthe default.

-Sensitive Specifies that key point names are case sensitive.

-NOUNREACH Does not map unreachable key points. Unreachable key pointsare those that don’t eventually affect the PO of the design. Thisis the default.

-UNREACH Maps unreachable key points. Unreachable key points arethose that don’t eventually affect the PO of the design.

-REPORT_UNREACH Reports unreachable key points. This is the default.

-NOREPORT_UNREACH Does not report unreachable key points.

-NAME_EFFORT Uses the specified amount of effort for key point mapping. Thisoption eliminates the need for simple renaming rules such as:

add renaming rule R1 “reg\[%d\]” “reg(@1)”-golden, which maps the following Golden and Reviseddesign DFFs:

Golden: DFF A/B/C_reg[5]Revised: DFF A/B/C_reg(5)

This option applies to only DFFs and DLATs.

HI This option is the system default level. Iteliminates the need for simple renamingrules.

LOW Uses low effort for key point mapping

-NONETS Does not map according to net names. This is the default.

-NETS Maps key points according to net names.



Related Commands

ADD MAPPED POINTS

ADD RENAMING RULE



MAP KEY POINTS

REPORT ENVIRONMENT




-BBOX_NAme_match Maps blackboxes only if both the module names and instancenames match. This is the default.

-NOBBOX_NAme_match Maps blackboxes if instance names match.

-REPORT_SUMMARY_SHOW_ZERO_COUNT

Specifies that the summary will be reported with ZERO count ifthere is an unmapped point of the same type either in Golden orRevised design.

-TIMEOUT_minutes <number>

Specifies the number of minutes for the mapping process tocontinue before it is interrupted. The default value is zero (0),which disables this check.

-PHASEMAPMODEL Uses the phase information provided by the ADD MAPPINGMODEL command to determine the mapping phase. Use thisoption when there is a phase mismatched between thesimulation model and the synthesis model.



SET MOS MODELSET MOs Model

<NMOS/PMOS>[Spice_model_name](LEC Mode)


Specifies the MOS model names used in SPICE. You can then re-read the SPICE netlist.

When reading in SPICE netlists, the parser automatically identifies transistor model namesas PMOS and NMOS types. However, if you have models that were not defined using .MODELstatements, the parser identifies them as ERROR. Instead of altering your SPICE file, you canuse this command.

Note: You must run this command before reading in the SPICE netlist.

Parameters

NMOS Defines the model name as an N-Channel device.

PMOS Defines the model name as a P-Channel device.

Spice_model_name Specifies a single or list of names for which to define models.This is necessary only if you have a P-Channel model namesnot starting with a ‘p,’ and N-Channel model names not startingwith ‘n.’



SET MULTIPLIER IMPLEMENTATIONSET MUltiplier Implementation

<AUTO | CSA | RCA | WALL | NBW | BKA>[-Both | -Golden | -Revised][-Verbose](Setup Mode)

Specifies the multiplier implementation in the Golden and Revised designs. Execute thiscommand before READ LIBRARY and READ DESIGN.

The types of multipliers you can specify are:

■ Carry Save Adder (CSA)

■ Ripple Carry Adder (RCA)

■ Booth Encoded-Wallace tree (WALL)

■ Non-Booth Encoded-Wallace tree (NBW) multipliers

■ Brent-Kung Adder (BKA)

The CSA multiplier implementation is the default.

An alternate method for specifying the multiplier implementation is to use a Synopsys orConformal directive in the design. See the following set multiplier implementation examplesfor using these directives and those shown in the “Examples” section below.

Synopsys Directive:// synopsys dc_script_begin

// set_implementation <csa | rca | wall | nbw | bka> [instance_name]


Conformal Directive:// conformal multiplier <csa | rca | wall | nbw | bka>

Note: Use either directive for multipliers specified with operational assignments. However, forDesignWare instances, use only the Synopsys directive along with the instance name.



Parameters

Examples

Synopsys Directive

The following two examples illustrate Conformal-supported use of the Synopsys directive:


// set_implementation wall

AUTO The system default for Conformal is that it automaticallydetermines the multiplier implementation as follows:

If a_width + b_width < = 52, Conformal chooses NBW.

If a_width + b_width > 52, Conformal chooses WALL.

The auto default setting is best suited when you are usingSynopsys Design Compiler with DesignWare Foundation. If youare not using DesignWare Foundation, it is probably best tospecify csa.

CSA Specifies that the multiplier type is a Carry Save Adder (CSA)multiplier.

RCA Specifies that the multiplier type is a Ripple Carry Adder (RCA)multiplier.

WALL Specifies that the multiplier type is a Booth Encoded, Wallacetree multiplier.

NBW Specifies that the multiplier type is a non-Booth Encoded,Wallace tree multiplier.

BKA Specifies that the multiplier type is a Brent-Kung Adder (BKA).

-Both Specifies the multiplier implementation type for both the Goldenand Revised designs. This is the default.

-Golden Specifies the multiplier implementation type for the Goldendesign.

-Revised Specifies the multiplier implementation type for the Reviseddesign.





assign out = in1 * in2;


// set_implementation wall U1


DW02_mult #(10,10) U1 (.A (in1), .B (in2), .TC (1’b0), .PRODUCT (out));

Conformal Directive

The following example illustrates the Conformal directive.

Note: The directive applies to only the statement on the following line. In this example, it doesnot apply to assign out2…:

// conformal multiplier wall



Related Command

READ DESIGN



SET MULTIPLIER OPTIONSET MUltiplier Option

[-NOAUTO | -AUTO][-NOCDP_INFO | -CDP_INFO][-Verbose](Setup Mode)

Specifies whether Conformal will automatically analyze multipliers when switching fromSetup to LEC mode. Additionally, use the -cdp_info option if you want Conformal to letyou know when Conformal Ultra will be helpful.

Parameters

Related Commands

ANALYZE DATAPATH

ANALYZE MULTIPLIER



SET DATAPATH OPTION

SET FLATTEN MODEL

-NOAUTO Does not automatically analyze multipliers when switching fromSetup to LEC mode. This is the default.

-AUTO Automatically analyzes multipliers when switching from Setupto LEC mode.

-NOCDP_INFO Does not display a message when Conformal Ultra canenhance multiplier analysis. This is the default.

-CDP_INFO Displays a message when Conformal Ultra can enhancemultiplier analysis.




SET NAMING RULESET NAming Rule

<<<string> -Hierarchical_separator> |<<string> -Tristate> |<<string> -REGister> |<<string> -Inverted_pin_extension> |<<string> -Parameter> |<<left_string> <right_string> -Array_delimiter> |<<left_string> <right_string> -Field_delimiter> |<<label_string> <forgen_string> <instance_string> -INStance> |<<label_string> <forgen_string> <variable_string> -VARiable>>[-Both | -Golden | -REvised](Setup Mode)

Specifies the naming rules for an RTL or hierarchical design. Execute this command beforeREAD LIBRARY and READ DESIGN.

Naming rules for RTL designs specify the following:

■ Hierarchical separator

■ Tristate and register names

■ Array delimiter

Naming rules for hierarchical designs specify the hierarchical separator.

■ Use the hierarchical separator string when matching key points between the Golden andRevised designs. The hierarchical separator setting has no effect on the way key pointsare reported (for example, when you use the REPORT GATE command).

■ Use the register, tristate, and array delimiter strings to instruct the Verilog RTL compilerhow key point names (inferred flip-flop/latch instance names) are constructed.

■ Use the following example to understand the correct use of the inverted pin extensionstring.Golden design: pin aRevised design: inverted pin a_BARType the following command:

set naming rule _BAR -inverted_pin_extension -golden

■ The parameter string defines the name of the new parameterized module name whennew parameters are passed. When an existing module has defined parameters and it isbeing instantiated with new parameters, a duplicate module is created with the specifiedparameter string.



■ The instance strings define the way instance names are generated. Different synthesistools use different schemes to generate instance names. To facilitate the compareprocess, you can use this command to instruct Conformal to generate instance namesin the same way as the synthesis tool.

■ The variable strings define the way variable names are generated.

Each string for all of the settings must be enclosed in double quotes (“ ”). These double quotescan be empty.

Use the REPORT ENVIRONMENT command to display the settings for the naming rules for theGolden and Revised designs.

Parameters

<string> -Hierarchical_separator

A character or string that specifies the hierarchical separator.The default is “/”.

<string> -Tristate A string that specifies the tristate naming. The default is“%s_tri”. The string must contain exactly one “%s”.

<string> -REGister A string that specifies the register naming. The default is“%s_reg”. The string must contain exactly one “%s”.

<string> -Inverted_pin_extension

A string that specifies the inverted pin extension. This optionappends the string to the Golden or Revised pin name. Refer tothe example shown in “Definition”.

<string> -Parameter A string that specifies parameter naming. The default is“_%s”.

<left_string> <right_string> -Array_delimiter

Two strings that specify the left and right array delimiter. Thedefault is “[” and “]” for the left and right string.

<left_string> <right_string> -Field_delimiter

Two strings that specify the left and right record field delimiterfor VHDL designs. The default is “[” and “]” for the left andright string.

label_string forgen_string instance_string -instance



forgen_string applies to “for generate” blocks that have aname and index, label_string applies to all of the otherblocks.

label_string specifies how to include the block name in theinstance name, where:

■ %L specifies the block name.

■ %s specifies the current instance name.

The default setting for label_string is %s.

For example, instance ins1 is inside block b1, and b2 is insideb1. If you specify a label_string of %L_%s, this commandgenerates the instance name b1_b2_ins1. If you specify alabel_string of %s[%L], this command generates theinstance name ins1[b1][b2].

forgen_string specifies how to use the generated blockname and loop index to form an instance name, where:

■ %L specifies the block name.

■ %s specifies the current instance name.

■ %d specifies the block index.

The default setting for forgen_string is %s_%d.

For example, instance ins1 is inside block b2 with a forloopindex of 3, and b2 is inside block b1 with a forloop index of 0.If you specify a forgen_string of %L[%d].%s, thiscommand generates the instance name b1[0].b2[3].ins1.

instance_string denotes how to specify the instance name,where %s specifies the current instance name. For example,your current instance name is ins1. If you specify aninstance_string of %s_INS, this command replaces theinstance name with ins1_INS. Note: The result of this optionreplaces the %s in label_string and forgen_string.

The default setting for instance_string is %s.

label_string forgen_string variable_string -variable



Examplesset naming rule “:” -hierarchical_separator -golden

set naming rule “register_%s” -register -revised

set naming rule “tristate_%s” -tristate

set naming rule “<” “>” -array -golden

For instance name generation, consider the following sample Verilog code:

generatebegin: blkAfor (i=0;i<=0;i=i+1) begin: forblkBor n1(a,b,c);

The variable naming scheme is similar to the instance namingscheme.

forgen_string applies to generated blocks that have a nameand index, label_string applies to all of the other blocks.

label_string specifies how to include the block name in thevariable name (applies to all variables inside the “for generate”block), where:

■ %L specifies the generated block name.

■ %s specifies the current variable name.

The default setting for label_string is %s.

forgen_string specifies how to use the generated blockname and loop index to form a variable name, where:

■ %L specifies the generated block name.

■ %s specifies the current variable name.

■ %d specifies the generated block index.

The default setting for forgen_string is %s_%d.

variable_string denotes how to specify the variable name,where %s specifies the current variable name. The defaultsetting for variable_string is %s.

-Both The naming rule applies to both the Golden and Reviseddesigns. This is the default.

-Golden The naming rule applies to the Golden design alone.

-REvised The naming rule applies to the Revised design alone.



for (j=23;j<=23;j=j+1) begin: forblkCand n2(d,e,f);

endbegin : blkDnor n3 (g,h,i);

endend

endendgenerate

■ set naming rule "%s" "%s_%d" "%s" -instance

This renames instances n1, n2 and n3 as n1_0, n2_0_23, and n3_0, respectively. Thisis also the default setting.

■ set naming rule "%s" "%L[%d].%s" "%s_INS" -instance

This renames instances n1, n2 and n3 as forblkB[0].n1_INS,forblkB[0].forblkC[23].n2_INS, and forblkB[0].n3_INS, respectively.

■ set naming rule "%L_%s" "%L[%d].%s" "%s" -instance

This renames instances n1, n2 and n3 as blkA_forblkB[0].n1,blkA_forblkB[0].forblkC[23].n2, and blkA_forblkB[0].blkD_n3,respectively.

Related Commands

ADD MAPPED POINTS

ADD RENAMING RULE



MAP KEY POINTS

READ DESIGN

REPORT ENVIRONMENT




TEST RENAMING RULE



SET PARALLEL OPTIONSET PARAllel Option

[-MAX_Remote <integer>][-SUBMIT_COMMAND_LINE <string>][-KILL_COMMAND_LINE <string>][-KEEP_DIR][-RESERVE_LICense <integer>](LEC / Setup Mode)


Sets the parameters for parallel processing. This command should be run immediately beforethe RUN PARALLEL COMPARISON command.

Parameters

-MAX_Remote Specifies the maximum number of remotes used for performingthe tasks. The number of available CPUs is considered as thatnumber of remotes. However, this is just a recommendation.The Conformal software will check the number of availablelicenses and might launch remote jobs less than the numberspecified.

-SUBMIT_COMMAND_LINE

Specifies the submit command interface.

The default value is:

bsub -o <logdir>/<jobnum>_LSF.log<submit_options> <command>

The keywords <logdir>, <jobnum>, and <command> aredetermined by the software.

You can specify <submit_options> with the RUN PARALLELCOMPARE command.

-KILL_COMMAND_LINE Specifies the kill command interface. The default value isbkill <jobid>. The keyword <jobid> is determined by thesoftware.

-KEEP_DIR Specifies that the directory created during parallel processingwill be saved.

-RESERVE_LICense Specifies the number of XL licenses to be reserved for otheruse.



Related Commands

RUN PARALLEL COMPARE



SET RETIMING OPTIONSET REtiming Option

[-NOAUTO | -AUTO][-NORETIMED_MODULE | -RETIMED_MODULE](Setup Mode)

Specifies whether the Conformal software automatically performs retiming analysis fordesigns when switching from Setup to LEC mode. According to the structure of the designs,the software automatically determines whether to use forward or backward pipeline retiming,or general retiming. The results of analysis enable the software to automatically resolveretiming designs.

Tip

Use the ADD MODULE ATTRIBUTE command to attach the PIPELINE_Retimeattribute to a module.

Parameters

Related Commands


ANALYZE RETIMING

-NOAUTO Does not automatically analyze retiming when switching fromSetup to LEC mode. This is the default.

-AUTO Automatically analyzes retiming when switching from Setup toLEC mode.

-NORETIMED_MODULE Performs retiming analysis on all modules with or without thePIPELINE_Retime attribute. This is the default.

-RETIMED_MODULE Performs retiming analysis only on modules with thePIPELINE_Retime attribute.



SET ROOT MODULESET ROot Module

<module_name>[-Golden | -Revised | -Both](Setup Mode)

Specifies the name of the root module for the Golden and Revised designs. The systemdefault specifies that when the design is read, Conformal automatically assigns the rootmodule. Thus, the SET ROOT MODULE command overrides the automatic assignment.

Use the REPORT ENVIRONMENT command to display the settings for the root module for theGolden and Revised designs.

Parameters

Related Commands

READ DESIGN

REPORT ENVIRONMENT

module_name This module is the root. This assignment overrides theautomatic root module assignment Conformal makes when youuse the READ DESIGN command.

-Golden Assigns the root module name for the Golden design. This isthe default.

-Revised Assigns the root module name for the Revised design.

-Both Assigns the root module name for both the Golden and Reviseddesigns.



SET RULE FILTERSET RUle Filter

<-ROOT_HIER_only>[-Golden | -Revised](Setup Mode)

Filters out rules that occur in modules outside the root hierarchy. It is a means to removeunnecessary rule reporting and focus only on the root module's hierarchy.

Use the REPORT RULE CHECK command with the -summary option to display all of the rulesand their settings and occurrences.

Parameters

Related Commands

READ DESIGN

READ LIBRARY

REPORT RULE CHECK

-ROOT_HIER_only Filters out rules that occur in modules outside the roothierarchy.

-Golden Applies the filter to the Golden design and library. This is thedefault.

-Revised Applies the filter to the Revised design and library.



SET RULE HANDLINGSET RUle Handling

<[<rule_name*…> [-Warning | -Error [-CONTinue] | -Ignore | -Note]][[-EXCLude | -INCLude] <-MODule | -DESIGN_FILE | -LIB_FILE> <name*…>]>

[ |-Design | -Library][-Both | -Golden | -Revised](Setup Mode)

Specifies the rule handling when reading in the designs and libraries or exclude the specifiedmodule, design file, library file, or rule from rule checking. Most rules are either warnings ornotes. Execute this command before READ LIBRARY and READ DESIGN.

Note: Multiple SET RULE HANDLING commands can be specified, and the effects arecumulative.

Use the REPORT RULE CHECK command with the -summary option to display all of the rulesand their settings and occurrences.

See the Encounter Conformal Equivalence Checking User Guide for rule definitions andsample cases.

Note: The wildcard (*) represents any zero or more characters in rule names.

Parameters

rule_name*… Changes rule handling for the specified rules. This supportswildcards.

-Warning The rule handling will be a warningmessage. This is the default.

-Error [-CONTinue]

The rule handling will be an error message.With the -CONTinue option, the programwill continue to run instead of erroring out.

-Ignore The rule handling will be ignore. SeeREPORT RULE CHECK to see how thisseverity level affects reporting.

-Note The rule handling will be a note.



Related Commands

READ DESIGN

READ LIBRARY

REPORT RULE CHECK

-EXCLude | -INCLude

Removes the unwanted rules. All rules will be checked bydefault.

-EXCLude removes some rules in the specified list.

-INCLude removes all rules not in the specified list.

-MODule Excludes the specified module from the RTLRule check.

-DESign_file Excludes the specified design file from theRTL Rule check.

-LIB_file Excludes the specified library file from theRTL Rule check.

name*… Specifies the name of the module, designfile, or library file.

-Design Applies the rule handling to only the designs.

If you do not specify -design or -library, Conformalapplies the rule handling to both designs and libraries.

-Library Applies the rule handling to only the libraries.

If you do not specify -design or -library, Conformalapplies the rule handling to both designs and libraries.

-Both Applies the rule handling to both the Golden and Reviseddesigns and libraries. This is the default.

-Golden Applies the rule handling to the Golden design and library.

-Revised Applies the rule handling to the Revised design and library.



SET SCREEN DISPLAYSET SCreen Display

<ON | OFf>(Setup / LEC Mode)

Specifies whether the transcript output is displayed on the terminal screen.

Tip

If the screen display is set to off, use the SET LOG FILE command to save thetranscript to a file.

Use the REPORT ENVIRONMENT command to display the setting for the screen display. Bydefault, screen display is on.

Parameters

Related Commands

REPORT ENVIRONMENT

SET LOG FILE

ON Displays the transcript on the terminal screen. This option isthe system default.

OFf Does not display the transcript on the terminal screen.



SET SPICE OPTIONSET SPIce OPTion

[-BUlk | -NOBUlk][-BBOX | -NOBBox][-NOADDGLOBALPINs | -ADDGLOBALPINs][-NOKEep_InstanceX | -KEep_InstanceX](Setup Mode)


Specifies options for reading the SPICE netlist design (when running the read design-spice command).

Parameters

-BULK Identifies nets connected to PMOS bulk terminals as powerand nets connected to NMOS bulk terminals as ground. Thisis the default.

-NOBULK By default, Conformal Custom identifies nets connected toPMOS bulk terminals as power and nets connected to NMOSbulk terminals as ground. However, this option removes thatassumption and you will need to specify power and groundpins/nets by using *.GLOBAL <name>:P for power nets and*.GLOBAL <name>:G for ground nets or use Conformalcommands to add constraints, tied signals (pins), or netattributes.

-BBOX Specifies that SUBCKT contains no transistors and will betreated as a blackbox. This is the default.

-NOBBox Specifies that SUBCKT contains no transistors and will beremoved along with all of its instantiations.

-NOADDGLOBALPINs Specifies that no extra ports for GLOBAL signals will be createdfor SUBCKT. This is the default.

-ADDGLOBALPINs Specifies that extra ports for GLOBAL signals will be created forSUBCKT.

-NOKEep_InstanceX Specifies that the first character ’X’ of the name of instance willnot be retained. This is the default.

-KEep_InstanceX Specifies that the first character ’X’ of the name of instance willnot be retained.



Examples

Sample Dofile:

set spice option -nobulk -nobbox -addglobalpins -keep_instanceX

read design -spice library.spi -golden

abstract logic

Related Commands

ABSTRACT LOGIC

READ DESIGN



SET STATETABLESET STATEtable

<ON | OFf>(Setup Mode)

Controls the global setting of the Synopsys Liberty state table support.

Note: This command must be used before READ DESIGN and READ LIBRARY.

Note: Using the READ DESIGN and READ LIBRARY command’s -STATEtable optionsupersedes these settings (it also supersedes the global setting).

Parameters

Related Commands

READ DESIGN -statetable

READ LIBRARY -statetable

ON Enables support for Synopsys Liberty state tables. This optionis the system default.

OFf Disables support for Synopsys Liberty state tables.



SET SYNTHESIS_OFF_COMMANDSET SYNTHESIS_OFF_Command


Specifies the pragma that is used to indicate the beginning of non-synthesizable constructsin the source code or in the generated generic netlist.

Note: If you do not run the SET_ATTR INPUT_PRAGMA_KEYWORD command prior to runningthis command, the default is translate_off.

Note: If this command is run multiple times, only the last value is used.

Parameters

Examples

Sample Dofile:







Related Commands

SET_ATTR INPUT_PRAGMA_KEYWORD

SET SYNTHESIS_ON_COMMAND

string Specifies the action.

Default: translate_off synthesis_off



SET SYNTHESIS_ON_COMMANDSET SYNTHESIS_ON_Command


Specifies the pragma that is used to indicate the end of non synthesizeable constructs in thesource code or in the generated generic netlist.

Note: If you do not run the SET_ATTR INPUT_PRAGMA_KEYWORD command prior to runningthis command, the default is translate_on.

Note: If this command is run multiple times, only the last value is used.

Parameters

Examples

Sample Dofile:







Related Commands

SET_ATTR INPUT_PRAGMA_KEYWORD

SET SYNTHESIS_OFF_COMMAND

string Specifies the action.

Default: translate_on synthesis_on



SET SYSTEM MODESET SYstem Mode

<Setup | LEc [-Map | -Nomap] [-PRESERVE] | EXPlorer>(Setup / LEC / Explorer Mode)

Switches system modes between the Setup mode and the LEC mode.

■ Setup mode: While in this mode, you read in the design and set all of the necessaryconstraints and environment variables.

■ LEC mode: While in this mode, Conformal does the comparison and diagnosis.

■ Explorer mode: While in this mode, you can cross-link from a timing report to an RTLdesign or a gate-level design through a schematic viewer or source code browser.

Note: This mode requires the Conformal Explorer license.

When you exit the Setup mode, Conformal attempts to map all key points in the Golden andRevised designs. A summary is given for the mapped points in the Golden and Reviseddesigns. An additional summary is given if Conformal identifies any unmapped key points.

Use the REPORT ENVIRONMENT command to display the current system mode.

Parameters

Related Command

REPORT ENVIRONMENT

REPORT TESTCASE

Setup Switches the system mode to Setup.

LEc Switches the system mode to LEC.

-Map Maps key points when entering the LEC system mode. This isthe default.

-Nomap Does not map key points when entering the LEC system mode.

-PRESERVE Preserves the netlist modeling. You can use this option fornetlists created with the REPORT TESTCASE command only.

EXPlorer Switches the system mode to Conformal Explorer.



SET UDP PINSET UDp Pin

<udp_name> <pin_name <0 | 1> ...>[-Golden | -Revised | -Both](Setup Mode)

Sets the pin inputs of the user-defined primitive (UDP) to constant values, which arepropagated into the UDP. Some inactive entries will be removed.

The constant set to inputs simplifies the state table of the UDP, which will sometimes eliminatesome ambiguity in the UDP description.

Note: This must be used before running the READ DESIGN command.

Parameters

Example

In this example, pins in1 and in2 of the UDP named udp_1 are set to 0 and 1, respectively:

set udp pin udp_1 in1 0 in2 1

Related Commands

READ DESIGN

READ LIBRARY

udpname Specifies the name of the UDP.

pin_name <0 | 1> Specifies the name of the pin and its input value. Choose 0or 1.

-Golden Sets the UDP inputs in the Golden design. This is thedefault.

-Revised Sets the UDP inputs in the Revised design.

-Both Sets the UDP inputs in both the Golden and Reviseddesigns.



SET UNDEFINED CELLSET UNDEfined Cell

<Error | Black_box | Generic_BBox>[-AUTO_Assign | -NOAUTO_Assign][-ASCEND | -NOASCEND]>

[-Both | -Golden | -Revised](Setup Mode)

Specifies how Conformal handles undefined cells it encounters when reading in the Goldenand Revised designs. The system default is to give an error message if there are anyundefined cells.

Use the REPORT ENVIRONMENT command to display the settings for the undefined cellshandling for the Golden and Revised designs. Execute this command before READ LIBRARYand READ DESIGN.

Parameters

Error When reading the designs, undefined cells trigger an errormessage. This is the default.

Black_box When reading the designs, regards undefined cells asblackboxes. This option takes Verilog parameter values toconstruct the module name for the created blackbox module.

Generic_BBox When reading the designs, regards undefined cells asblackboxes. This option ignores Verilog parameter values anduses the object bit widths to construct the module name for thecreated blackbox module.

-AUTO_Assign Automatically determines and assign directions to all blackboxpins. This is the default.

Note: If Conformal cannot determine the direction of a pin as“input” or “output”, it assigns I/O direction.

-NOAUTO_Assign Assigns I/O direction to all blackbox pins.

Note: You must manually reassign all pin directions accordingto the design.

-ASCEND Arranges bits of bus pins in ascending order; that is, in1 (0 to 7).This is the default.

-NOASCEND Arranges bits of bus pins in descending order; that is, out1 (7down to 0).



Related Commands

ADD BLACK BOX


READ DESIGN

READ LIBRARY

REPORT ENVIRONMENT

-Both The specified handling for undefined cells applies in both theGolden and Revised designs. This is the default.

-Golden The specified handling for undefined cells applies in only theGolden design.

-Revised The specified handling for undefined cells applies in only theRevised design.



SET UNDEFINED PORTSET UNDEfined Port

<Error | Ignore>[-Both | -Golden | -Revised](Setup Mode)

Specifies how Conformal handles undefined ports it encounters when reading in the Goldenand Revised libraries and designs. The system default is to report an error message ifthere are any undefined ports referenced by the module instance.

Use the REPORT ENVIRONMENT command to display the settings for the undefined portshandling for the Golden and Revised designs. Execute this command before READ LIBRARYand READ DESIGN.

Parameters

Related Commands

READ DESIGN

READ LIBRARY

REPORT ENVIRONMENT

Error Displays an error message for undefined ports.

Ignore Ignores undefined ports.

-Both Applies the specified handling for undefined ports in both theGolden and Revised designs. This is the default.

-Golden Applies the specified handling for undefined ports to the Goldendesign.

-Revised Applies the specified handling for undefined ports to theRevised design.



SET UNDRIVEN SIGNALSET UNDRiven Signal

< Z | 0 | 1 | X >[-Both | -Golden | -Revised](Setup Mode)

Specifies globally how Conformal treats undriven signals in the Golden and Revised designs.The system default specifies that undriven signals are classified as high-impedance(always driven by Z) in the Golden and Revised designs.

Use the REPORT ENVIRONMENT command to display the settings for the undriven signals forboth the Golden and Revised designs. Execute this command before READ LIBRARY andREAD DESIGN.

Parameters

Related Command

REPORT ENVIRONMENT

Z Specifies undriven signals as high impedance (always driven byZ). This option is the system default.

0 Specifies undriven signals as Logic 0.

1 Specifies undriven signals as Logic 1.

X Specifies undriven signals as unknown (X).

-Both Applies the state of the undriven signal to both the Golden andRevised designs. This is the default.

-Golden Applies the state of the undriven signal to the Golden design.

-Revised Applies the state of the undriven signal to the Revised design.



SET WIRE RESOLUTIONSET WIre Resolution

<And | Or | Wire>[-Both | -Golden | -Revised](Setup Mode)

Specifies how Conformal treats the output behavior of multi-driven nets. The system defaultfor both the Golden and Revised designs specifies that multi-driven nets are treatedas a wire-AND behavior.

When you use the wire option and Conformal encounters a multi-driven net (that is, buscontention) in a design, Conformal models this multi-driven net as TIE-X.

Note: This TIE-X is a pseudo input, not a “don’t care”.

Use the REPORT ENVIRONMENT command to display the settings of the wire resolution forthe Golden and Revised designs.

Parameters

Related Command

REPORT ENVIRONMENT

And Assigns a wire-AND behavior to multi-driven nets. This optionis the system default.

Or Assigns a wire-OR behavior to multi-driven nets.

Wire Assigns a TIEX behavior to multi-driven nets.

-Both Applies the specified behavior of multi-driven nets to both theGolden and Revised designs. This is the default.

-Golden Applies the specified behavior of multi-driven nets to theGolden design.

-Revised Applies the specified behavior of multi-driven nets to theRevised design.



SET X CONVERSIONSET X COnversion

<DC | E | 0 | 1>[-Both | -Golden | -Revised](Setup Mode)

Specifies how Conformal handles X assignments when modeling the design. It takes effectwhen changing from the Setup mode to the LEC mode.

The system defaults specify that X assignments are treated as “Don’t Cares” for the Goldenand “Error (E) Gates” for the Revised design. If the X assignment space of the Reviseddesign is within the X assignment space of the Golden design, then the E gate is marked asan extra unmapped point (redundant gate) after comparison.

Tip

The Revised X Handling feature enhances RTL-to-RTL comparisons. It ensures thatthe Revised Xs are in the Golden Don't Care space. To turn off this feature, useset x conversion dc -revised. This feature has been available since version4.3.

However, use this option only if you are certain that the X assignment space of theRevised design is within the X assignment space of the Golden design; otherwise,potential errors might be masked.

Use the REPORT ENVIRONMENT command to display the settings of the X assignment for theGolden and Revised designs.

Parameters

DC Assigns “Don’t Care” handling to X.

E Assigns “Error Gate” handling to X. E is a pseudo input.

0 Assigns Zero logic handling to X: 1’b0.

1 Assigns One logic handling to X: 1’b1.

-Both Applies the specified behavior of X assignments to both theGolden and Revised designs. This is the default.

-Golden Applies the specified behavior of X assignments to the Goldendesign.



Related Command

REPORT ENVIRONMENT

-Revised Applies the specified behavior of X assignments to the Reviseddesign.



SET XCSET XC

(Setup Mode)


Analyzes switch and primitive drive strength to achieve the most accurate logic functionresult. This technique can be applied to complex custom macros such as RAM and ROM andis essential to accurate verification of circuits with complex layer switch nets.



SETENVSETENV

<variable> <value>(Setup / LEC Mode)

Assigns a value to an environment variable name.

Parameters

Examplessetenv LM_LICENSE_FILE 5280@host

where host is the license server host name.

Related Command

PRINTENV

variable Adds the specified variable to the environment.

value Assigns the specified value to the variable.



SUBSTITUTE BLACKBOX MODELSSUBStitute BLackbox Models

[-Golden | -Revised][-NO_RENAME_RULE](Setup Mode)

Replaces all blackboxed modules in the design space with modules in the library space.

Use this command after running the READ DESIGN and READ LIBRARY commands.

Parameters

Related Command

ADD BLACK BOX

-Golden Applies to all blackboxed modules in the Golden design. This isthe default.

-Revised Applies to all blackboxed modules in the Revised design.

-NO_RENAME_RULE Does not use renaming rules for matching pin and modulenames.



SUBSTITUTE BLACKBOX WRAPPERSUBStitute BLackbox Wrapper

<pattern_list>(Setup Mode)

Searches for each blackbox instance in your design whose module name matches those in aspecified pattern list, and replaces them with new, fully-defined modules. Use this module inconjunction with the WRITE BLACKBOX WRAPPER command.

Parameters

Example

The following is a set of sample commands that show this and related commands in context.

Sample module:

<<< gol.v>>>module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst,cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout;

DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs),.wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );

1. Specify that Conformal treat undefined cells as blackboxes.

> set undefined cell black_box

2. Read in the Golden design, which contains our sample module.

> read design gol.v

3. Write a wrapper file dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox moduleDW_ram_r_w_s_dff_5_8_0.

write blackbox wrapper DW* -directory dir

break

Note: This command also generates synthesis script template files dir/dc.tcl anddir/rc.tcl.

pattern_list Searches for blackbox instances whose module name matchesthe specified pattern(s).

This option accepts the “*” wildcard.



4. Use the dir/dc.tcl script with your own synthesis tool to generatedir/_DW_ram_r_w_s_dff_5_8_0.g.v.

5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v file into the design.

> read design -append dir/*.g.v

6. Substitute the old module of blackbox instance ram with the new module_DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w_s_dff_5_8_0.g.v:229).

> substitute blackbox wrapper DW*

Related Command

WRITE BLACKBOX WRAPPER



SYSTEMSYSTEM

<string_command>(Setup / LEC Mode)

Enables any command your UNIX operating system recognizes.

Note: In GUI mode, the Conformal software prints the return in the transcript window.

You can substitute the exclamation mark (!) for the word “System”, as shown in the “Example”section, below.

Parameters

Examplesystem ls

system pwd

!pwd

string_command Any valid UNIX command.



TCLMODETCLMODE

(Setup / LEC Mode)

Switches from native Conformal command entry mode (VPX mode) to Tcl command entrymode. VPX mode is the default command mode.

There are two types of Tcl mode commands:

■ Native Tcl commands

■ Conformal Tcl commands

Note: When issuing commands in Tcl mode mode, you must type them in lowercase.

For more information about native Tcl commands, refer to the public Tcl manual, which iswidely available online. Conformal Tcl commands are discussed in detail in the EncounterConformal Equivalence Checking User Guide.

Tip

To start the Conformal software in Tcl mode without executing any initializationscript, run the following command at a UNIX system prompt:

UNIX% lec -tclmode

Tip

In the Tcl command entry mode, you can save report data to a file using theredirection command. For example, the following command saves the gate reportdata to a file named gate.out:

TCL_SETUP> report_gate -type dff > gate.out

Related Command

VPXMODE



TEST RENAMING RULETESt REnaming Rule

<-Design [-NOprint | -Print <Single | Pair | Group>]|<string>|-GATE_id <gate_id>>

[-All | -NEw_rule <string> <string>][-MAp [-TYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>…|-NOTYpe < PI | E | Z | DFf | DLat | CUt | BBox | PO>…]|-MOdule |-PIn [-BBox <module_name>]]

[-RULE_USAGE | -NORULE_USAGE][-Both | -Golden | -Revised][-SORTNAme][-File <filename> [-REPlace]][-VErbose](LEC Mode)

Displays the results of the key point matching based on the user-specified renaming rules.Use this command to obtain a quick summary of how well the key points will be mappedbased on the specified renaming rules. Test new and existing rules.

Parameters

-Design Tests the renaming rules on the entire design. This argumentinstructs Conformal to display a summary of the Golden andRevised pairs and groups and Golden and Revised singleun-grouped key points for the entire design.

-NOprint Does not display the key point pairs, un-grouped single keypoints, or grouped key points. This is the default.

-Print Displays key points as follows:

Single Un-grouped single key points

Pair Key point pairs

Group Grouped key points

string A string that the renaming rule uses as an example.

-GATE_id gate_id Tests renaming rules on the specified gate.

-All Tests all renaming rules. This is the default.


-NEw_rule string string



A new renaming rule:

The first string is the pattern to be matched; the second string isthe substitution pattern.

-MAp Tests the renaming rules on key points that will be mapped.This is the default.

-TYpe Tests renaming rules for all key points of the specified type.This is the default.

The available types are as follows:

PI Primary Inputs

E TIE-E gates

Z TIE-Z gates

DFF D flip-flops

DLAT D-latches


BBOX Blackboxes

PO Primary Outputs

-NOTYpe Tests renaming rules for all key points except the specifiedtypes. The available types are as follows:

PI Primary Inputs

E TIE-E gates

Z TIE-Z gates

DFF D flip-flops

DLAT D-latches


BBOX Blackboxes

PO Primary Outputs

-MOdule Tests the renaming rules on the modules in the design.

-PIn Tests the renaming rules on pin names of blackboxes.



Examples

■ The following command displays the summary results of the renaming rules on thedesigns:

test renaming rule -design -all

■ The following command displays a list of all Golden/Revised un-grouped single keypoints:

test renaming rule -design -print single

■ The following command displays a list of all Golden/Revised grouped key points:

test renaming rule -design -print group

■ The following command displays a list of all Golden/Revised pair key points:

test renaming rule -design -print pair

■ The following command writes a list of all Golden/Revised grouped key points to a file:

test renaming rule -design -print group -file group_list

■ The following command displays the summary results of the renaming rule on thedesigns with a new rule:

test renaming rule -design -new_rule <string> <string>

-RULE_USAGE Displays the number of matches for the specified string. Thisoption is turned on by default.

-NORULE_USAGE Does not display the number of matches for the specifiedrenaming rule.

-BBox module_name Tests the pin renaming rule on the specified blackbox module.The default is to test all blackboxes.

-Both Tests the renaming rules on both the Golden and Reviseddesigns. This is the default.

-Golden Tests the renaming rules on the Golden design.

-Revised Tests the renaming rules on the Revised design.

-SORTNAme When this option is used with the -print option, the resultsappear in alphabetical order by name.

-File filename Writes the results to the specified file.

-REPlace Replaces the above file, if it exists.

-VErbose Displays both the original key point name and the renamed keypoint.



■ The following command displays the summary results of the renaming rules applied to asample string:

test renaming rule <string> -all

■ The following command displays the summary results of the new renaming rule appliedto a sample string:

test renaming rule <string> -new_rule <string> <string>

Related Commands

ADD RENAMING RULE


MAP KEY POINTS


SET NAMING RULE



UNIQUIFYUNIQuify

<module_name… | -ALL [-Library | -NOLibrary]>[-Force][-USE_RENaming_rules][-Summary | -Verbose][-Golden | -Revised](Setup Mode)

Makes the specified module, which has multiple instances, unique. This command lets youremedy the “incompatible” instantiations warnings during hierarchical script generation. IfConformal does not make the modules unique, they are not included in the hierarchical dofile.

When using hierarchical compare for abort resolution, this command allows you to includemore modules in the hierarchical dofile, therfore reducing the compare complexity of helpingresolve aborts.

For more information, see Hierarchical Comparison for Abort Resolution in the EncounterConformal Equivalence Checking User Guide.

Parameters

module_name… Makes the specified module(s) unique.

-ALL Makes all modules in the specified design unique.


-Library Makes all modules in designs and libraries unique. This is thedefault.

-NOLibrary Makes all modules in designs unique.

-Force Forcibly makes specified modules in the Golden or Reviseddesign unique, even if those modules have not been madeunique in the complementing design. (For example, forciblymake Golden modules unique when the Revised modules havenot been made unique.)

-USE_RENaming_rules Considers renaming rules for instances.

When adding renaming rules, the software renames the Goldendesign instances to be same as in the Revised design, sorunning a subsequent UNIQUIFY command with this option willmake the Golden modules that have matching instance namesin the Revised design unique.



Example

The following command example creates a hierarchical dofile script named hier.docontaining the compare script for the sub-modules and the root module, then runshierarchical compare. This is can help in resolving aborts.

...

uniquify -all

write hier_compare dofile hier.do

run hier_compare hier do

Related Commands

RESOLVE

RUN HIER_COMPARE


-Summary Summarizes the outcome of making modules unique. This isthe default.

-Verbose Provides expanded information about the modules that weremade unique.

-Golden The specified modules are in the Golden design. This is thedefault.

-Revised The specified modules are in the Revised design.



USAGEUSAge

[-Elapse | -Delta ](Setup / LEC Mode)

Displays the total CPU run time and peak memory use since you started Conformal.

Parameters

Related Command

COMPARE

-Elapse Displays the elapsed time of a process.

-Delta Displays the difference, in seconds, between the current CPUrun time and CPU run time when you last issued the usagecommand.



VALIDATE CIRCUITVALidate CIrcuit

[-Revised | -Golden][-BBOXSCRipt <filename>][-MODule <module name>][-DOfile <filename>…][-POWERPINs <name 0> <name 1>… <name N>][-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs][-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput][-ASM | -NOASM](Setup Mode)


Checks circuit libraries and custom blocks (when applicable), and enables equivalencechecking on the full integrated circuit design. Use this command at the integrated-circuit levelfor RTL or Gate to final circuit. This application is for checking the consistency of pre-definedlibraries during design verification.

Important

Do not use this command for validating the library itself. To validate library itself, usethe VALIDATE LIBRARY command instead.

For both the Golden and Revised designs, refer to the same library so that anyinconsistencies at the library cell level will not affect the equivalence checking on design level.After which, all the library cells under this checking will be replaced by their counterpartreference cells.

Note: Conformal Ultra users can use this to check a verified circuit. However, you need aConformal Custom license to diagnose logic abstraction and errors that relate to librarycomparisons.

Parameters

-Revised Validates the Revised database. This is the default.

-Golden Validates the Golden database.

-BBOXSCRipt <filename>

Creates a dofile with the specified name that blackboxes allvalidated cells for structural verification, which is moreaccurate than logical verification.



-MODule <module name>

Validates the specified module.

By default, Conformal Ultra validates the root module. Usethis option to validate a module other than the root module.

Note: Conformal Ultra validates only the topmost library andcustom cells (that exist in the reference side) that are used bythe specified module.

-DOfile <filename>…

Specifies the name of the dofile that was used to verify allcustom blocks so that they can be re-checked.

If a custom module has not been verified yet, blackbox itbefore running the VALIDATE CIRCUIT command.VALIDATE CIRCUIT can check for consistency in customblocks, but it cannot verify custom blocks. Use ConformalCustom to verify custom blocks.

-POWERPINs <name 0> <name 1> ... <name N>

Defines names for the pin(s) that are used as extraneouspower pins, which are ignored during cell verification. Formultiple power pins, each pin name must be separated by aspace.

Cadence recommends that you use the ADD PINCONSTRAINT command to tie power pins to 1 and groundpins to 0.

-PRESERVE_MODEL_OPTIONs



Preserves any user-defined settings made prior to thiscommand. This is the default.

This option disables any flattening options that VALIDATECIRCUIT sets by default.

By default, the following flatten model options are set whenVALIDATE CIRCUIT compares two modules:

-seq_redundant-latch_fold-all_inv_seq_merge-all_seq_merge-seq_const

See the SET FLATTEN MODEL command for an explanationof these options.

With -PRESERVE_MODEL_OPTIONs, the comparison is donewithout changing any flatten model options. Any options thatwere set prior to running validate circuit are used instead.

-NO_PRESERVE_MODEL_OPTIONs

Does not disable any flattening options that VALIDATECIRCUIT sets by default.

-POWERPIN_TO_INput

Specifies that if there are power pins that are input/outputpins, they will be changed to input pins before validation. Thisis the default.

-NO_POWERPIN_TO_INput

Specifies that power pins that are input/output pins will NOTbe changed to input pins before validation.

-ASM Enables the Advanced State-element Modeling (ASM)algorithm. This helps to analyze loop structure to producebetter modeling of state elements, such as D-Latch, DFF, andbus-keeping I/O logic. This is the default.



Related Commands

READ DESIGN

READ LIBRARY

SET FLATTEN MODEL


Tip




VALIDATE LIBRARYVALidate LIbrary

[-Revised | -Golden][-NOSPIce | -SPIce][-NOGOLPINDir | -GOLPINDir][-PRESERVE_MODEL_OPTIONs | -NO_PRESERVE_MODEL_OPTIONs][-POWERPINs <name 0> <name 1>… <name N>][-POWERPIN_TO_INput | -NO_POWERPIN_TO_INput][-ASM | -NOASM](Setup Mode)

Note: This is a Conformal Ultra and Conformal Custom command.

Compares all top-level cells with matching names. Conformal abstracts the modules on theSPICE side before comparison. This application is for library verification during library design.

Important

To abstract SPICE modules, you must have a Conformal Custom license.

Parameters

-Revised Validates the Revised database. This is the default.

-Golden Validates the Golden database.

-NOSPIce Abstracts and validates the modules that are not SPICE. Thisis the default.

Note: This option requires a Custom license.

-SPIce Abstracts and validates the SPICE modules.

Note: This option requires a Custom license.

-NOGOLPINDir Does not copy the pin directions from the Golden design to theRevised design. This is the default.

-GOLPINDir Copies the pin directions from the Golden design to the Reviseddesign. This is for all pins within the library cells being validated.



-PRESERVE_MODEL_OPTIONs

Preserves any user-defined settings made prior to thiscommand. This is the default.

This option disables any flattening options that VALIDATELIBRARY sets by default.

-NO_PRESERVE_MODEL_OPTIONs

Does not disable any flattening options that VALIDATELIBRARY sets by default.

-POWERPINs <name 0> <name 1> ... <name N>

Defines names for the pin(s) that are used as extraneous powerpins, which are ignored during cell verification. For multiplepower pins, each pin name must be separated by a space.

Cadence recommends that you use the ADD PINCONSTRAINT command to tie power pins to 1 and ground pinsto 0.

-POWERPIN_TO_INput Specifies that if there are power pins that are input/output pins,they will be changed to input pins before validation. This is thedefault.

-NO_POWERPIN_TO_INput

Specifies that power pins that are input/output pins will NOT bechanged to input pins before validation.

-ASM Enables the Advanced State-element Modeling (ASM)algorithm. This helps to analyze loop structure to produce bettermodeling of state elements, such as D-Latch, DFF, andbus-keeping I/O logic. This is the default.


Tip




Related Command

VALIDATE CIRCUIT



VERSIONVERsion

(Setup / LEC Mode)

Displays the current version release number of Conformal. You can use this command afterthe SET LOG FILE command so the version becomes a part of the transcript log. In this way,you record the Conformal version that created your results. This command is also helpfulwhen you use the SAVE SESSION and RESTORE SESSION commands, because you mustuse the same Conformal version when you restore a session.

Related Commands

RESTORE SESSION

SAVE SESSION

SET LOG FILE



VPXMODEVPXMODE

(Setup / LEC Mode)

Switches from Tcl mode to native Conformal command entry mode (VPX mode). VPX is thedefault command mode.

Important

When issuing this command in the Tcl command interpreter, you must type this inlowercase. For example:

TCL_LEC> vpxmode

Tip

In VPX mode, you can save report data to a file using the redirection command. Forexample, the following command saves the gate report data to a file namedgate.out:

SETUP> report gate -type dff > gate.out

Related Command

TCLMODE



WRITE BLACKBOX WRAPPERWRIte BLackbox Wrapper

-DIRectory <dirname> <pattern_list>(Setup Mode)

Creates a wrapper for each blackbox instance in your design whose module name matchesthose in a specified pattern list. Use this command to help complete equivalency checking fordesigns that contain DesignWare or ChipWare blackboxed modules.

This command produces a module instantiation wrapper file for each blackboxed modulewrapper, and synthesis script templates that you can use with your own synthesis tool tosynthesize the modules that Conformal blackboxed.

Synthesize the wrapper modules using the outputted scripts. Then, read in thenewly-synthesized files using the READ DESIGN -append command. Finally, use theSUBSTITUTE BLACKBOX WRAPPER command to substitute the old blackboxed modules withthe newly synthesized modules.

Note: When specifying the cells that Conformal will treat as blackboxes, use the setundefined cell black_box command instead of the add notranslate modulescommand.

Parameters

Examples

The following is a set of sample commands that show this and related commands in context.

Sample module:

<<< gol.v>>>module design(clk, rst, cs, wr, rd_addr, wr_addr, din, dout); input clk, rst,cs, wr; input [2:0] rd_addr, wr_addr; input [4:0] din; output[4:0] dout;

DW_ram_r_w_s_dff #(5, 8, 0) ram (.clk(clk), .rst_n(rst), .cs_n(cs),.wr_n(wr), .rd_addr(rd_addr), .wr_addr(wr_addr), .data_out(dout), .data_in(din) );

-DIRectory <dirname> Writes out the module instantiation wrapper file and thescripts to this directory.

pattern_list Writes out module wrappers for blackbox instanceswhose module name matches the specified pattern(s).

This option accepts the “*” wildcard.



1. Specify that Conformal treat undefined cells as blackboxes.

> set undefined cell black_box

2. Read in the Golden design, which contains our sample module.

> read design gol.v

3. Write a wrapper file dir/_DW_ram_r_w_s_dff_5_8_0.v for blackbox moduleDW_ram_r_w_s_dff_5_8_0.

write blackbox wrapper DW* -directory dir

break

Note: This command also generates synthesis script template files dir/dc.tcl anddir/rc.tcl.

4. Use the dir/dc.tcl script with your own synthesis tool to generatedir/_DW_ram_r_w_s_dff_5_8_0.g.v.

5. Read the newly created dir/_DW_ram_r_w_s_dff_5_8_0.g.v file into the design.

> read design -append dir/*.g.v

6. Substitute the old module of blackbox instance ram with the new module_DW_ram_r_w_s_dff_5_8_0_DW_ram_r_w_s_dff_5_8_0_0(dir/_DW_ram_r_w_s_dff_5_8_0.g.v:229).

> substitute blackbox wrapper DW*

Related Command

SUBSTITUTE BLACKBOX WRAPPER



WRITE COMPARED POINTSWRIte COmpared Points

[-CLass <All | Eq | INVequivalent | NONeq | ABort | NOTcompared>][-TYpe <All | PO | DFf | DLat | Bbox | Cut>][-File <filename>][-Replace](LEC Mode)

Writes compared points information to a file. You can use this file to add a specific class andtype of compared points to a compare list.

Parameters

-CLass Writes out the class of compared points. By default, thecommand writes out all classes.

All Writes all compared point classes. This isthe default if you do not specify the -CLassoption.

Eq Writes compared points that are equivalent.

INVequivalent

Writes the compared points that are invertedequivalent.

NONeq Writes the compared points that arenon-equivalent.

ABort Writes the aborted compared points.

NOTcompared Writes the compared points that are notcompared.

-TYpe Writes out the type of compared points. By default, thecommand writes out all types.

All Writes all compared point types. This is thedefault if you do not specify the -TYpeoption.

PO Writes the compared points of the primaryoutputs.

DFf Writes the compared points of the Dflip-flops.



Related Commands

ADD COMPARED POINTS

DLat Writes the compared points of the D-latches.

Bbox Writes the compared points of theblackboxes.

Cut Writes the compared points for artificialgates that break combinational loops.

-File <filename> Specifies the filename.

-Replace Replaces the existing file.



WRITE DESIGNWRIte DEsign

<filename>[ | -ALL | -BBOX][-Used][-Library][-REPlace][-RTL][-TEST_VIEW][-Golden | -REVised](Setup / LEC Mode)

Writes out the Golden or Revised design in Verilog format to examine how Conformalabstracts RTL descriptions into gate-level descriptions.


Parameters

filename Writes the design to this file.

-ALL Writes out all modules that are stored in the design space.

-BBOX Writes out all of the empty module descriptions of blackboxes inthe design.

By default, the command writes out the design tree of the rootmodule, excluding modules in the library space.

-Used Writes out the specified modules and all the referencedmodules, including modules in the design space.

-Library Writes out the library information.


-RTL Outputs word-level operator expressions such as *, +, and -.By default, the command writes out the design without using theword-level operators. Without this option, the command writesout the design in Verilog primitive gates.



Related Command

READ DESIGN

-TEST_VIEW Writes out the abstraction result of ABSTRACT LOGIC-test_view.

The result might include Encounter Test primitives. To read thenetlist back, use the READ DESIGN command’s -defineoption for ET_EC_MODEL. For example:

read design <netlist> -define ET_EC_MODEL

-Golden Writes out the Golden design only. This is the default.

-REVised Writes out the Revised design only.



WRITE ECO DESIGNWRIte ECo Design

[-OVERWrite | -NEWFILE [filename_fmt] | -REVIEWonly][-BACKup [filename_fmt]][-REPORT [filename]][-REPlace](Setup Mode)

Writes out the ECO netlist and attempts to reduce the number of text differences between theoriginal netlist file and the ECO netlist file. This will reduce the number of differences reportedby the UNIX diff command between the two files.

Limitations

■ Does not work with VHDL netlists.

■ Does not work if you flatten the design during the ECO process.

Parameters

-OVERWrite Overwrites the original files. This is the default.

-NEWFILE [filename_fmt]

Writes the design into new files. The default format for the newfiles is %s.eco, where %s is the original filename.

-REVIEWonly Reviews the changes only and does not write out the design

-BACKup [filename_fmt]

Creates a back up original files if using the -OVERWriteoption. The default format for the backup files is %s.bak,where %s is the original file name.

-REPORT [filename]

Generates a report showing the differences between theoriginal design and the ECO design. If the filename is notprovided, the report will print to the screen.

-REPlace Replaces the file if it already exists when using the -NEWFILEand -REPORT options.



Example

The following is a sample script that writes out the a.v.eco and b.v.eco files after runningthe Conformal ECO commands:

read design a.v b.v -golden

// ECO process

analyze eco ...

optimize patch ...

write eco design -newfile -replace

Related Commands

REPORT ECO CHANGES



WRITE HIER_COMPARE DOFILEWRIte HIer_compare Dofile

<filename>[-MODULE <golden_module> <revised_module>[-HIERarchical | -FLATten]][-Black_box | -NOBlack_box][-CONDitional][-Exact_pin_match | -NOExact_pin_match][-NOConstraint

| -Constraint [-EXTRACT_Clock] [-INPUT_OUTPUT_Pin_equivalence][-RUN_HIER_compare]

][-PREPEND_String <string>][-APPEND_String <string>][-COMPARE_String <string>][-CONDitional][-Threshold <integer>][-LEVEL <integer>][-All][-Usage][-Replace][-RETIMED_modules][-IGNORE_MISMATCH_ports][-VERBOSE](Setup Mode)

Writes out a hierarchical dofile script that verifies the two hierarchical designs starting fromthe lower-level modules and progressing to the top root module. Use options to specify oneof the following actions:

■ Blackbox modules after comparison

■ Write modules with different numbers of pins to the dofile script

■ Propagate the constraints to lower-level modules and apply them to the dofile script

■ Change the minimum number of module primitives considered for hierarchicalcomparison


This command also generates a dofile script to compare two libraries, such as a Liberty andVerilog library. Use the -all option to write all library models to the dofile script forcomparison.

Note: Hierarchical comparison is also useful in resolving aborts. See the UNIQUIFYcommand for more information.



Parameters

<filename> Specifies the name of the dofile script that verifies designhierarchy.

-MODULE <golden_module> <revised_module>

Writes the specified Golden module and Revised module to thehierarchical dofile script.

-HIERarchical Includes all of the submodules of the specified module in thehierarchical dofile script. This is the default.

-FLATten Flattens all of the submodules of the specified module.

-Black_box Blackboxes each module after comparison. This is thedefault.

-NOBlack_box Does not blackbox each module after comparison.

-CONDitional Automatically merges the module to the next level in thehierarchy if the comparison at the current level wasunsuccessful.

-Exact_pin_match Writes only those modules with matching pin names to thehierarchical dofile script. This is the default.

-NOExact_pin_match Writes all modules to the hierarchical dofile script.

-NOConstraint Does not apply the root module constraints and equivalences tothe hierarchical dofile script. This is the default.

-Constraint Propagates root module constraints and equivalences andapplies them to the hierarchical dofile script.

-EXTRACT_Clock Extracts the clock pins in the Golden and Revised designs, andautomatically adds the renaming rules to hierarchical dofilescript to map the clock ports in the two designs. This can beused when the design has undergone Clock-Tree-Synthesis(CTS).

-INPUT_OUTPUT_Pin_equivalence

Extracts input-output pin equivalences within a module andapplies them to hierarchical dofile script. This can be usedwhen the design has feedthroughs or feedback buffers.



-RUN_HIER_compare Writes out more modules in the hierarchical dofile script byperforming less stringent constraint checking.

The resulting dofile must only be processed by the RUNHIER_COMPARE command and its default options.

-PREPEND_String <string>

Appends any string of commands to the hierarchical dofilescript before key point comparison for each module.

Use “;” to separate commands.

Use double quotes to surround each prepended command (see“Examples”).

-APPEND_String <string>

Appends any string of commands to the hierarchical dofilescript after key point comparison for each module.

Use the semi-colon character (;) to separate commands. Usedouble quotes to surround each appended command (seeExamples).

-COMPARE_String <string>

Replaces the default compare command with a string ofcompare commands in the hierarchical dofile script generationfor each module.

Use the semi-colon character (;) to separate commands. Usedouble quotes to surround each compare command (seeExamples).

-CONDitional Skips blackboxing for nonequivalent submodules during thehierarchical comparison. (The end result is that Conformalflattens these submodules.)

To report the flattened modules, use the reporthier_compare result -flattened command.

-Threshold integer This threshold is the minimum number of primitives within amodule that will be written to the hierarchical dofile script. Theminimum default number is 50 primitives.

-LEVEL integer Writes all modules to the hierarchical dofile script up to thespecified hierarchical level.



Exampleswrite hier_compare dofile hier.do -replace

write hier_compare dofile lec.do -replace

write hier_compare dofile hier.do -append_string “usage” -prepend_string “reportunmapped points -notmapped” -replace

■ The following is a sample dofile that reads in the two hierarchical designs, writes out thehierarchical dofile script, and compares design hierarchies:

read library golden.lib -verilog -golden

read design golden.v -verilog -golden

read library revised.lib -verilog -revised

read design revised.v -verilog -revised

write hier_compare dofile hier.do -replace

set log file hier.log -replace

dofile hier.do

exit -force

■ The following is a sample dofile that reads in a synthesis library and simulation library,writes out all of the library models, and compares library hierarchies:

read design syn.lib -liberty -golden

read design simulation.v -verilog -revised

write hier_compare dofile lib_ver.do -replace -all

-All Writes “all” library modules to the hierarchical dofile script.

“All” applies within the given defaults. Use this option for libraryverification.

-Usage Executes the USAGE command after each comparison and atthe end of the hierarchical comparison.


-RETIMED_modules Writes out only those modules which have thePIPELINE_RETIME attribute attached to them.

Use the ADD MODULE ATTRIBUTE command to attach thePIPELINE_RETIME attribute to a module.

-IGNORE_MISMATCH_ports

Forces all modules with mismatched ports to be written out in ahierarchical dofile.

-VERBOSE Provides additional information when writing out thehierarchical dofile script.



set log file lib_ver.log -replace

dofile lib_ver.do

exit -force

■ In the following command, the default compare command is replaced with twocommands during each module comparison, set compare effort low andcompare -abort_stop 1 -noneq_stop 1:

write hier_compare dofile -compare_string \“set compare effort low; compare -abort_stop 1 -noneq_stop 1”

■ The following command example creates a hierarchical dofile script named hier.docontaining the compare script for the sub-modules and the root module, then runshierarchical compare. This is can help in resolving aborts.

...

uniquify -all

write hier_compare dofile hier.do

run hier_compare hier do

Related Commands

ADD NOBLACK BOX

DELETE NOBLACK BOX

READ DESIGN

READ LIBRARY


REPORT NOBLACK BOX


RUN HIER_COMPARE


SET NAMING RULE

UNIQUIFY



WRITE LIBRARYWRIte LIbrary

<filename>[-Verilog][-REPlace][-Golden | -REVised](Setup / LEC Mode)

Writes out the Golden or Revised library to a Verilog file. The default is to write out thelibrary as functional Verilog model descriptions.

Use this command to examine how Conformal abstracts complex UDP library models.


Parameters

Related Command

READ LIBRARY

filename Specifies the library filename.

-Verilog Writes out the library in Verilog format. This is the default.


-Golden Writes out only the Golden library. This is the default.

-REVised Writes out only the Revised library.



WRITE MAPPED POINTSWRIte MApped Points

<filename>[-CLass < Full | System | User>[-TYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>…][-NOTYpe <PI | E | Z | DFf | DLat | CUt | BBox | PO>…][-REPlace](LEC Mode)

Writes the mapped point information to a file. If the comparison needs to be done at a latertime, you can use this command to accelerate the mapping process.

Use the READ MAPPED POINTS command to read the file.

Use the tilde character (~) to shorten the file’s path.

Parameters

filename Specifies the filename.

-CLass Writes out the System, User, or Full classes of mapped points.

Full Both the User and System class. This isthe default.

System Key points that are mapped automatically.

User User class: key points that are manuallymapped with the ADD MAPPED POINTScommand.

-TYpe mapped_keypoint_type

Writes only the mapped key points of the specified type.Available types are as follows:

PI Primary input

E TIE-E

Z TIE-Z

DFf D flip-flop

DLat D-latch




Related Commands

READ MAPPED POINTS


BBox Blackbox

PO Primary output

-NOTYpe mapped_keypoint_type

Does not write the mapped key points of the specified type.Available types are as follows:

PI Primary input

E TIE-E

Z TIE-Z

DFf D flip-flop

DLat D-latch


BBox Blackbox

PO Primary output




WRITE MEMORY PRIMITIVEWRIte MEmory Primitive

<filename>[-Module <name*> | -All][-REPlace][-OPTionsdef <filename1>][-COMmondef <filename2>](LEC Mode)


Writes memory primitives to a file. Use this command to retrieve information for simulation.

For additional information about memory primitives, refer to the “Memory Primitive DataSheet” located at <install_dir>/doc/MEM_datasheet.pdf.


Note: The wildcard (*) represents any zero or more characters in module names.

Parameters

filename Specifies the filename.

-Module name* Writes only the memory primitives for the specified module.


-All Writes out memory primitives for all modules.


-OPTionsdef <filename1>

Writes parameter option definitions to a separate file. This willwrite the ‘define statements, which are options to availableparameters, from the memory primitives to a separate file.

-COMmondef <filename2>

Writes the common module called Vpx_wireOrlatOrff_datato a separate file. This module is common to all memoryprimitives.

You can write common memory primitive definitions to a separatefile during each call to WRITE MEMORY PRIMITIVE, or you canuse an existing file using the -rep option.



Related Command

READ DESIGN



WRITE PARTITION DOFILEWRIte PArtition Dofile

<filename>[-Map filename][-Usage][-Replace][-PREPEND_String <string>][-APPEND_String <string>][-COMPARE_String <string>](Setup / LEC Mode)

Writes out a partition dofile script based on the key point names specified with the ADDPARTITION KEY_POINT command. The number of compare iterations is based on whetherthe key point names have all-pattern, one-hot, or one-cold constraints.


Parameters

filename The partition dofile is written to this file.

-Map filename Uses the specified file for key point mapping. (You must use theWRITE MAPPED POINTS command before using this option.)

-Usage Executes the USAGE command after each comparison and atthe end of the partition dofile.


-PREPEND_String <string>

Appends any string of commands to the partition dofile scriptbefore key point comparison for each module.


Use double quotes to surround each prepended command (see“Examples” below).

-APPEND_String <string>

Appends any string of commands to the partition dofile scriptafter key point comparison for each module.


Use double quotes to surround each appended command (see“Examples” below).



Examplewrite partition dofile partition.do -replace

write partition dofile ptn.do -append_string “usage” -prepend_string “reportunmapped points -notmapped” -replace

In the following command, the default compare command is replaced with two commandsduring each module comparison, set compare effort low and compare-abort_stop 1 -noneq_stop 1:

write partition dofile -compare_string “set compare effort low; compare -abort_stop1 -noneq_stop 1”

Related Commands




WRITE MAPPED POINTS

-COMPARE_String string

Replaces the default compare command with a string ofcompare commands in the partition dofile script generation foreach module.


Use double quotes to surround each compare command (see“Examples”).



WRITE RULE CHECKWRIte RUle Check

<filename>[-DEsign | -LIbrary][-Golden | -REVIsed][-Replace](Setup Mode)

Writes the rule violations into a rule file. Use this command the first time you run a session.For later runs, exclude the violations already flagged with the read rule check -exclude<filename> command.


Parameters

Examples

In the following example, the second report rule check will not report any rules.

read design g.v -goldenread design r.v -revised

write rule check rule.g -golden -replacewrite rule check rule.r -revised -replace

read design g.v -golden -replaceread design r.v -revised -replace


filename Writes rule check violations to the specified file.

-DEsign Writes only design rule check violations. If you do not specify-design or -library, Conformal writes rule check violationsfrom both designs and libraries.

-LIbrary Writes only library rule check violations. If you do not specify-design or -library, Conformal writes rule check violationsfrom both designs and libraries.

-Golden Writes rule check violations from the Golden design. This isthe default.

-Revised Writes rule check violations from the Revised design.

-REPlace Replaces the previously saved file.



read rule check rule.g -exclude -goldenread rule check rule.r -exclude -revised


Related Command

READ RULE CHECK



3

HDL Rule Check Messages

This chapter is organized into sections by HDL rule categories. Each section lists all of therules and messages for the specified category. Each rule message is defined and followed bya sample case that can cause the message. The examples include a brief explanation thatdirect you to the pertinent lines of code, which appear in bold type.

The rule categories included in this chapter are listed below. Register Transfer Levelmessages are a super-set of rules that apply to both Verilog and VHDL. However, rulesincluded in the Verilog category apply to Verilog, only.

■ Directive on page 522

■ File on page 549

■ Hierarchy on page 551

■ Ignored on page 584

■ Register Transfer Level on page 603

■ SPICE Netlist Format on page 720

■ System Verilog on page 733

■ User-Defined Primitive on page 752

■ Verilog on page 764

Within each category, rules are grouped in sets according to their relationship to each other.For example, DIR1.1 and DIR1.2 both relate to pragmas. Likewise, IGN3.1 and IGN3.2 aregrouped because they both address how the checker handles duplications.


Encounter Conformal Equivalence Checking Reference ManualHDL Rule Check Messages

Directive

This category of rules applies to designs that include directives or pragmas. The followingtable lists the Directive (DIR) rule check numbers and messages.

Rule Number Message

DIR1.1 built_in pragma applied to function

DIR1.2 map_to_operator pragma applied to function

DIR1.3 return_port_name pragma applied to function

DIR2.1 full_case directive is detected

DIR2.2 parallel_case directive is detected

DIR3.1 synthesis/translate/compile on/off directive is detected

DIR3.2 dc_script_begin and dc_script_end directives is detected

DIR4.1 HDL directive/pragma is unsupported

DIR4.2 HDL directive/pragma is supported

DIR4.3 HDL directive/pragma is disabled

DIR4.4 HDL directive/pragma is ignored

DIR5.1 Conformal multi_port directive is detected

DIR5.2 Conformal multi_port directive is detected

DIR5.3 Conformal mem_rowselect directive is detected

DIR5.4 Conformal conformal cutpoint directive is supported

DIR6.1 Ignored compiler directive is detected

DIR6.2 Supported compiler directive is detected

DIR7.1 Unsupported synthesis attribute is detected

DIR7.2 Supported synthesis attribute is detected

DIR8.1 ‘protected/‘endprotected pragma is used

DIR9.1 Verilog ‘celldefine is for timing simulation. Use the LIBERTYlibrary instead

DIR9.2 Illegal to redefine a Verilog compiler directive as a macro

DIR9.3 Verilog compiler directive is redefined as a macro



DIR1.1

Message

built_in pragma applied to function

Default Severity

Warning

Description

The design applies the built_in pragma to a function. If the checker supports the specifiedpragma, it also displays the rule DIR4.2 message.

Example

In the following example, pragma built_in is inserted in function my_or. See line 4 (inbold).

ARCHITECTURE arch OF test ISFUNCTION my_or ( l, r : bit )RETURN bit IS-- pragma built_in SYN_ORBEGINRETURN '0';

END my_or;BEGINproc2 : PROCESSBEGINout0 <= my_or (in1,in2);

END PROCESS;END arch;



DIR1.2

Message

map_to_operator pragma applied to function

Default Severity

Warning

Description

The design applies the map_to_operator pragma to a function. If the checker supports thespecified pragma, it also displays the rule DIR4.2 message.

Example

In the following example, the map_to_operator pragma is inserted in function my_leq.See line 5 (in bold).

ARCHITECTURE arch OF test ISFUNCTION my_leq ( l, r : bit_vector(3 downto 0) )RETURN boolean IS-- pragma map_to_operator LEQ_TC_OPBEGINRETURN false;

END my_leq;BEGINproc2 : PROCESSBEGINout0 <= my_leq (in1,in2);

END PROCESS;END arch;



DIR1.3

Message

return_port_name pragma applied to function

Default Severity

Warning

Description

The design applies the return_port_name pragma to a function that contains this pragma.If the checker supports the specified pragma, it also displays the rule DIR4.2 message.

Example

In the following example, the return_port_name pragma on line 8 (in bold) is inserted infunction DWF_div_uns.

module test;parameter a_width = 16;parameter b_width = 16;

function [a_width-1 : 0] DWF_div_uns;// Function to compute the unsigned quotient

// pragma map_to_operator DIV_UNS_OP// pragma return_port_name QUOTIENT

input [a_width-1 : 0] A;input [b_width-1 : 0] B;

begin// pragma translate_off

return 0;// pragma translate_on

endendfunction

endmodule



DIR2.1

Message

full_case directive is detected

Default Severity

Warning

Description

The design includes a full_case directive in a case statement. If the checker supports thespecified directive, it also displays the rule DIR4.2 message.

Example

The following example uses the synopsys full_case directive in line 7 (in bold).

module test ( a, e, sel, out0);input a, e;input sel;output out0;reg out0;always @(sel or a or e) begincase(sel) // synopsys full_case1'b1 : out0 = a;default: out0 = e;

endcaseend

endmodule



DIR2.2

Message

parallel_case directive is detected

Default Severity

Warning

Description

The design includes a parallel_case directive used in a case statement. If the checkersupports the specified directive, it also displays the rule DIR4.2 message.

Example

The following example includes the synopsys parallel_case directive on line 7 (in bold).

module test ( a, e, sel, out0);input a, e;input sel;output out0;reg out0;always @(sel or a or e) begincase(sel) // synopsys parallel_case1'b1 : out0 = a;default: out0 = e;

endcaseend

endmodule



DIR3.1

Message

synthesis/translate/compile on/off directive is detected

Default Severity

Warning

Description

The design includes a directive belonging to one of the following classes:

■ synthesis on/off

■ translate on/off

■ compile on/off

If the checker supports this directive, it also displays the rule DIR4.2 message.

In the Conformal Equivalency Checker, you can also define your own directive to turnsynthesis on and off with the following commands:

■ SET_ATTR INPUT_PRAGMA_KEYWORD <string>

■ SET SYNTHESIS_OFF_COMMAND <string>

■ SET SYNTHESIS_ON_COMMAND <string>

Example

The following example includes the synopsys translate_off and synopsystranslate_on directives. See lines 5 and 7 (in bold).

module test ( clk, din, dout );input clk, din;output dout;reg dout;// synopsys translate_offreg [0:0] mem [1:0];// synopsys translate_onalways @(posedge clk)dout <= din;endmodule



DIR3.2

Message

dc_script_begin and dc_script_end directives is detected

Default Severity

Warning

Description

The design includes the dc_script_begin and dc_script_end directives. If the checkersupports the specified directives, it also displays the rule DIR4.2 message..

Example

In the following example, the design includes the dc_script_begin and dc_script_enddirectives. See lines 5 and 7 (in bold).

module test ( clk, din, dout );input clk, din;output dout;reg dout;// synopsys dc_script_begin// set_implementation wall MPYDW// synopsys dc_script_endalways @(posedge clk)dout <= din;endmodule



DIR4.1

Message

HDL directive/pragma is unsupported

Default Severity

Warning

Description

The design includes one or more HDL directives or pragmas that the checker does notsupport.

Example

In the following example, the checker does not support the synopsysnot_defined_or_not_supported directive. See line 6 (in bold).

module test ( clk, in0, out0 );input clk, in0;output out0;reg out0;always @( posedge clk )// synopsys not_defined_or_not_supportedout0 <= in0;

endmodule



DIR4.2

Message

HDL directive/pragma is supported

Default Severity

Warning

Description

The design includes one or more HDL directives or pragmas that the checker supports.

Example

In the following example, the checker supports the synopsys full_case directive. See line7 (in bold).

module test ( a, e, sel, out0);input a, e;input sel;output out0;reg out0;always @(sel or a or e) begincase(sel) // synopsys full_case1'b1 :out0 = a;

default:out0 = e;

endcaseend

endmodule



DIR4.3

Message

HDL directive/pragma is disabled

Default Severity

Warning

Description

The design includes one or more HDL directives or pragmas that were disabled by the user.The command used to disable a directive or pragma is:

set directive off <directive_name>

Example

In the following example, the design includes the conformal assertion_librarydirective on line 5 (in bold). However, we disabled it with the SET DIRECTIVE OFFcommand. (Shown below the test case.)

module test (a, b, q);input [3:0] a, b;output [3:0] q;reg [3:0] q;// conformal assertion_libraryalways @ (a or b ) beginq = a & b;

endendmodule

Input:

SETUP>set directive off assertion_library

SETUP>read design test.v -verilog



DIR4.4

Message

HDL directive/pragma is ignored

Default Severity

Warning

Description

The specified HDL directive or pragma is not supported and will be ignored.

Example

In the following example, if the dofile contains the following line:

set directive off translate_on translate_off unknown_pragma

The unknown_pragma is not a supported directive or pragma and will be ignored.



DIR5.1

Message

Conformal multi_port directive is detected

Default Severity

Warning

Description

The checker generates this message when the design includes the Conformal multi_portdirective. This directive specifies that the checker will model the specified register withmultiple clock ports, multiple data ports, and a single output port.

Note: If you do not include the multi_port directive, by default, the checker createsmultiple registers with outputs wired together.

Example

In the following example, the design includes the conformal multi_port directive in line5 (in bold).

module test ( clk1, clk2, in0, out0 );input clk1, clk2, in0;output out0;reg out0;// conformal multi_port “out0”always @( posedge clk1 )out0 <= 1'b0;

always @( posedge clk2 )out0 <= in0;

endmodule



DIR5.2

Message

Conformal multi_port directive is detected

Default Severity

Warning

Description

The checker generates this message when the design includes the Conformal clock_holddirective. This directive specifies that the checker will model the selected registers asgated-clock registers.

Example

In the following example, the design includes the conformal clock_hold directive on line5 (in bold).

module test ( clk, din, adr, out0 );input clk, din, adr;output out0;reg [0:0] mem [1:0];

// conformal clock_hold memalways @(posedge clk)begin

mem[adr] <= din;endassign out0 = mem[adr];

endmodule



DIR5.3

Message

Conformal mem_rowselect directive is detected

Default Severity

Warning

Description

The checker generates this message when the design includes the Conformalmem_rowselect directive. This directive specifies that the checker will model the followingtype of RTL into a structure that lets you define the signals that are synthesized as part of thedecoded word line of the ram_array, while all other signals on the sensitivity list aresynthesized into the logic cone of the input bit line.

always @(clk or we or din or addr)beginif (clk && we) ram_array(addr) = din;

end

Example

In the following example, the design includes the conformal mem_rowselect directive online 7 (in bold).

module test(clk, en, addr, din, dout);input clk, en;input [1:0] addr;input [0:0] din;output [0:0] dout;reg [0:0] ram [3:0];

// conformal mem_rowselect “ram clk en addr[1]”always @(clk or en or addr or din) begin

if (clk && en) ram[addr[1:0]] = din;endassign dout = ram[addr[1:0]];

endmodule



DIR5.4

Message

Conformal conformal cutpoint directive is supported

Default Severity

Warning

Description

The variable defined by the pragma is the cut point in the design.

Example

In the following example, ram is defined as the cutpoint.

module test(clk, en, addr, din, dout);input clk, en;input [1:0] addr;input [0:0] din;output [0:0] dout;reg [0:0] ram [3:0];// pragma cutpoint "ram”always @(clk or en or addr or din) beginif (clk && en & ram[0] ) ram[addr[1:0]] = din;

endassign dout = ram[addr[1:0]];endmodule



DIR6.1

Message

Ignored compiler directive is detected

Default Severity

Warning

Description

The checker detected the use of an ignored compiler directive. Below is a full list of ignoredcompiler directives:

1. ‘accelerate

2. ‘autoexpand_vectornets

3. ‘default_decay_time

4. ‘default_strength

5. ‘delay_mode

6. ‘delay_mode_distributed

7. ‘delay_mode_unit

8. ‘delay_mode_zero

9. ‘end_pre_16a_paths

10. ‘expand_vectornets

11. ‘line

12. ‘noaccelerate

13. ‘noexpand_vectornets

14. ‘noremove_gatenames

15. ‘nounconnected_drive

16. ‘pre_16a_paths

17. ‘remove_gatenames



18. ‘remove_names

19. ‘switch

20. ‘timescale

21. ‘unconnected_drive

22. ‘unprotected

23. ‘uselib

Example

In the following example, the Verilog RTL accepts compiler directives ‘celldefine and‘endcelldefine on lines 1 and 8. All modules declared after ‘celldefine and before‘endcelldefine are marked as ASIC library cells. Currently only Conformal ConstraintDesigner uses this marking for finding timing paths.

‘celldefinemodule cell1 (a, b);input a;output b;

buf (b, a);endmodule‘endcelldefine



DIR6.2

Message

Supported compiler directive is detected

Default Severity

Warning

Description

The checker detected a supported compiler directive. Below is a full list of supported compilerdirectives:

1. ‘celldefine and ‘endcelldefine

2. ‘define

3. ‘ifdef, ‘ifndef, ‘elsif, ‘endif

4. ‘undef

5. ‘include “<filename>”

6. ‘protect and ‘endprotect

7. ‘protected and ‘endprotected

8. ‘default_nettype net_type

9. ‘resetall

Example

In the following example, the checker supports compiler directive ‘default_nettype wireon line 1 (in bold).

‘default_nettype wiremodule test (din, dout);input din;output dout;

assign dout = din;endmodule



DIR7.1

Message

Unsupported synthesis attribute is detected

Default Severity

Warning

Description

The checker detected a synthesis attribute that it does not support.

Example

In the following example, the checker ignores the attribute MAX_DELAY, rendering it ineffective(see lines 9 and 10).

entity TEST isport(IN1 : in integer;OUT1 : out bit

);end test;

architecture RTL of TEST isattribute MAX_DELAY : string;attribute MAX_DELAY of TEST: entity is “1431”;

beginOUT1 <= ’1’ when IN1 > 329 else ’0’;

end RTL;



DIR7.2

Message

Supported synthesis attribute is detected

Default Severity

Warning

Description

The design includes a synthesis attribute that the checker supports.

Example

The following example defines the attribute ENUM_ENCODING to specify the encoding of theenumeration type (see lines 10 and 11).

entity TEST isport(SEL : in bit_vector(2 downto 0);OUT1 : out bit

);end test;

architecture RTL of TEST istype ET is (ET1, ET2, ET3);attribute ENUM_ENCODING : string;attribute ENUM_ENCODING of ET : type is “00 01 11";signal SIG1 : ET;

beginprocess (SEL)beginif (SEL = "000") thenSIG1 <= ET1;

elsif (SEL = "111") thenSIG1 <= ET2;

elseSIG1 <= ET3;

end if;end process;OUT1 <= ’1’ when (SIG1 = ET3) else ’0’;

end RTL;



DIR8.1

Message

‘protected/‘endprotected pragma is used

Default Severity

Warning

Description

The content after the pragma is protected.

Example

In the following example, line 3 is protected because it is between the ‘protected and‘endprotected directives:

Pragma `protected/`endprotected usedprimitive FOO_P `protectedSOME98098jlkajdGOO`endprotected endprimitive



DIR9.1

Message

Verilog ‘celldefine is for timing simulation. Use the LIBERTY library instead

Default Severity

Ignore

Description

A Verilog module enclosed between ‘celldefine and ‘endcelldefine is recognized asa technology library cell. Conformal Constraint Designer prefers using technology cells in theLIBERTY format, and reports a rule check violation. The default severity for this rule check isERROR. You can override the severity with the SET RULE HANDLING command.

Example

If the following module is read using READ DESIGN or READ LIBRARY command, theConformal software reports this rule check error by default.

‘celldefinemodule TECH_CELL_BUF (Y, A);output Y;input A;

buf I0(Y, A);specifyspecparamtplh$A$Y = 1.0,tphl$A$Y = 1.0;

(A *> Y) = (tplh$A$Y, tphl$A$Y);endspecify

endmodule // TECH_CELL_BUF‘endcelldefine



DIR9.2

Message

Illegal to redefine a Verilog compiler directive as a macro

Default Severity

Warning

Description

You have attempted to redefine a Verilog compiler directives that is one of the following:

‘celldefine

‘default_nettype

‘define

‘else

‘endcelldefine

‘endif

‘ifdef

‘ifndef

‘include

‘nounconnected_drive

‘resetall

‘timescale

‘unconnected_drive

‘undef



Example

The following ‘define statement (see line 1) causes a DIR9.2 rule violation:

‘define timescale 1’b0module test (in,out);input in;output out;assign out = in;endmodule



DIR9.3

Message

Verilog compiler directive is redefined as a macro

Default Severity

Warning

Description

You have attempted to redefine other Verilog compiler directives that are not as follows:

‘celldefine

‘default_nettype

‘define

‘else

‘endcelldefine

‘endif

‘ifdef

‘ifndef

‘include

‘nounconnected_drive

‘resetall

‘timescale

‘unconnected_drive

‘undef



Example

The following ‘define statement (see line 1) causes a DIR9.3 rule violation:

‘define switch 1’b1module test (in,out);input in;output out;assign out = in;endmodule

The above statement causes the ‘switch directive to be deleted and replaced by a user-defined macro.



File

This category of rules applies to designs that include file issues. The following table lists theFile issue (FIL) rule numbers and their messages.

Rule Number Message

FIL1.1 Input file recursion detected



FIL1.1

Message

Input file recursion detected

Default Severity

Error

Description

This detects that input files are included recursively.

Example

The two files in the following example are recursively included:In file file1.v, has ’‘include "file2.v"’.

In file file2.v, has ’‘include "file1.v"’.



Hierarchy

This category of rules applies to designs that are comprised of hierarchical modules. Thefollowing table lists the Hierarchy (HRC) rule check numbers and messages.

Rule Number Message

HRC1.1 Module/entity is not loaded due to unsupported construct (blackboxed)

HRC1.2 Module/entity is not translated (blackboxed)

HRC1.3 Module/entity is undefined and created (blackboxed)

HRC1.4 Module/entity is empty (blackboxed)

HRC1.5 Module/entity is referenced recursively (blackboxed)

HRC2.1 Module/entity instantiated from un-imported library

HRC2.2 Module/entity exists in library and design

HRC2.3 Module/entity is renamed

HRC2.4 Ambiguous component is instantiated

HRC2.6 Multiple component is declared

HRC3.1 Module instance has different number of arguments

HRC3.2 Component is instantiated without specifying any port connection

HRC3.2a Module/entity has no I/O ports

HRC3.3 Undefined named port connection

HRC3.4 Duplicate port connection is detected

HRC3.4a Actual net is connected to more than one port

HRC3.5a Open input/inout port connection is detected

HRC3.5b Open output port connection is detected

HRC3.5c Expression to null port connection is detected

HRC3.6 Port connection width mis-matches. Undriven signals are floating

HRC3.7 Boundary port direction might not be correct

HRC3.8 Port positional association occurred in instantiation

HRC3.9 Constraint contains floating net



HRC3.10 Input port connects to instance output pin. This might cause multipledrivers to the net

HRC3.11 Too many actuals connect to formals

HRC3.12 Port declaration error

HRC3.13 Usage of ’const ref’ port is treated as ’input’ port

HRC4 Multiple root modules/entities are found

HRC5 DesignWare is referenced but not defined

HRC6.1 Mapping empty edif cell to parameterized module is not supported

HRC7 Modules specified by the ‘add notranslate modules’ command cannotbe found

Rule Number Message



HRC1.1

Message

Module/entity is not loaded due to unsupported construct (blackboxed)

Default Severity

Warning

Description

The design includes one or more modules or entities that contain unsupported constructs.The checker will blackbox all modules and entities that contain unsupported constructs.

Example

In the following example, real value 50.2 is an unsupported construct (see lines 7 and 8)(inbold).

module test (clk,in1,out0);input clk,in1;output out0;reg out0;real r1;always @ ( posedge clk )begin if (r1 > 50.2) beginout0 <= in1;endendendmodule



HRC1.2

Message

Module/entity is not translated (blackboxed)

Default Severity

Note

Description

The design includes one or more modules or entities that were blackboxed with thecommand:

add notranslate module <module_name>

Example

Input:

SETUP> add notranslate module SUB

SETUP> read design SUB.v -verilog

// Note: (HRC1.2) Module/entity not translated (black boxed) (occurrence:1)



HRC1.3

Message

Module/entity is undefined and created (blackboxed)

Default Severity

Note

Description

Indicates that blackboxing was specified for design modules that are referenced but notdefined. This message can be generated by the following commands:

■ SET UNDEFINED CELL <blackbox>

■ ADD NOTRANSLATE MODULES

The ADD NOTRANSLATE MODULES command causes undefined modules to be blackboxed.

Example

In the following example, the design references module SUB on line 9, but it is not defined.

module TEST (in0,in1,in2,out0);input in0,in1,in2;output out0;reg out0;always @ ( in0 or in1 )beginout0 = in0 | in1;

endSUB inst1 (.in2(in2));

endmodule



HRC1.4

Message

Module/entity is empty (blackboxed)

Default Severity

Warning

Description

The design includes one or more empty modules or entities. The checker blackboxes allempty modules.

Example

In the following example, the checker blackboxes the empty SUB module.

module SUB (in2, out3);input in2;output out3;endmodule



HRC1.5

Message

Module/entity is referenced recursively (blackboxed)

Default Severity

Warning

Description

The design includes one or more modules that are referenced recursively. The checkerblackboxes all recursively referenced modules.

Example

In the following example, module abc is referenced recursively and will be blackboxed (seeline 4).

module abc (a,b);input a;output b;abc gen1_x1 (a,b);endmodule



HRC2.1

Message

Module/entity instantiated from un-imported library

Default Severity

Warning

Description

The design includes one or more components that are instantiated, but the checker did notfind an imported library containing the components.

Example

In the following example, component SUB is instantiated but the checker did not find animported library (see line 8)(in bold).

ARCHITECTURE arch OF test ISBEGINproc2 : PROCESS (in0, in1, sig2)BEGINout0 <= in0 or in1 or sig2;

END PROCESS;sig1 <= in2;inst1 : SUB PORT MAP (in0=>sig1, out0=>sig2);

END arch;



HRC2.2

Message

Module/entity exists in library and design

Default Severity

Warning

Description

One or more modules or entities exist in both design and library spaces. The checker selectsmodules and entities from the design space.

Example

In the following example, we read in module test for both the library and design spaces.

Input:

SETUP> read library test.v

SETUP> read design test.v



HRC2.3

Message

Module/entity is renamed

Default Severity

Warning

Description

The library space includes one or more modules or entities with the same name. The checkerwill rename these library modules or entities.

Example

In the following example, the design includes the entity name e1 in two libraries (lib1 andlib2). Therefore, the checker renames the el entities as follows:

■ From library lib1:

ENTITY e1 ISPORT (min1: IN bit;

mout1: OUT bit);END;ARCHITECTURE rtl OF e1 ISBEGINmout1 <= not min1;

END;

Library 1: el is renamed lib1_e1

■ From library lib2:

ENTITY e1 ISPORT (min1: IN bit;

mout1: OUT bit);END;ARCHITECTURE rtl OF e1 ISBEGINmout1 <= not min1;

END;

Library 2: el is renamed lib2_e2



HRC2.4

Message

Ambiguous component is instantiated

Default Severity

Warning

Description

A library component is instantiated, but more than one library contains the component.

Example

In the following example, component e1 is instantiated, but both library liba and libbcontain the e1 component (see line 15)(in bold).

LIBRARY liba;LIBRARY libb;USE liba.pkg.ALL;USE libb.pkg.ALL;

ENTITY top ISPORT (in1: IN bit;out1: OUT bit);

END;ARCHITECTURE rtl OF top ISCOMPONENT e1PORT(min1: IN bit; mout1: OUT bit);

END COMPONENT;BEGINinst1: e1 PORT MAP (min1=>in1, mout1=>out1);

END;



HRC2.6

Message

Multiple component is declared

Default Severity

Warning

Description

A component is declared in more than one library.

Example

In the following example, In line 13, component c1 is declared in both lib1, package pp1and lib2, package pp2:

library lib1, lib2;use lib1.pp1.all;use lib2.pp2.all;ENTITY top ISPORT (ccc : IN bit;bbb : IN bit;ooo : OUT bit);

END top;ARCHITECTURE rtl OF top ISBEGINu0: c1 port map (ccc=>ccc, bbb=>bbb, ooo=>ooo);

END rtl;



HRC3.1

Message

Module instance has different number of arguments

Default Severity

Warning

Description

The design includes one or more module instances with arguments that differ from themodule definition.

Example

In the following examples, instance inst1 has 3 connections, but module sub has only 2ports:

module sub (in2,out3);input in2;output out3;assign out3 = in2;endmodule

module test (in2,out0);input in2;output out0;sub inst1 (in2,in2,out0);

endmodule



HRC3.2

Message

Component is instantiated without specifying any port connection

Default Severity

Warning

Description

The design includes one or more components that are instantiated but do not have a portconnection.

Example

In the following example, module SUB is instantiated, but has no connected ports (see line4)(in bold).

module TEST (in2,out0);input in2;output out0;

SUB inst1 ();

endmodule



HRC3.2a

Message

Module/entity has no I/O ports

Default Severity

Warning

Description

The module has no I/O ports.

Example

In the following example, module ABC does not have any I/O ports.

module ABC;endmodule



HRC3.3

Message

Undefined named port connection

Default Severity

Error

Description

The design includes one or more module instances that refer to undefined ports.

Example

In the following example, module sub references port in4, but does not define it (see line4)(in bold).

module test(a, b, c, d, e);input a, b, c, d;output e;sub inst0 (.in1(a),.in2(b),.in3(c),.in4(d), .out1(e));endmodule

module sub (in1, in2, in3, out1);input in1, in2, in3;output out1;wire out1;assign out1 = in1 ^ in2;endmodule



HRC3.4

Message

Duplicate port connection is detected

Default Severity

Warning

Description

The design includes duplicate ports that the checker has ignored.

Example

In the following example, the checker will ignore the duplicate port .c included on line 4.

module test (a, b, q);input [3:0] a, b;output [3:0] q;sub sub1 (.c(a), .c(b), .q1(q));endmodule

module sub (c, d, q1);input [3:0] c, d;output [3:0] q1;assign q1 = c | d;endmodule



HRC3.4a

Message

Actual net is connected to more than one port

Default Severity

Warning

Description

Actual net is connected to more than one port in module declaration.

Example

In the following example, din is connected to both .in1 port and .in2 port (see line 1).

module sub(.in1(din), .in2(din), .out(dout));input din;output dout;assign dout = din;endmodule

module top(din, dout);input din;output dout;sub sub1(.in1(din), .in2(din),.out(dout));endmodule



HRC3.5a

Message

Open input/inout port connection is detected

Default Severity

Warning

Description

The design includes one or more input or inout ports with open connections.

Example

In the following example, the connection for port .d is open (see line 4).

module test (a, b, q);input [3:0] a, b;output [3:0] q;sub sub1 (.c(a), .d(), .q1(q));endmodule




HRC3.5b

Message

Open output port connection is detected

Default Severity

Note

Description

The design includes one or more output ports with open connections.

Example

In the following example, the connection for port .q1 is open (see line 4).

module test (a, b, q);input [3:0] a, b;output [3:0] q;sub sub1 (.c(a), .d(b), .q1());endmodule




HRC3.5c

Message

Expression to null port connection is detected

Default Severity

Warning

Description

The design includes one or more null ports with open connections.

Example

In the following example, the connection between module port c and d is open (see line 4).

module test (a, b, q);input [3:0] a, b;output [3:0] q;sub sub1 (a, x, b, q);endmodule

module sub (c,, d, q1);input [3:0] c, d;output [3:0] q1;assign q1 = c | d;endmodule



HRC3.6

Message

Port connection width mis-matches. Undriven signals are floating

Default Severity

Warning

Description

The design includes at least one port that has port connection width mis-matches.

Example

In the following example, port_name out1, which is two-bit, is greater in size thanport_expr e, which is one-bit. See line 4 (in bold).

module test(a, b, e);input a, b;output e;sub inst0 (.in1(a),.in2(b),.out1(e));endmodule

module sub (in1, in2, out1);input in1, in2 ;output [1:0] out1;wire [1:0] out1;assign out1 = {in1,in2};endmodule



HRC3.7

Message

Boundary port direction might not be correct

Default Severity

Warning

Description

The design includes one or more module boundary ports that might be declared incorrectlybecause of their irregular use.

Example

In the following example, both input in1 and input in2, drive output out0. Thus, the checkerinterprets this situation to mean that input in2 is incorrectly declared (see lines 4 and 5).

module test(in1, in2, out0);input in1, in2;output out0;not U1 (out0, in1);assign out0=in2;endmodule

Note: For multi-driven nets, the checker applies wire-AND resolution by default.



HRC3.8

Message

Port positional association occurred in instantiation

Default Severity

Warning

Description

The design includes one or more module instances that use port positional association. In apositional association, the port_exprs connect to the ports of the module in the specifiedorder.

Port positional association syntax:

module_name instance_name( port_expr1,

port_expr2, …);

Example

In the following example, port_expr a connects to port o0 and port_expr b connects to porto1 of module sub. See line 9 (in bold).

module sub (o0, o1);output o0, o1;assign o0 = 1'b0;assign o1 = 1'b1;endmodule

module test(a, b);output a, b;sub s1(a, b);endmodule



HRC3.9

Message

Constraint contains floating net

Default Severity

Warning

Description

The constraint has floating nets.

Example

In the following example, val is a floating net (see line 8):module test(in, out);input in;output out;wire val;assign out = in;endmoduleappend_to module test;$constraint( val == 1'b1);endmodule



HRC3.10

Message

Input port connects to instance output pin. This might cause multiple drivers tothe net

Default Severity

Warning

Description

There is an input port connected to an instance output pin. This could cause multiple driversto the net.

Example

In the following example, the input pin b is connected to the instance sub output pin o1. Inmodule ABC it is an input pin, and in sub s1 is is an output pin.

module sub (o0, o1);output o0, o1;assign o0 = 1'b0;assign o1 = 1'b1;endmodulemodule ABC(a, b);output a;input b;sub s1(a, b);

endmodule



HRC3.11

Message

Too many actuals connect to formals

Default Severity

Error

Description

The number of actuals in the port map is more than the number of formals.

Example

In the following example, there are three actuals but only two formals (see line 20):

entity sub isport (o0, o1 : out bit

);end sub;architecture arch of sub isbegino0 <= '0';o1 <= '1';

end arch;entity test isport (a : out bit;b : out bit;c : in bit

);end test;architecture arch of test isbeginu1 : sub port map (o0 => a, o1=> b, o1 =>c);

end arch;



HRC3.12

Message

Port declaration error

Default Severity

Error

Description

The external port name specified by .name should not conflict with other internal port names,or other external port names.

Example

In the following example, you cannot redeclare a1 input a1:

module hrc3_12 (.a1(a1));endmodule;



HRC3.13

Message

Usage of ’const ref’ port is treated as ’input’ port

Default Severity

Warning

Description

The ’const ref’ port is treated as ’input’ port. You will get this message when running the READDESIGN -systemverilog command to read in the design and there is a violation on thisrule.

Example

In the following example, in line 5, port ’din’ of function func is declared as ’const ref’, it will betreated as ’input’ port.

module test(in, out);input in;output reg out;function func;const ref din;beginfunc = din;

endendfunctionalways @(in)out = func(in);

endmodule



HRC4

Message

Multiple root modules/entities are found

Default Severity

Warning

Description

The design includes multiple modules or entities at the top level of hierarchy; thus, any oneof them can be designated as the root module. By default, the checker selects the modulewith the greatest gate count.

Example

In the following example, the file test.v contains two possible root modules, TEST0 andTEST1.

test.v file:module TEST0 (in0,in1,in2,out0);input in0,in1,in2;output out0;assign out0 = in0 | in1;endmodule

module TEST1 (in0,in1,in2,out0);input in0,in1,in2;output out0;assign out0 = in0 & in1;endmodule



HRC5

Message

DesignWare is referenced but not defined

Default Severity

Warning

Description

The design includes one or more DesignWare multiplier/divider instances, but does not definethem. The checker supplies the missing definition, using a Conformal multiplier definition.

Example

In the following example, DesignWare multiplier DW02_mult is instantiated (see line 9), butthe design does not define it. The checker will supply the missing DW02_mult definition witha Conformal multiplier definition.

module test(A,B,TC,PRODUCT);parameter A_width = 8;parameter B_width = 8;

input [A_width-1:0] A;input [B_width-1:0] B;input TC;output [A_width+B_width-1:0] PRODUCT;

DW02_mult mult_1 (A,B,TC,PRODUCT);endmodule



HRC6.1

Message

Mapping empty edif cell to parameterized module is not supported

Default Severity

Warning

Description

The EDIF design includes an empty cell that is an instance of a parameterizable Verilogmodule, which is not supported.

Example

In the following example, top.edf is an EDIF file that contains a cell called CTLBLK, whichis defined in a Verilog module.

CTLBLK module:

module CTLBLK( A, SUM );parameter INIT = 16'h0000;…endmodule

Input:

> read design top.edf -golden -edif

// Warning: (HRC6.1) Mapping empty edif cell to parameterized module is notsupported (occurrence:1)



HRC7

Message

Modules specified by the ‘add notranslate modules’ command cannot be found

Default Severity

Warning

Description

A module cannot be found in the design that was specified with the ADD NOTRANSLATEMODULES command.

Example

In the following example mod1 is the name of module that does not exist in the design.

Input:

> add notranslate modules mod1

// Warning: (HRC7) Modules specified by the ‘add notranslate modules’ commandcannot be found (occurrence:2)



Ignored

This category of rules applies to designs that include constructs or statements that are eitherredundant or unsupported, and thus ignored by the checker. The following table lists theIgnored (IGN) rule numbers and messages. The severity level for all IGN rule checkmessages is warning.

Rule Number Message

IGN1.1 initial assignment is ignored

IGN1.2 final construct is ignored

IGN2.1 Delay value(s) are ignored

IGN2.2 Illegal defparam statement(s) are ignored

IGN2.3 Unsupported defparam statement is ignored

IGN3.1 Duplicated pin/port names are detected and ignored

IGN3.2 Duplicate modules/entities are detected. Subsequent modules/entities are ignored

IGN3.3 Multiple declarations of same packages are detected. Earlierdeclarations are ignored

IGN3.4 Duplicate modules/entities are detected. Previous modules/entities are ignored

IGN3.5 Duplicate modules/entities are detected. Local module/entity isused

IGN3.6 Blackbox is replaced with the current module/entity

IGN4 Attribute instance(s) are ignored

IGN5.1 Liberty state table is ignored with the -nostatetable option

IGN5.2 Liberty attribute is ignored

IGN5.3 Liberty state table contains lowercase value(s) and is ignored

IGN6.1 timeunit statement is ignored

IGN6.2 timeprecision statement is ignored

IGN7.1 trireg net is treated as regular wire net



IGN1.1

Message

initial assignment is ignored

Default Severity

Warning

Description

The initial statement is a SystemVerilog construct for simulation that the checker doesnot support. Thus, when the checker detects this construct in the syntax, it ignores the entireinitial construct. Similarly, the checker reports rule IGN1.2 for the final statement.

Example

In the following example, the checker ignores the keyword initial. See line 5 (in bold).

module test ( clk, din, dout );input clk, din;output dout;wire dout;initial dout = !din;assign dout = din;endmodule



IGN1.2

Message

final construct is ignored

Default Severity

Warning

Description

The final statement is a SystemVerilog construct for simulation that the checker does notsupport. Thus, when the checker detects this statement in the syntax, it ignores the entirefinal statement. Similarly, the checker reports rule IGN1.1 for the initial statement.

Example

In the following example, the checker ignores the entire final statement. See lines 7, 8, and9 (in bold).

module test(aa, bb, o1, o2);input aa, bb;output o1, o2;assign o1 = aa == bb;assign o2 = aa != bb;

final begin$display(“done”);

endendmodule



IGN2.1

Message

Delay value(s) are ignored

Default Severity

Warning

Description

The checker has ignored one or more delay values.

Example

In the following example, the checker ignores delay value #(10). See line 5 (in bold).

module test ( clk, din, dout );input clk, din;output dout;wire dout;not #(10) (dout, din);endmodule



IGN2.2

Message

Illegal defparam statement(s) are ignored

Default Severity

Warning

Description

The design uses one or more defparam keywords illegally. The checker ignores illegallyused defparam keywords.

Example

In the following example, P8P is undefined. The checker will ignore the statement. See line 4(in bold).

module test ( clk, din, dout );input clk, din;output dout;defparam P8P.INI=8'h88;assign dout = din;endmodule



IGN2.3

Message

Unsupported defparam statement is ignored

Default Severity

Warning

Description

The defparam directive is unsupported and ignored.

Example

In the following example, defparam is ignored (see line 16):

module sub1(aa, oo);parameter NN = 1'b0;input aa;output oo;assign oo = aa & NN;

endmodulemodule sub2(aa, oo);input aa;output oo;sub1 u0 [2:0] (aa, oo);

endmodulemodule sub3(aa, oo);input aa;output oo;sub2 u0(aa, oo);defparam u0.u0[0].NN = 1'b1;

endmodule



IGN3.1

Message

Duplicated pin/port names are detected and ignored

Default Severity

Warning

Description

The design includes duplicate pins or ports.

Example

In the following example, the checker ignores the duplicated port dout (see the first line)

module test ( dout, clk, din, dout );input clk, din;output dout;reg dout;always @(posedge clk)dout <= din;endmodule



IGN3.2

Message

Duplicate modules/entities are detected. Subsequent modules/entities are ignored

Default Severity

Warning

Description

The design includes duplicate modules or entities. The checker ignores duplications.

Example

In the following example, the design duplicates module test. The checker ignores thesecond module test.

Note: Ellipses ( … ) denote characters that are present in the file, but not shown in thisexample.

module test ( clk, din, dout );…endmodule

module test ( clk, din, dout );…endmodule



IGN3.3

Message

Multiple declarations of same packages are detected. Earlier declarations areignored

Default Severity

Warning

Description

There are multiple declarations of the same package. The checker ignores earlierdeclarations.


Example

In the following example, the first declaration for pkg is ignored.

package pkg isCONSTANT val1 : bit := ’1’;

end pkg;

package pkg isCONSTANT val1 : bit := ’0’;

end pkg;



IGN3.4

MessageDuplicate modules/entities are detected. Previous modules/entities are ignored

Default Severity

Warning

Description

There are multiple definitions for a module or entity. The checker takes the last definition andignores previous ones. This usually occurs when you use the -lastmod option with the READDESIGN command.

Example

In the following example, the checker ignores the first definition for test when you use theread design -lastmod test.v -replace command.module test ( clk, din, dout );input clk, din;output dout;reg dout;

always @(posedge clk)dout <- din;

endmodule

module test (clk, din, dout );input clk, din;output dout;reg dout;

always @(posedge clk)dout <= din;

endmodule



IGN3.5

Message

Duplicate modules/entities are detected. Local module/entity is used

Default Severity

Warning

Description

Duplicate modules are found and the Conformal software uses the local module. If you wantto use the local module, you must use the read design -localref command.

Example

In the following example, you can use read design -localref to use local module sub1(see lines 9 for each of the following files). For each file, the instantiation of sub1 in lines 9will use the sub1 defined in lines 1 (module sub1(aa, oo)).

File mod1.v

module sub1(aa, oo);input aa;output oo;assign oo = aa;

endmodulemodule mod1(aa, oo);input aa;output oo;sub1 u0 (aa, oo);

endmodule

File mod2.v

module sub1(aa, oo);input aa;output oo;assign oo = !aa;

endmodulemodule mod2(aa, oo);input aa;output oo;sub1 u0 (aa, oo);

endmodule



IGN3.6

Message

Blackbox is replaced with the current module/entity

Default Severity

Warning

Description

The blackbox module is replaced by a non-blackbox module.

Example

In the following example, same module, but the first one is a blackbox, so this will replace themodule sub1 in mod2.v will replace the modue sub1 in mod1.v. Use read design-bboxsolver to replace sub1 with a non-blackbox model

File mod1.v:module sub1(aa, oo);input aa;output oo;// this is a bbox

endmodule

File mod2.v:module sub1(aa, oo);input aa;output oo;assign oo = !aa;

endmodule



IGN4

Message

Attribute instance(s) are ignored

Default Severity

Warning

Description

The checker has ignored one or more attribute instances.

Example

In the following example, the checker ignores the attribute instance (* a = b *). See line 4.

module test(a, b);input a;output b;(* a = b *) assign b = a;endmodule



IGN5.1

Message

Liberty state table is ignored with the -nostatetable option

Default Severity

Note

Description

A Liberty file contains a state table and is ignored due to the -nostatetable optionspecified in the READ DESIGN or READ LIBRARY command. The checker does not supportstate tables.

Example

In the following example, while reading the Liberty library lsi_10k.lib, the checkerencountered 17 occurrences of the unsupported state table. Refer to the state table examplebelow.

Input:

SETUP>read lib -lib lsi_10k.lib

// Parsing file lsi_10k.lib…

// Warning: (IGN5.1) Liberty State Table is not supported and is ignored

(occurrence:17)

State Table Example:

statetable ( " D CP ", " Q QN") {table : " - ~R : - - : N N, \

H/L R : - - : H/L L/H";}



IGN5.2

Message

Liberty attribute is ignored

Default Severity

Ignore

Description

The Liberty attribute is ignored.

Example

Some unsupported attributes are:

poly_template

hyperbolic_noise_above_high

hyperbolic_noise_low

hyperbolic_noise_high

steady_state_current_high

steady_state_current_low

steady_state_current_tristate



IGN5.3

Message

Liberty state table contains lowercase value(s) and is ignored

Default Severity

Warning

Description

The parser found lowercase value(s) in the truth table of the statetable. These must bechanged to uppercase.

Example

In the following example, lines 2 and 3 shows that the edge value(s) ’~r’ and ‘r’ are writtenin lowercase, which should be changed to uppercase:

statetable( " D CP" , " Q QN" ) {

table : " - ~r : - - : N N,\

H/L r : - - : H/L L/H" ;

}



IGN6.1

Message

timeunit statement is ignored

Default Severity

Warning

Description

The timeunit statement is a SystemVerilog construct for simulation that the checker doesnot support. When the checker detects this statement in the syntax, it ignores the entiretimeunit statement. Similarly, the checker reports rule IGN6.2 for the timeprecisionstatement.

Example

In the following example, the checker ignores the timeunit statement on line 2:

module test(aa, bb, o1, o2);timeunit 1ps;input aa, bb;output o1, o2;assign o1 = aa == bb;assign o2 = aa != bb;

endmodule



IGN6.2

Message

timeprecision statement is ignored

Default Severity

Warning

Description

The timeprecision statement is a SystemVerilog construct for simulation that the checkerdoes not support. When the checker detects this statement in the syntax, it ignores the entiretimeprecision statement. Similarly, the checker reports rule IGN5.3 for the timeunitstatement.

Example

In the following example, the checker ignores the timeprecision statement on line 2:

module test(aa, bb, o1, o2);timeprecision 0.1ps;input aa, bb;output o1, o2;assign o1 = aa == bb;assign o2 = aa != bb;

endmodule



IGN7.1

Message

trireg net is treated as regular wire net

Default Severity

Warning

Description

A trireg net can model a charge storage node whose charge decays over time. TheConformal software does not support charge storage and charge decays. As a result, thesoftware treats a trireg net as regular wire net.

Example

In the following example, the checker ignores the trireg statement on line 3 (in bold).

module test (clk, in1, out1);input clk;input trireg in1;output reg out1;

always @(clk)out1 = in1;

endmodule



Register Transfer Level

This category of rules applies to designs that are written in the register transfer level ofabstraction. The following table lists the Register Transfer Level (RTL) rule numbers andmessages.

Rule Number Message

RTL1.1 Variable/signal is assigned by more than one concurrent statement

RTL1.2 Variable/signal is assigned by multiple non-blocking assignments

RTL1.2a Variable/signal on instance INOUT port might have multiple drivers

RTL1.3 Variable/signal is assigned by both blocking and non-blockingassignments

RTL1.4 Assignment with LHS bit width is greater than RHS bit width

RTL1.5a Assignment with RHS bit width is greater than LHS bit width

RTL1.5b Potential loss of RHS msb or carry-out bit

RTL1.6 Blocking assignment is in sequential always block

RTL1.7 Non-blocking assignment is in combinational always block

RTL1.8 Latch is assigned by blocking assignments

RTL1.9 Parameter bit width does not match RHS bit width

RTL1.11 Variable is assigned by both continuous and procedural statements

RTL1.12 variable(SV:logic/bit) is assigned by multiple continuous statements

RTL1.13 Mismatched enumeration types are in the assignment

RTL1.14 Mismatched enumeration types are in the expression

RTL2.1 Variable is referenced before the assignment

RTL2.1a Variable is referenced before assignment in subprogram. Possiblesimulation mismatch

RTL2.2 Variable is referenced but never assigned

RTL2.3 Externally defined signal reference is not supported

RTL2.4 Externally defined signal reference is supported

RTL2.5 Undriven net is detected

RTL2.6 Shared variables are not supported



RTL2.7 Dynamic slice is not supported

RTL2.8 ’BUS’ and ’REGISTER’ signal type are not supported for synthesis

RTL2.9 Guarded assignment requires GUARD signal

RTL2.10 GUARD is not declared

RTL2.11 Implicitly declared GUARD signal cannot be updated

RTL2.12 Illegal redeclaration of GUARD signal

RTL2.13 Undriven pin is detected

RTL3.1 Variable/signal is unassigned in asynchronous set/reset

RTL3.2 Assignment of X is in asynchronous set/reset branch

RTL3.3 Non-constant value assignment is in asynchronous set/reset value

RTL3.4 DFF/DLAT is with both asynchronous set and reset connections

RTL3.5 Variable/signal is assigned without using asynchronous set/reset

RTL4.1 Enum encoding is applied to enum type

RTL4.2 Multiple wait statements. FSM encoding might be different

RTL4.3 Enum value size is different than the declared data type

RTL4.4 Encoding format has too many values

RTL5.1 Overlapped case items are in parallel case statement

RTL5.2 Non-binary case items are in case statement

RTL5.3 Case expressions/items are resized

RTL5.4 Partial case items are in full case statement

RTL6.1 X created due to the assignment of value X

RTL6.2 Integer value range constraint is added

RTL6.3 X created when divisor equals to zero

RTL6.4 Enum value constraint is added

RTL6.5 priority if and unique if statements are incomplete

RTL6.6 unique if statements have redundant or overlapping conditions

RTL7.1 Design includes comparison that uses X or Z values

Rule Number Message



RTL7.2 Gate or transistor primitive is using weak attributes

RTL7.3 Array index in RHS might be out of range

RTL7.4 Array index in LHS might be out of range

RTL7.5 Input signal is assigned by logic values

RTL7.6 Value X or Z is treated as 0 in unary/binary expressions

RTL7.7 Real number rounded to integer value

RTL7.8 Overflowed integer is truncated

RTL7.9 Sign overflowed integer is truncated

RTL7.10 Comparison with signed and unsigned operands

RTL7.11 Implicit signed expression is converted to unsigned

RTL7.12 Unsized integer number is truncated to 32 bits

RTL7.13 Logical operator is applied to multiple-bit operand

RTL7.14 Loop exceeds maximum iterations

RTL7.15 Null slice is not supported

RTL7.16 Variable index is out of the defined range

RTL7.17 Exponentiation operator is unsupported

RTL7.18 Argument size to integer type conversion is too large

RTL7.19 Added constraint on integer overflow for arithmetic operation ADD/SUB

RTL7.20 Size value in size’(expr) casting is too large

RTL7.21 Real variables are not supported

RTL8.1 Multiple multipliers/dividers are in module/entity

RTL8.2 Latch(es) are inferred due to an incomplete conditional statement

RTL8.3 Unreachable DFF/DLAT is removed

RTL8.4 Unreachable DFF/DLAT is kept

RTL8.5 Implicit signed multiplier is detected in module/entity

RTL9.1 Instance inout/output port has dynamic indexing. Treated as floating

RTL9.2 Design has irregularly used inout/output expression

Rule Number Message



RTL9.3 Supply0/supply1 is converted into a wire

RTL9.4 Supply0/supply1 net is not a module port

RTL9.5 Power pin is converted to an input pin

RTL9.7 Cannot read value from OUT port

RTL9.8 Set Liberty pin direction to output because it has an output function

RTL9.9 Extra ’;’ is detected in port list

RTL9.10 Liberty cell does not use any input pin

RTL9.11 Liberty Master-Slave DFF cell clock phase does not match the timingtable

RTL9.12 Liberty cell with internal_node does not have correct statetable

RTL9.13 Set liberty cell to blackbox because some of its output pins have nofunction

RTL9.14 Liberty cell has duplicate signal (pin/member)

RTL10 Both posedge and negedge are used in different always/process

RTL11 Incomplete condition is in a function/procedure/task block

RTL12 Referenced variable(s)/signal(s) are not in sensitivity list

RTL12.1 Constant object is in sensitivity list

RTL13 For loop condition is always false

RTL13.1 The FOR-LOOP index should not be assigned within the loop itself

RTL13.2 The evaluation of for-loop condition is not constant

RTL14 Signal with fanin drive and no fanout load is detected

RTL14.1 Fanout load of the signal is removed

RTL15 Clock and asynchronous set/reset expression must be one bit wide

RTL15.1 Else branch of event controlled if statement is not supported

RTL15.2 Sensitivity/clock style is unsupported

RTL16.1 Non-local variable is read in a function body

RTL16.2 Non-local variable is assigned in a function body

RTL17 Variable size exceeds the maximum limit

Rule Number Message



RTL17.1 Expression size exceeds the maximum limit

RTL18.1 Package is not an IEEE standard

RTL18.2 Function definition has empty body

RTL18.3 Function call does not refer to a function definition

RTL18.4 Ignoring resolution function. This might cause mismatches betweensimulation and synthesis

RTL19.1 Identifier is a reserved keyword and might conflict in designs with mixedlanguages

RTL20.1 Pre-defined attribute is not supported

RTL20.2 Function is not supported

RTL20.3 Could not find configuration

Rule Number Message



RTL1.1

Message

Variable/signal is assigned by more than one concurrent statement

Default Severity

Warning

Description

The design includes one or more cases where a variable or signal is assigned by two or moreconcurrent statements.

Example

In the following example, the design concurrently assigns output out0. See lines 4 and 5 (inbold).

module SEN (clk,rst,in0,in1,out0);input clk,rst,in0,in1;output out0;assign out0 = in0 & in1;assign out0 = in1 & in0;endmodule



RTL1.2

Message

Variable/signal is assigned by multiple non-blocking assignments

Default Severity

Warning

Description

The design includes one or more cases where a variable or signal is assigned by two or morenon-blocking assignments.

Example

In the following example, variable out0 is assigned by a non-blocking assignment. See lines7 and 8 (in bold).

module VLGT (clk,rst,in0,in1,out0);input clk,rst,in0,in1;output out0;reg out0;always @(posedge clk)beginout0 <= in0 & in1;out0 <= in1 & in0;

endendmodule



RTL1.2a

Message

Variable/signal on instance INOUT port might have multiple drivers

Default Severity

Warning

Description

The variable or signal on the INOUT instance port might have multiple drivers.

Example

In the following example, in line 4 , ports VSSA and VSSG are defined as INOUT ports in thelibrary file:

module mod1_G(Y,A,VDDA,VSSA,VDDG,VSSG);input A, VDDA, VSSA, VDDG, VSSG;output Y;KAQ2 I0(.Y(I0_Y), .A(A), .VDD_A(VDDA), .VSS_A(VSSA), .VDD_G(VDDG), \.VSS_G(VSSG));

KAQ2 I2(.Y(Y), .A(I0_Y), .VDD_G(VDDG), .VSS_G(VSSG), .VDD_A(VDDA), \.VSS_A(VSSA));

endendmodule;



RTL1.3

Message

Variable/signal is assigned by both blocking and non-blocking assignments

Default Severity

Warning

Description

The design includes one or more cases where a variable or signal is assigned by bothblocking and non-blocking assignments.

Example

On line 7 of the following example, variable out0 is assigned by a blocking assignment, andon line 9, variable out0 is assigned by a non-blocking assignment.

module VGT (rst,in0,in1,out0);input rst,in0,in1;output out0;reg out0;always @(rst or in1 or in0) beginif (rst)out0 = in1 & in0;

elseout0 <= in0 & in1;

endendmodule



RTL1.4

Message

Assignment with LHS bit width is greater than RHS bit width

Default Severity

Warning

Description

The design includes one or more assignments with a left-hand-side (LHS) bit width greaterthan the right-hand-side (RHS) bit width.

Example

In the following example, the assignment of in0 to out0 has mismatched bit widths. See line6 (in bold).

module VT (clk,in0,out0);input clk,in0;output [3:0] out0;reg [3:0] out0;always @(posedge clk) beginout0 <= in0;

endendmodule



RTL1.5a

Message

Assignment with RHS bit width is greater than LHS bit width

Default Severity

Warning

Description

The design includes one or more assignments with a right-hand-side (RHS) bit width greaterthan the left-hand-side (LHS) bit width.

Example

1. In the following example, the design assigns a two-bit vector logic 2'b01 to a one-bitoutput out0 (see line 3).

module test(out0);output out0;assign out0 = 2'b01;endmodule

2. In the following Verilog example, the self-determined bit width for the RHS expression is5, while the LHS is only 4.

x[3:0] = a[4:0] + b [4:0];



RTL1.5b

Message

Potential loss of RHS msb or carry-out bit

Default Severity

Warning

Description

The design includes one or more assignments where there is potential for the right-hand-side(RHS) to lose its most-significant-bit (MSB) or carry-out bit.

Example

1. In the following example, the self-determined bit width of the RHS is 4 and the LHS isalso 4; however, x[3:0] does not take the potential carry-out from the RHS.

x[3:0] = a[3:0] + b[3:0];

2. In the following Verilog example, the self-determined bit width for the RHS is 4 and theLHS is also 4; however, arithmetically, the product is 8 bits and x[3:0] only takes thelower 4 bits of the total 8 bits.

x[3:0] = a[3:0] * b[3:0];



RTL1.6

Message

Blocking assignment is in sequential always block

Default Severity

Warning

Description

The design includes one or more blocking assignments in a sequential always block.

Example

On lines 7 and 9 of the following example, the design uses blocking assignments:

module VLGT (clk,rst,in0,in1,out0);input clk,rst,in0,in1;output out0;reg out0;always @(posedge clk) beginif (rst)out0 = in1 & in0;

elseout0 = in0 & in1;

endendmodule



RTL1.7

Message

Non-blocking assignment is in combinational always block

Default Severity

Warning

Description

The design includes one or more non-blocking assignments in a combinational always block.

Example

On lines 7 and 9 of the following example, the design uses non-blocking assignments:

module VT (sel,in0,in1,out0);input sel,in0,in1;output out0;reg out0;always @(sel or in1 or in0) beginif (sel)out0 <= in1 & in0;

elseout0 <= in0 & in1;

endendmodule



RTL1.8

Message

Latch is assigned by blocking assignments

Default Severity

Warning

Description

The design includes one or more latches that are coded using a blocking assignment. Werecommend that sequential elements be coded using a non-blocking assignment rather thana blocking assignment.

Example

In the following example, latch Q is coded using a blocking assignment (see line 7):

module Dlat(data, en, Q);input data, en;output Q;reg Q;

always @( en or data)if (en) Q = data;

endmodule



RTL1.9

Message

Parameter bit width does not match RHS bit width

Default Severity

Warning

Description

The design includes one or more parameter bit widths that do not match with right-hand-side(RHS) bit widths.

Example

In the following example, parameter my_values is declared as a 3-bit vector, but wasassigned a 4-bit vector (see line 3):

module test (Z);output [3:0]Z;parameter signed [2:0] my_values = 4’b1010;assign Z = my_values;endmodule



RTL1.11

Message

Variable is assigned by both continuous and procedural statements

Default Severity

Error

Description

A variable is assigned by both continuous and procedural statements.

Example

In the following example, variable t1 is assigned in lines 5 and 8.

module test (a, b,t1);input a,b ;output t1 ;logic t1 ;assign t1 = a & b;always @(a or b )begintask1 (t1);

endtask task1 (output c);beginc = a | b;

endendtaskendmodule



RTL1.12

Message

variable(SV:logic/bit) is assigned by multiple continuous statements

Default Severity

Error

Description

A variable is assigned by multiple continuous statements.

Example

In the following example, variable t1 is assigned in lines 5 and 6.

module test (a, b,t1);input a,b ;output t1 ;logic t1 ;assign t1 = a & b;assign t1 = a | b;endmodule



RTL1.13

Message

Mismatched enumeration types are in the assignment

Default Severity

Error

Description

There are mismatched enumeration types in the assignment.

Example

In the following example, In line 5, read and din have mismatched enumeration type.

typedef enum {write , add, sub, mult} instr_t;typedef enum {WAIT, LOAD, STORE} state_t;module test(output state_t read, input instr_t din);always_combread = din;

endmodule



RTL1.14

Message

Mismatched enumeration types are in the expression

Default Severity

Error

Description

There are mismatched enumeration types in the expression.

Example

In the following example, In line 6, enumeration types are mismatched.

module test (output integer out1) ;enum {IDLE=2’b00, S1, S2} state;assign state = S1;always @*beginout1 = (state == 4)? 2’b00:state;

endendmodule



RTL2.1

Message

Variable is referenced before the assignment

Default Severity

Warning

Description

The design includes one or more variables that are referenced before they are assigned.

Example

On line 8 of the following example, the design references variable sig1, but does not assignit until line 9:

module TPS (clk,in1,in2,out0);input clk,in1,in2;output out0;reg out0;always @ (in1 or in2)beginreg sig1;out0 = sig1;sig1 = in1 | in2;

endendmodule



RTL2.1a

Message

Variable is referenced before assignment in subprogram. Possible simulationmismatch

Default Severity

Warning

Description

For initialized variable in subprogram, simulation mismatch might occure when the variable isreferenced before the assignment. For the Conformal Equivalence Checking software andsynthesis tools, the variable will default to 0. However, for simulation, the variable assumespreviously assigned value.

Example

In the following example, in line 16, variable nxt_svl is referenced before assignment. Thiscan cause a simulation or synthesis mismatch.

function [11:0] foo;...reg nxt_svl;begin

if (reset)begin...nxt_svl = 1’b0;...

endelsebegin...case (state)state0:if (nxt_svl)...

state5:nxt_svl = 1’b1;

...endfunction



RTL2.2

Message

Variable is referenced but never assigned

Default Severity

Warning

Description

The design includes one or more variables that are referenced but never assigned in thedesign.

Example

In the following example, the design references variable da0, but never assigns it:

module SEN (clk,rst,out0);input clk,rst;output out0;reg out0;reg da0;always @ ( posedge rst or posedge clk )beginif (rst) begin

out0 <= 1'b0;endelse begin

out0 <= da0;end

endendmodule



RTL2.3

Message

Externally defined signal reference is not supported

Default Severity

Warning

Description

The checker did not support one or more externally defined signal references when they wereused in multiple entities. The checker only supports one entity that uses the externally definedsignal.

Example

In the following example, the design references the externally defined signal glob1 inmultiple entities, which causes the checker to error out.


PACKAGE pack ISSIGNAL glob1 : boolean;

END PACK;

USE work. pack.all;ENTITY test IS

…

END test;ARCHITECTURE arch OF test IS…glob1 <= in0 or in1;

END arch;

ENTITY test2 IS…END test2;ARCHITECTURE arch OF test2 IS…glob1 <= in0 or in1;

END arch;



RTL2.4

Message

Externally defined signal reference is supported

Default Severity

Note

Description

The checker supports one or more externally defined signal references. The checker onlysupports the first entity that uses the externally defined signal.

Example

In the following example, the design uses signal glob1 although it is defined outside entityTEST (see line 13).

package pack issignal glob1 : boolean;

end pack;use work. pack.all;entity TEST isport (in0, in1, in2 : in boolean;out0 : out boolean

);end test;architecture arch of test isbeginglob1 <= in0 or in1;out0 <= glob1 and in2;

end arch;



RTL2.5

Message

Undriven net is detected

Default Severity

Warning

Description

The specified wire is not assigned. It is connected to an object indicating that the wire hasbeen read at least once. Such usage leads to redundant code, undefined states, and errors.To avoid this, assign wires properly. If unassigned wires are not used, remove them. This rulehonors the synthesis off or on pragmas. This implies that a wire is considered unassignedwhen assignment is made inside synthesis off or on pragma and its declaration is outside thepragma.

Example

In the following example, g1 (line 5) is an undriven net:module unassigned_wire (in1, out1);input in1;output out1;wire g1;assign out1 = in1 & g1;

endmodule



RTL2.6

Message

Shared variables are not supported

Default Severity

Warning

Description

Shared variables are not supported. To avoid this error, remodel the design.

Example

In the following example, shared variable counter (line 8) is not supported:library IEEE;use IEEE.std_logic_1164.all;entity shared_variables isport (DataIn : in integer);

end entity shared_variables;architecture shared_variables_arch of shared_variables issubtype ShortRange is integer range 0 to 1;shared variable counter : ShortRange := 0;

beginPROC1:processbegincounter := counter + 1;wait;

end process PROC1;PROC2:processbegincounter := counter - 1;wait;

end process PROC2;end architecture shared_variables_arch;



RTL2.7

Message

Dynamic slice is not supported

Default Severity

Warning

Description

The left and right bounds of the part range cannot be evaluated to constant values. Suchexpressions are not supported by synthesis tools and are ignored.

Example

In the following example, the dynamic slice in line 14 is not supported:Library IEEE;use IEEE.std_logic_1164.all;Entity TEST is

Port (Sdq_data : out std_logic_vector (7 downto 0));

End TEST;Architecture ARCH_TEST of TEST isType vect_array is array (7 downto 0) of std_logic_vector (7 downto 0);Signal data : vect_array;BeginProcessVariable I : integer;BeginSdq_data (I+7 downto I) <= data (I) (7 downto 0);

End process;End ARCH_TEST;



RTL2.8

Message

’BUS’ and ’REGISTER’ signal type are not supported for synthesis

Default Severity

Warning

Description

The BUS and REGISTER signal type are not supported by the synthesis tools and are ignored.

Example

In the following example, the bus signal type in line 5 is not supported:entity EG1 is

port (a: in BIT; z: out bit);end;architecture RTL of EG1 issignal sig1: bit bus;begin

processbeginif a = ’1’ then z <= ’1’;else z<= ’0’;end if;

end process;end;



RTL2.9

Message

Guarded assignment requires GUARD signal

Default Severity

Error

Description

The GUARD signal is not declared for guarded assignment.

Example

In the following example, the guarded signal is not declared for line 9’s guarded assignment:entity EG1 is

port (a,b: in bit; z: out bit);end;architecture RTL of EG1 issignal val: bit;begin

guarded_block: blockbeginval <= guarded a and b;

end block;z <= val;

end;



RTL2.10

Message

GUARD is not declared

Default Severity

Error

Description

The GUARD signal is not declared.

Example

In the following example, the guard signal in line 8 is not declared:entity EG1 is

port (a,b: in bit; z: out bit);end;architecture RTL of EG1 isbegin

guarded_block: block --(a = ’1’)beginz <= ’1’ when guard else ’0’;

end block;end;



RTL2.11

Message

Implicitly declared GUARD signal cannot be updated

Default Severity

Error

Description

The implicitly declared GUARD signal cannot be updated. The implicit guard signal will bedeclared for a guarded block. This is illegal to update the implicitly declared GUARD signal.

Example

In the following example, the guard signal in in line 8 is illegal:entity EG1 is


guarded_block: block (a = ’1’)beginguard <= (b= ’1’);z <= ’1’ when guard else ’0’;

end block;end;



RTL2.12

Message

Illegal redeclaration of GUARD signal

Default Severity

Error

Description

The redeclaration of GUARD signal is illegal. The implicit GUARD signal will be declared for aguarded block. It is illegal to redeclare GUARD signal.

Example

In the following example, the guard signal in in line 7 is illegal:entity EG1 is


guarded_block: block (a = ’1’)signal guard : boolean;beginz <= ’1’ when guard else ’0’;

end block;end;



RTL2.13

Message

Undriven pin is detected

Default Severity

Warning

Description

Undriven pin(s) are detected in the design.

Example

In the following example, pin in1 of instance test is undriven (see line 4):module top (din1, dout1);output dout1;input din1;test t1(.in2(din1),.out1(dout1));endmodulemodule test(in1,in2, out1);input in1, in2;output out1;assign out1 = in1 & in2;

endmodule



RTL3.1

Message

Variable/signal is unassigned in asynchronous set/reset

Default Severity

Warning

Description

The design includes one or more variables or signals that are unassigned in one of theconditional branches in asynchronous set/reset branches.

Example

In the following example, the design assigns output out0 in the else branch, but not in theif branch of the asynchronous set/reset. See line 11 (in bold).

module SEN (clk,rst,in0,out0,out1);input clk,rst,in0;output out0,out1;reg out0,out1;always @ ( posedge rst or posedge clk )beginif (rst) beginout1 <= 1'b0;

endelse beginout0 <= in0;out1 <= !in0;

endend

endmodule



RTL3.2

Message

Assignment of X is in asynchronous set/reset branch

Default Severity

Warning

Description

The design includes one or more X value assignments in asynchronous set/reset branches.

Example

In the following example, the design assigns X value to out0. See line 8 (in bold).

module OPW (clk,rst,in0,out0);input clk,rst,in0;output out0;reg out0;always @ ( posedge rst or posedge clk )beginif (rst) beginout0 <= 1'bx;

endelse beginout0 <= in0;

endend

endmodule



RTL3.3

Message

Non-constant value assignment is in asynchronous set/reset value

Default Severity

Warning

Description

The design includes one or more non-constant value assignments in asynchronous set/resetbranches.

Example

In the following example, the design assigns a non-constant value to out0. See line 8 (inbold).

module OPW (clk,rst,in0,in1,out0);input clk,rst,in0,in1;output out0;reg out0;always @ ( posedge rst or posedge clk )beginif (rst) beginout0 <= in1;

endelse beginout0 <= in0;

endend

endmodule



RTL3.4

Message

DFF/DLAT is with both asynchronous set and reset connections

Default Severity

Warning

Description

The design includes one or more DFFs or DLATs that have both asynchronous set and resetconnections.

Example

On line 8 of the following example, the design uses rst for an asynchronous reset. Thedesign then uses set for an asynchronous set on line 10.

module test (clk,set,rst,in0,in1,out0);input clk,set,rst,in0,in1;output out0;reg out0;always @ ( posedge rst or posedge set orposedge clk )beginif (rst)out0 <= 1'b0;

else if (set)out0 <= 1'b1;

elseout0 <= in0;

endendmodule



RTL3.5

Message

Variable/signal is assigned without using asynchronous set/reset

Default Severity

Ignore

Description

Design style check to report if the RTL codes infer to a DFF gate that does not use anyasynchronous set or reset signal.

Example

On line 6 of the following example, the design assigns output out0without any asynchronousset or reset signal:

module SEN (clk,rst,in0,out0);input clk,rst,in0;output out0;reg out0;always @(posedge clk)out0 <= in0;

...endmodule



RTL4.1

Message

Enum encoding is applied to enum type

Default Severity

Note

Description

The design includes one or more ENUM_ENCODING attributes to declare enum type in VHDL.For Verilog, use the synopsys enum directive to declare enum type.

Example

On line 14 of the following example, the design includes an ENUM_ENCODING attribute todeclare enum type:

PACKAGE small_1164 ISattribute ENUM_ENCODING : string;

TYPE std_ulogic IS ( 'U', -- Uninitialized'X', -- Forcing Unknown'0', -- Forcing 0'1', -- Forcing 1'Z', -- High Impedance'W', -- Weak Unknown'L', -- Weak 0'H', -- Weak 1'-' -- Don't care

);attribute ENUM_ENCODING of std_ulogic : type is “U D 0 1 Z D 0 1 D”;

end package;



RTL4.2

Message

Multiple wait statements. FSM encoding might be different

Default Severity

Warning

Description

The design includes one or more always/process blocks containing multiple wait statements.The checker creates a Finite State Machine (FSM) when it encounters multiple waitstatements. We recommend that you verify that the FSM encoding is what you expected.

Example

On lines 8 and 12 of the following example, the design uses the wait statement:

Module Medge (Clock, Cond, In1, In2, In3, Out1);input Clock, Cond, In1, In2, In3;output Out1;reg Out1;

alwaysbegin@ (posedge Clock);Out1 = In1;if (Cond)begin@ (posedge Clock);Out1 = In2;

endelsebegin@ (posedge Clock);Out1 = In3;

endend

endmodule



RTL4.3

Message

Enum value size is different than the declared data type

Default Severity

Warning

Description

The enum value size is different than the declared data type.

Example

The declared type ‘light’ size is 2, but the enum value GREEN size is 3:

module enum10(input clk,output reg out1);typedef enum reg signed [1:0] { RED = 2'sb10,YELLOW,GREEN = 3'b000} light;light mylight;always @(clk)beginmylight=RED;out1 = mylight;

endendmodule



RTL4.4

Message

Encoding format has too many values

Default Severity

Warning

Description

There are more encoding values than necessary.

Example

In line 3, there are more encoding values than are needed:

attribute ENUM_ENCODING : string;type fifo_valid_state_type is (full1, full2, full3, empty);attribute ENUM_ENCODING of fifo_valid_state_type : type is "0001 0011 0010 00000100 0101 0111 0110 1110";



RTL5.1

Message

Overlapped case items are in parallel case statement

Default Severity

Warning

Description

The design includes multiple case_items that potentially match the case_expressions inparallel case statements.

A parallel case statement syntax:

case (case_expression) //synopsys Parallel_case case_item1 ://case_item_statement1;case_item2 : case_item_statement2;default : case_item_statement3;endcase

Example

On lines 8 and 9 of the following example, case_items 2'b1? and 2'b?1 match thecase_expression sel when sel is equal to 2'b11.

module test ( a, b, sel, out0);input a, b;input [1:0] sel;output out0;reg out0;always @(sel or a or b) begincasez (sel) //synopsys parallel_case2'b1? : out0 = a;2'b?1 : out0 = b;default: out0 = 1'bx;

endcaseend

endmodule



RTL5.2

Message

Non-binary case items are in case statement

Default Severity

Warning

Description

The design includes one or more case_items with non-binary values in case statements.

A case statement syntax:

case (case_expression)case_item1 : case_item_statement1;case_item2 : case_item_statement2;default : case_item_statement3;

endcase

Example

In the following example, the design includes a Z value for a case_item. See line 9 (in bold).

module test ( a, b, c, sel, out0);input a, b, c;input sel;output out0;reg out0;always @(sel or a or b or c) begincase(sel)1'b1 : out0 = a;1'bz : out0 = b;default: out0 = c;

endcaseend

endmodule



RTL5.3

Message

Case expressions/items are resized

Default Severity

Warning

Description

The design includes one or more case item sizes that do not match the case expression sizes.

Example

On lines 8 and 10 of the following example, the case items have a single bit, while the caseexpression (line 3) is a 2-bit vector.

module test ( a, b, c, sel, out0);input a, b, c;input [1:0] sel;output out0;reg out0;always @(sel or a or b or c) begincase(sel)1’b1 :out0 = a;

1’b0 :out0 = b;

default:out0 = c;

endcaseend

endmodule



RTL5.4

MessagePartial case items are in full case statement

Default Severity

Note

Description

The design includes a partial case enumeration in a full case statement.

Example

The following example contains a potential partial case enumeration. The 4’b00 and 4’11case items are not enumerated in the full_case statement(in bold).

module test (out, a, b, select);output out;input a, b;

input [1:0] select;reg out;

always @(select or a or b) begincasez (select) /* full_case */

4’b01: out = a;4’b10: out = b;

endcaseendendmodule



RTL6.1

Message

X created due to the assignment of value X

Default Severity

Warning

Description

One or more assignments use value X. The checker generates a don’t care for any value Xassignment.

Example

In the following example, the design assigns a 1'bx value to output o. See line 6 (in bold).

module test(o,i);output o;reg o;input i;alwayso = 1'bx;endmodule



RTL6.2

Message

Integer value range constraint is added

Default Severity

Warning

Description

When you read in the design, you specified a constraint on integers for a specific range. Theswitch of the command that you used to apply the constraint is -rangeconstraint.

Example

In the following example, integer int1 has a value range from -1024 to 1024 (see line 4).

ENTITY test ISPORT (

clk : IN std_ulogic ;int1 : IN integer range -1024 to 1024 ;bufferA : BUFFER std_ulogic);

END test;ARCHITECTURE arc OF test ISBEGIN

PROCESSBEGIN

IF clk = '1' AND clk'event THENIF int1 = 4095 THENbufferA <= '0' ;ELSEbufferA <= '1' ;END IF ;

END IF ;END PROCESS;

END;

Input:

SETUP>read design test.vhdl -vhdl -rangeconstraint



RTL6.3

Message

X created when divisor equals to zero

Default Severity

Warning

Description

The design contains one or more divisors that are signals or variables, and not constants.Thus, there is a chance that they will equal zero. In these cases, the checker creates X.

Example

In the following example, the divisor B is an input signal, thus the checker creates X (see line4).

module test(A, B, QUOTIENT);input [7:0] A, B;output [7:0] QUOTIENT;assign QUOTIENT = A / B;endmodule



RTL6.4

Message

Enum value constraint is added

Default Severity

Warning

Description

The checker recognized the synopsys enum fsm_state directive, thus it added aconstraint to Enum value.

Example

In the following example, on lines 3 through 9 (in bold), the checker constrains enum statesra_state and next_state to a one-hot condition.

module test (masterclk, reset_n, mem_write);…parameter [4:0] // synopsys enum fsm_statesiddle = 5’b00001,step01 = 5’b00010,step02 = 5’b00100,step03 = 5’b01000,step04 = 5’b10000,reg [4:0] /* synopsys enum fsm_states */ ra_state, next_state;

always @(ra_state or mem_write) begincase (ra_state)

iddle: begintmp = mem_write;next_state = step01;end

step01: begintmp = 1’b0;next_state = step02;end

…default: begin

tmp = mem_write;next_state = iddle;end

endcaseend…endmodule



RTL6.5

Message

priority if and unique if statements are incomplete

Default Severity

Warning

Description

There are incomplete priority if and unique if SystemVerilog statements. Thepriority if and unique if SystemVerilog statements ensure that all conditions arecomplete; they ensure that default else statements exist and if/else if conditions cover allconditions.

Example

In the following example, the incomplete priority if statement in line 4 triggers this rulecheck, while the complete priority if statement in lines 11-12 do not trigger this rulecheck.

module test1(input aa, output oo);reg oo;always @* begin

priority if (aa) oo = !aa; // incomplete conditionendendmodule

module test2(input aa, output oo);reg oo;always @* begin

priority if (aa) oo = !aa;else oo = aa; // complete condition

endendmodule



RTL6.6

Message

unique if statements have redundant or overlapping conditions

Default Severity

Note

Description

There are possible redundant or overlapping conditions in unique if statements. Structuralchecks generate this message; a more detailed analysis is done during compare.

Example

In the following example, there are overlapping conditions in the unique if statement thatwill cause a rule check report. See line 5.

module test3(input aa, bb, output oo);reg oo;always @* beginunique if (aa && bb) oo = !aa;else if (aa || bb) oo = aa;else oo = 1’b0;

endendmodule



RTL7.1

Message

Design includes comparison that uses X or Z values

Default Severity

Warning

Description

The design includes one or more comparisons that use X or Z values as comparators.

Example

In the following example, the design compares reset rst with an X value. See line 7 (in bold).

module test (clk,rst,in0,out0);input clk,rst,in0;output out0;reg out0;always @ ( posedge clk )beginif (rst == 1'bx)out0 <= 1'b0;

elseout0 <= in0;

endendmodule



RTL7.2

Message

Gate or transistor primitive is using weak attributes

Default Severity

Warning

Description

One or more gates or transistor primitives are using weak attributes.

Note: Not all weak attributes will be used. In the case of a multiple-driven net, the gate withthe strong attribute will drive the output.

Example

In the following example, the design uses a weak attribute for a buffer primitive. See line 5 (inbold).

module test (clk,rst,in0,out0);input clk,rst,in0;output out0;wire out0;buf (weak0, weak1) (out0, in0);endmodule



RTL7.3

Message

Array index in RHS might be out of range

Default Severity

Warning

Description

The design includes an index where its right hand side might be out of range.

Example

In the following example, it uses an index where its right hand side might be out of range. Seeline 10(in bold).

module test (clk, idx, in0, out0);input clk;input [3:0] idx;input [3:0] in0;output out0;reg out0;

always @ ( posedge clk)beginout0 <= in0[idx];

endendmodule



RTL7.4

Message

Array index in LHS might be out of range

Default Severity

Warning

Description

The design includes an index where its left hand side might be out of range.

Example

In the following example, it uses an index where its left hand side might be out of range. Seeline 10(in bold).

module test (clk, idx, in0, out0);input clk;input [3:0] idx;input in0;output [3:0] out0;reg [3:0] out0;

always @ ( posedge clk)beginout0[idx] <= in0;

endendmodule



RTL7.5

Message

Input signal is assigned by logic values

Default Severity

Warning

Description

The design includes one or more primary input signals that are assigned by logic values.

Example

In the following example, the design assigns logic value 1 to primary input a. See line 4 (inbold).

module test(a, b);input a;output b;assign a = 1'b1;assign b = 1'b1;endmodule



RTL7.6

Message

Value X or Z is treated as 0 in unary/binary expressions

Default Severity

Warning

Description

The checker treats the 1’bx or 1’bz in unary/binary expression as 1’b0.

Example

In the following example, on line 7 (in bold), the 1’bx value in the conditional expression istreated as 1’b0. Thus, input in2 will be assigned directly to output out.

module test(in1, in2, out);input in1, in2;output out;reg out;

always beginout = 1’bx ? in1 : in2;

endendmodule



RTL7.7

Message

Real number rounded to integer value

Default Severity

Warning

Description

The checker rounds real numbers to integer values.

Example

In the following example, on line 2 (in bold), input din has a real value of 2.2. However, thechecker truncates this value at .2.

module test (din, dout);input [2.2:0] din;output [2:0] dout;

assign dout = din;endmodule



RTL7.8

Message

Overflowed integer is truncated

Default Severity

Warning

Description

The design contains one or more integers that overflow. Thus, the checker truncates them.

Example

In the following example, the checker truncates integer b;. See line 3.

module test (b);output b;integer b;

always

b = 5147483648;endmodule



RTL7.9

Message

Sign overflowed integer is truncated

Default Severity

Warning

Description

The design contains one or more integers that overflow at the sign bit. Thus, the checkertruncates them.

Example

In the following example, the checker truncates integer b;. See line 3 (in bold).

module test (b);output b;integer b;

alwaysb = 2147483648;

endmodule



RTL7.10

Message

Comparison with signed and unsigned operands

Default Severity

Warning

Description

The design includes both signed and unsigned operands used in a relational expression.

Example

In the following example, the checker compares the signed operand in1 (on line 4) to theunsigned operand in2 (on line 5). The checker converts in1 to an unsigned operand first,and then compares it with in2. An unsigned comparison results.

module test (out0, in1, in2);

output out0;input signed [31:0] in1;input unsigned [31:0] in2;

assign out0 = in1 > in2;

endmodule



RTL7.11

Message

Implicit signed expression is converted to unsigned

Default Severity

Warning

Description

The design includes a signed expression that the checker has converted to an unsignedexpression implicitly.

Example

In the following example, the checker converts the signed operand in1 to unsigned in theconditional expression. See line 7 (in bold).

module test (out0, cond1, in1);

output unsigned [32:0] out0;input cond1;input signed [31:0] in1;

assign out0 = cond1 ? out0 : in1;endmodule



RTL7.12

Message

Unsized integer number is truncated to 32 bits

Default Severity

Warning

Description

The checker truncated an unsized integer literal to 32-bit.

Example

In the following example, the checker truncates ’hf00000000 to h00000000. See line 2.

module test6(input aa, output oo);assign oo = (’hf00000000 > 32’h0)?aa:!aa;



RTL7.13

Message

Logical operator is applied to multiple-bit operand

Default Severity

Warning

Description

The logical operator is applied to multiple-bit operand when the operand is not a single-bitexpression.

Example

In the following example, the logical operator && is applied to multiple-bit operand tmp (seeline 5):

module test(in, out);input in;output out;wire [2:0] tmp;assign out = in && tmp;endmodule



RTL7.14

Message

Loop exceeds maximum iterations

Default Severity

Warning

Description

An index variable should be sufficiently large enough to hold both the initial and the finalvalues that the loop index could take. If the index variable is small, the loop will be executedfewer number of times. This can lead to unpredictable behavior.

.Example

In the following example, ’I’ can only take values from 0 to 3 as its size 2 bits. Line 8 of thecode shows that the index of the for loop ranges from 0 to 5. Since the loop index variable ’I’is not large enough to hold the final value of the loop index, the loop may never terminate.module neg_BITUSD_loop_idx_bitsel(a, b, c);input [3:0] a, b;output [3:0] c;reg [3:0] c;always @(a or b)begin: Preg [1:0] I;for (I = 2; I <= 5; I = I + 1)begin: loop2c[I] = a[I] | b[I];

endend

endmodule



RTL7.15

Message

Null slice is not supported

Default Severity

Warning

Description

The specified datatype or node is defined with a null range, and it cannot hold any value. InVHDL, a range is considered to be a null range, if the subset of values specified by the rangeis empty (a decreasing range with a ’to’ direction, or an increasing range with a ’downto’direction). Examples of null range are (3 to 0) and (1 downto 8). The synthesis tools do notsupport null range.

Example

In the following example, the null slice in line 9 is not supported:entity TEST1 is

port (in1: in integer ;out2: buffer bit;out3: out bit) ;

end TEST1 ;architecture ARCH_TEST1 of TEST1 istype myvector is array(0 downto 7) of BIT;beginprocess (in1)variable vec: myvector;variable index: integer;variable temp: bit;begin

vec:= (’1’, ’1’, ’1’, ’1’, ’1’, ’1’, ’1’, ’1’) ;temp:= vec(in1);

end process;end ARCH_TEST1 ;



RTL7.16

Message

Variable index is out of the defined range

Default Severity

Warning

Description

A bit or part select reference in an expression is found to have an index specification outsideof the defined range of the variable. This can lead to unexpected simulation or synthesisresults. Cadence recommends that you change the reference so that the index or subrangefalls within the valid range.

Example

In the following example, index [4] is out of a’s range (see line 7):module test1 (a, b, out1);input [3:0] a;input [3:0] b;output out1;reg out1;always @(a or b)

out1 = a[4] & b[3];endmodule



RTL7.17

Message

Exponentiation operator is unsupported

Default Severity

Warning

Description

Some synthesis tools do not support the exponentiation operator. Cadence recommends thatyou remodel your HDL source code.

Example

In the following example, a ** 5 (line 14) is not supported:Library IEEE;use IEEE.std_logic_1164.all;use IEEE.std_logic_arith.all;

entity TEST1 isport (

a : in INTEGER;out1 : out INTEGER

) ;end TEST1 ;architecture ARCH_TEST1 of TEST1 isbeginprocess (a)beginout1 <= a ** 5;

end process;end ARCH_TEST1 ;



RTL7.18

Message

Argument size to integer type conversion is too large

Default Severity

Warning

Description

The argument width is too large for conversion ’CONV_INTEGER’. The maximum argumentwidth is 32 for a ’signed’ argument or 31 for an ’unsigned’ argument.

The Logical Equivalency Checker does truncations for the following:

■ unsigned (31 bits) conversion to integer

■ signed (32 bits) conversion to integer

Example

In the following example, on line 10, the argument for ’conv_integer’ is 32 bit width’unsigned’, is too large (maximum if 31 for an ‘unsigned’ argument).library ieee;use ieee.std_logic_1164.all;use ieee.std_logic_arith.all;entity IntCtrl isport( IRQ : out integer;

IntCtrlReg_th : in std_logic_vector(31 downto 0));end IntCtrl;architecture rtl of IntCtrl isbeginIRQ <= conv_integer(unsigned(IntCtrlReg_th));

end rtl;



RTL7.19

Message

Added constraint on integer overflow for arithmetic operation ADD/SUB

Default Severity

Warning

Description

A constraint is added on the integer overflow for the ADD or SUB arithmetic operation.

Example

In the following example, in line 11, if (CONV_INTEGER(a) + b) > 2**31-1 (overflow),the software can derive a constraint on this overflow, and then compare can ignore thedifferent interpretation synthesis tool made when (CONV_INTEGER(a) + b) > 2**31-1occurs.LIBRARY IEEE;USE IEEE.std_logic_1164.ALL;USE IEEE.STD_LOGIC_ARITH.ALL;USE IEEE.STD_LOGIC_UNSIGNED.ALL;ENTITY test ISPORT ( a, b : IN natural;

z : OUT integer );END test;ARCHITECTURE rtl OF test ISBEGIN

z <= CONV_INTEGER(a) + b ;END rtl;



RTL7.20

Message

Size value in size’(expr) casting is too large

Default Severity

Error

Description

The size value in size’(expr) casting is too large. Use a positive integer value as the sizevalue.

Example

In the following example, the size ’hffffffff’ in line 4 is too large:module test(in, out);input in;output out;assign out = ’hffffffff’(in);endmodule;



RTL7.21

Message

Real variables are not supported

Default Severity

Warning

Description

Real variables are not supported in synthesis models. They are converted to 32-bit integerswhen encountered in the static verification tool flows.

Example

In the following example, r1 (line 5) is not supported:module real_in_cmp (b, out1);input [1:0] b;output out1;reg out1;real r1;always @(b)r1 = b;endmodule



RTL8.1

Message

Multiple multipliers/dividers are in module/entity

Default Severity

Note

Description

One or more modules or entities have multiple multipliers or dividers.

Example

In the following example, the design uses two multipliers in module test. See line 4 (inbold).

module test (a, b, c, q);input [3:0] a, b, c;output [11:0] q;assign q = a * b * c;endmodule



RTL8.2

Message

Latch(es) are inferred due to an incomplete conditional statement

Default Severity

Note

Description

The checker has inferred one or more latches. The checker infers a latch when it finds anincomplete conditional statement.

Example

In the following example, the checker infers latch out0 so that output out0 will retain itsprevious value when the clk = 1'b0, the missing condition. See line 8 (in bold).

module test (clk,rst,in0,out0);input clk,rst,in0;output out0;reg out0;always @ ( clk or in0 )beginif (clk)out0 = in0;

endendmodule



RTL8.3

Message

Unreachable DFF/DLAT is removed

Default Severity

Warning

Description

The design includes one or more DFFs or DLATs that are unreachable. Unreachable registersare those registers that do not propagate to any observable point (for example, spare flops).

By default, the checker removes all unreachable DFFs and DLATs that are local to a module.

If you want to keep the unreachable DFFs and DLATs, use the READ DESIGN command’s-keep_unreach option. For example:

read design test.vhdl -vhdl -keep_unreach

Example

In the following example, the output of register out1[1] does not propagate to anyobservable point. See line 9 (in bold).

module TEST (clk,in1,in2,out0);input clk,in1,in2;output out0;reg out0;reg[1:0] out1;always @ ( posedge clk )beginout0 <= in1;out1[1] <= in2;

endendmodule



RTL8.4

Message

Unreachable DFF/DLAT is kept

Default Severity

Warning

Description

The design includes one or more DFFs or DLATs that are unreachable. Unreachable registersare those registers that do not propagate to any observable point (for example, spare flops).

By default, the checker removes all unreachable DFFs and DLATs that are local to a module.You will receive this message if you use the READ DESIGN command’s -keep_unreachoption. For example:

read design test.vhdl -vhdl -keep_unreach

Example

In the following example, on line 9, DFF out1[1] is unreachable:

module TEST (clk,in1,in2,out0);input clk,in1,in2;output out0;reg out0;reg[1:0] out1;always @ ( posedge clk )beginout0 <= in1;out1[1] <= in2;

endendmodule



RTL8.5

Message

Implicit signed multiplier is detected in module/entity

Default Severity

Note

Description

The checker detected (and recognized) the Verilog signed multiplier coding style that useseither sign-extension or subtraction.

Example

In the following example, on lines 5, a signed multiplier is created using sign-extension codingstyle:

module test( in1, in2, out);//using sign-extensioninput [21:0] in1;input [13:0] in2;output [34:0] out;assign out= {{21{in2[13]}}, in2[13:0]} * {{13{in1[21]}}, in1[21:0]};endmodule



RTL9.1

Message

Instance inout/output port has dynamic indexing. Treated as floating

Default Severity

Warning

Description

The design includes one or more instance inout/output ports with dynamic indexing. Dynamicindexing is a non-synthesizable coding style. As a result, the checker creates floating signalsfor all inout/outputs.

Example

In the following example, only one of the two-bit outputs out0 is dynamically selected by inputin2. See line 12 (in bold).

module SUB (in2, out3);input in2;output out3;assign out3 = in2;endmodule

module TEST (in0,in1,in2,out0);input [1:0] in0;input in1,in2;output [1:0] out0;reg [1:0] out0;SUB inst1 (.in2(in0[in1]),.out3(out0[in2]));

endmodule



RTL9.2

Message

Design has irregularly used inout/output expression

Default Severity

Warning

Description

The design includes one or more irregularly used inout/output expressions.

Example

In the following example, inout port inout3 is tied to 0 logic value. See line 13 (in bold).

module SUB (in2, inout3);input in2;inout inout3;wire inout3;assign inout3 = in2;

endmodule

module TEST (in0,in1,in2,out0);input [1:0] in0;input in1,in2;output [1:0] out0;reg [1:0] out0;SUB inst1 (.in2(in0[in1]),.inout3(1'b0));

endmodule



RTL9.3

Message

Supply0/supply1 is converted into a wire

Default Severity

Warning

Description

The supply0 or supply1 net is converted into a wire.

Example

In the following example, supply0 net in2 is converted to a wire.

module test (in, out);input in;output out;supply0 in2;assign out = in & in2;endmodule



RTL9.4

Message

Supply0/supply1 net is not a module port

Default Severity

Warning

Description

The supply0 or supply1 net is not a module port.

Example

In the following example, supply0 net in2 is not a module port (see line 4):

module test (in, out);input in;output out;supply0 in2;assign out = in & in2;endmodule



RTL9.5

Message

Power pin is converted to an input pin

Default Severity

Warning

Description

A power pin is converted to an input pin.

Example

In the following example, when running the following Conformal commands:set power pin -input vss vdd

read des test.v -fix_power_pin

the vss and vdd pins are changed from inout to input pins.

input in;output out;inout vss, vdd; // changed to input pinssupply0 vss;supply1 vdd;

assign out = !in;endmodule



RTL9.7

Message

Cannot read value from OUT port

Default Severity

Error

Description

A feedback loop has been detected through the asynchronous set or resets of flip-flop(s) andthe listed signals, wires, or expressions.

Example

In the following example, dout (line 5) is the outport. Attempting to read from doutwill causean error:library ieee;use ieee.std_logic_1164.all;Entity dff isport (clk: in std_logic;

reset: in std_logic;din: in std_logic;dout: out std_logic);

end dff;Architecture behave of dff issignal reset_cond: std_logic;beginreset_cond <= dout or reset; <b>process (clk,din,reset_cond)beginif reset_cond = ’1’ then

dout <= ’0’;elsif clk’event and clk = ’1’ then

dout <= din;end ifend process;end behave;



RTL9.8

Message

Set Liberty pin direction to output because it has an output function

Default Severity

Warning

Description

This rule check sets the pin direction from the Liberty library to an output because it has anoutput function.

Example

In the following example, in line 9, the direction of pin Y is set to an output because it has anoutput function:library(test) {cell (AND2X2) {pin(A) {direction : input;

}pin(B) {direction : input;

}pin(Y) {function : "(A B)";

}}}



RTL9.9

Message

Extra ’;’ is detected in port list

Default Severity

Warning

Description

This rule check indicates that there is an extra semi-colon (;) after the last port in the port list.

Example

In the following example, in line 3, there is an extra semi-colon (;) after bit:

entity e isport(q : out bit;d : in bit;);

end;architecture a of e is+beginq <= d;

end;



RTL9.10

Message

Liberty cell does not use any input pin

Default Severity

Warning

Description

Indicates that the Liberty cell does not use any input pin.

Example

In the following example, in line 11, no input pin is used in the output function.

library(test) {cell (AND2X2) {pin(A) {direction : input;

}pin(B) {direction : input;

}pin(Y) {direction : output;function: "(1)";

}}}



RTL9.11

Message

Liberty Master-Slave DFF cell clock phase does not match the timing table

Default Severity

Warning

Description

Indicates that the liberty cell is a master-slave flip flop, but its clock phase does not match withthe timing table.

Example

In the following example, the master-slave flip-flop is triggered by clocked_on_also :!phi, but a timing_type of rising edge is used in pin q. This causes a phase mismatch.cell (DFFDDRX8) {...pin (resetb) {direction : input;capacitance : 0.00563;min_pulse_width_low : 0.33680;

}pin (q) {function : "IQ" ;direction : output;max_fanout : 7.8535;timing() {related_pin : "phi";timing_type : rising_edge ;...

}}

ff (IQ,IQN) {clocked_on : phi ;clocked_on_also : !phi ;clear : !resetb ;next_state : "(!phi * dp) + (phi * dn)" ;

}}



RTL9.12

Message

Liberty cell with internal_node does not have correct statetable

Default Severity

Warning

Description

Indicates that there is an internal_node in the liberty cell, but the corresponding statetableis missing or a corresponding pin of the internal_node name is not found in the cell.

Example

In the correct liberty file, if the internal_node attribute exists, there should be acorresponding statetable group as following:

statetable("in1", "ires"){...}

but there is no statetable in the cell in the following example:

cell(test){pin (in1) {direction: input;}pin (ires) {direction: internal;internal_node: "ires"}pin (out1) {direction: output;function: "in1 in2";}

}



RTL9.13

Message

Set liberty cell to blackbox because some of its output pins have no function

Default Severity

Warning

Description

Indicates that some of the liberty cell’s output pin has no function attribute in it, but sometiming table exist in the output pin. Then the liberty cell is set to be a blackbox.

Example

In the following example, if line 3 is removed, the cell would be marked as a blackbox.

pin (out2) {direction: output;function: "!in1";timing(){...}

}



RTL9.14

Message

Liberty cell has duplicate signal (pin/member)

Default Severity

Error

Description

Indicates that there are duplicated signals in a bundle declaration of the Liberty cell.

Example

In the following example, the bundle (z) has duplicated members z01:

cell(zhdp_mpt2) {bundle(r) {

members(r0, r1);direction : input;capacitance : 0.003750;fanout_load : 0.188;min_pulse_width_high : 0.056;

}bundle(z) {

members(z01, z01); /* ERROR: z01 is duplicated *direction : inout;capacitance : 0.005625000;

}} /* cell(zhdp_mpt2) */



RTL10

Message

Both posedge and negedge are used in different always/process

Default Severity

Warning

Description

Both the posedge and negedge of a clock are used in different always/process blocks.

Example

On line 5 of the following example, the design uses the posedge clock in an always block.And on line 9, the design uses the negedge clock in another always block.

module SEN (clk,rst,in0,out0,out1);input clk,rst,in0;output out0,out1;reg out0,out1;always @ ( posedge clk )beginout0 <= in0;

endalways @ ( negedge clk )beginout1 <= !in0;

endendmodule



RTL11

Message

Incomplete condition is in a function/procedure/task block

Default Severity

Warning

Description

The design includes one or more incomplete conditional statements within functions,procedures, or task blocks.

Examples

■ In the following example, the if statement is missing its else branch. See line 8 (inbold).

module TER (clk,rst,in0,out0);input clk,rst,in0;output out0;wire out0;assign out0 = func1 (in0,rst);function func1;input in0, rst;if (rst)func1 = in0;

endfunctionendmodule

■ Incomplete conditional statements might lead to false positive result under certaincircumstance and should be carefully examined.

In the following example, the variable parameter type output in the subprogram might getan ambiguous value because of the incomplete conditional statements. In this testcase,nxt_state is associated with a variable parameter of mode OUT in procedurenext_state. Inside the procedure, when x = 3, there is no assignment to z. In this case,nxt_state does not hold its original value of 3 after calling procedure next_state.Instead, it gets a value 0 (in bold).

library ieee;use ieee.std_logic_1164.all;

entity test isprocedure next_state(x: in integer range 0 to 3;

z: out integer range 0 to 3) is



begincase x iswhen 1 => z := 1;when 2 => z := 2;when others => NULL;

end case;end next_state;

end test;

architecture rtl of test isbegin

processvariable cur_state: integer range 0 to 3;variable nxt_state : integer range 0 to 3;

begincur_state := 3;nxt_state := 3;next_state(cur_state, nxt_state);

end process;end rtl;



RTL12

Message

Referenced variable(s)/signal(s) are not in sensitivity list

Default Severity

Warning

Description

The design includes one or more variables or signals that are referenced but not included insensitivity lists.

Example

On line 7 of the following example, the design references variable in2, which is not includedin the sensitivity list on line 5.

module SEN (in0,in1,in2,out0);input in0,in1,in2;output out0;reg out0;always @ ( in0 or in1 )beginout0 = in0 | in1 | in2;

endendmodule



RTL12.1

Message

Constant object is in sensitivity list

Default Severity

Warning

Description

There is a constant object in the sensitivity list.

Example

In the following example, val is a constant (see line 6):

module SEN (in0,out0);input in0;output out0;parameter val = 1;reg out0;always @ ( in0 or val )beginout0 = in0 ;

endendmodule



RTL13

Message

For loop condition is always false

Default Severity

Warning

Description

The design includes one or more for loops that will never hold true.

Example

On line 7 of the following example, the variable i is initialized with a value of 2 (i=2). Thus,this for loop will never hold true, since i will never be less than a value of 1 (i<1).

module test(out,in);output [3:0] out;reg [3:0] out;input [3:0] in;integer i;always beginfor (i=2; i<1; i=i+1) begin

out = i;endout = in;

endendmodule



RTL13.1

Message

The FOR-LOOP index should not be assigned within the loop itself

Default Severity

Warning

Description

The FOR-LOOP index cannot be assigned within the loop.

Example

In the following example, i is the FOR-LOOP index and it is assigned within the loop (see line8):

module top(input [1:0] in, output [4:0] out);sum sum1(in,out);endmodulemodule sum(input [1:0] a, output [4:0]result);integer i;always beginfor (i=0; i<3; i=i+1) begini = a;

endend

endmodule



RTL13.2

Message

The evaluation of for-loop condition is not constant

Default Severity

Warning

Description

The Conformal software detected a non-static loop. As per synthesis semantics, a loop in anHDL design must be statically unrollable—that is, the number of loop iterations should bestatically known.

Example

In the following example, N is not a constant (see line 9):module neg_NSLOOP (a, b, c);input [1000:0] a, b;output [1000:0] c;reg [1000:0] c;integer N;always @(a or b)begin: Pinteger I;for (I = 0; I < N; I = I + 1)c[I] = a[I] & b[I];

endendmodule



RTL14

Message

Signal with fanin drive and no fanout load is detected

Default Severity

Warning

Description

The checker has removed one or more floating signals. This situation occurs when the outputof a logic cone has no fan-out loads. In other words, the signal is driven by a gate or input port(has drives), but its output does not drive any gate or output port (has no loads).

Example

On line 5 of the following example, flt does not have any fan-out loads, so the checkerissues the RTL14 warning.

module test(aa, bb, o1, o2);input aa, bb;output o1, o2;wire flt;assign flt = aa != bb;assign o1 = aa == bb;endmodule



RTL14.1

Message

Fanout load of the signal is removed

Default Severity

Warning

Description

Indicates that the fanout load of a signal is removed, and therefore the signal becomes afloating signal, which is also removed.

Example

In the following example, bb (on line 5) has fanout load at line 4, but this fanout is removedbecause aa has RTL14 violation. The RTL14.1 rule checker reports that the fanout load of bbis removed, and therefore bb becomes a floating signal, which is also removed.module test(oo);output oo;wire aa, bb, cc;assign aa = !bb; // RTL14 rule violationassign bb = !cc; // RTL14.1 rule violation

endmodule



RTL15

MessageClock and asynchronous set/reset expression must be one bit wide

Default Severity

Error

Description

A clock variable or an asynchronous set/reset variable in the sensitivity list is more than one-bit wide.

Example

On line 1 of the following example, myReset is declared as a two-bit wide. On line 2, anRTL15 error is reported because myReSet is not a single-bit and it is used as anasynchrounous set/reset variable on the sensitivity list.

reg [1:0] myReset; // myReset is two-bit widealways @(posedge clk or posedge myReset) begin...

end



RTL15.1

Message

Else branch of event controlled if statement is not supported

Default Severity

Warning

Description

For modeling a flip-flop with asynchronous forces, the clock edge should be the fulfillingcondition of the last conditional block. In addition, there should be assignment to output underonly one clock edge. Both edges of clock signal are used in a sequential process.

Example

In the following example, both HIGH and LOW edges of the signal clk are used in a sequentialprocess (see lines 19 and 21, respectively):

library ieee;use ieee.std_logic_1164.all;use ieee.numeric_std.all;entity ClockEdge isport (sort : out unsigned (3 downto 0);

clk : in std_logic;rst : in std_logic;ena1 : in unsigned (3 downto 0));

end ClockEdge;architecture rtl_clkedge of ClockEdge isconstant ZERO : unsigned(3 downto 0) := "0000";constant HIGH : std_logic := ’1’;constant LOW : std_logic := ’0’;begin

p0_OK:process (clk,rst)begin

if (rst =HIGH) thensort <= ZERO;

elsif ( clk’event and clk=HIGH) thensort <= ena1;

elsif ( clk’event and clk=LOW) thensort <= ena1 + ena1;

end if;end process p0_OK;

end rtl_clkedge;



RTL15.2

Message

Sensitivity/clock style is unsupported

Default Severity

Warning

Description

The always block is sensitive to both the edges and levels of some signals. Synthesis toolsdo not support both level and edge sensitive nodes in the sensitivity list.

Example

In the following example, line 5 has both level and edge sensitivity nodes:module mult_clks_in_always2 (clk, q, d, rst1, rst2);input clk, d, rst1, rst2;output q;reg q;always @(clk or posedge rst1)begin

if (rst2)q <= d;

endendmodule



RTL16.1

Message

Non-local variable is read in a function body

Default Severity

Warning

Description

A non-local variable is read in a function body.

Example

On line 1 of the following example, glob_1 is declared outside of function f1(). On line 7,an RTL16.1 warning is reported because glob_1 is read inside the function body. RTL16.1warns potential mismatch between synthesis and simulation semantics.

reg glob_1; // glob_1 is declared outside of function f1...function f1 ...reg local_1;

begin...

local_1 = glob_1; // RTL16.1: glob_1 is read inside the function body...end



RTL16.2

Message

Non-local variable is assigned in a function body

Default Severity

Warning

Description

A non-local variable is assigned in a function body.

Example

On line 1 of the following example, glob_1 is declared outside of function f1(). On line 7,an RTL16.2 warning is reported because glob_1 is assigned inside the function body.RTL16.2 warns about the function body contains a side effect due to this external variableassignment.

reg glob_1; // glob_1 is declared outside of function f1...function f1 ...reg local_1;...

begin...glob_1 = local_1; // RTL16.2: glob_1 is assigned inside the function body...

end



RTL17

Message

Variable size exceeds the maximum limit

Default Severity

Error

Description

The variable size exceeds the maximum limit.

Example

In the following example, the variable tmp size exceeds the limit of 8192*8192 (see line 3)

module test (out);output [31:0] out;wire [8192*8192:0] tmp;assign out = tmp[31:0];endmodule



RTL17.1

Message

Expression size exceeds the maximum limit

Default Severity

Error

Description

The expression size exceeds the maximum limit.

Example

The following example triggers the RTL17.1 message because the expression size exceedslimit 67108864. The objects maximum bit size of 67108864 is predefined by all Conformaltools.module test(output r1);wire [67108864:0] r1; // ERROR: RTL17.1 violationassign r1 = 0;

endmodule



RTL18.1

Message

Package is not an IEEE standard

Default Severity

Ignore

Description

The IEEE package is not a standard package.

Example

In the following example, std_logic_arith is not a standard IEEE package (see line 2):

library ieee;use ieee.std_logic_arith.all;entity test isport (out1 : out signed (1 downto 0);in1 : in signed (1 downto 0);in2 : in signed (1 downto 0));

end test;architecture rtl of test isbeginp1:process( in1,in2)beginout1 <= in1 + conv_integer(in2);

end process p1;end rtl;



RTL18.2

Message

Function definition has empty body

Default Severity

Warning

Description

The function definition has empty body.

Example

In the following example, the function byte_reversal in line 10 is an empty function:

library ieee;use ieee.std_logic_1164.all;entity func isport(data:in std_logic_vector(8 downto 0);rev_data:out std_logic_vector(8 downto 0));end func;architecture func of func isfunction byte_reversal (arg:std_logic_vector)return std_logic_vector is

beginend byte_reversal;beginprocessbeginrev_data <= byte_reversal(data);end process;end func;



RTL18.3

Message

Function call does not refer to a function definition

Default Severity

Error

Description

The function call does not refer to a function definition.

Example

In the following example, the function func in line 6 is not defined:

module test(in,out);input in;output out;reg out;always @(in)out = func(in);

endmodule



RTL18.4

Message

Ignoring resolution function. This might cause mismatches between simulation andsynthesis

Default Severity

Warning

Description

The ’resolved’ function defined in package IEEE STD_LOGIC_1164 is the only supportedresolution function. Other resolution functions are ignored.

Example

In the following example, resolution function RESOLVE_VOLTAGE is ignored:

...function RESOLVE_VOLTAGE ( V: UVOLTAGE_VECTOR ) return UVOLTAGE;subtype VOLTAGE is RESOLVE_VOLTAGE UVOLTAGE;



RTL19.1

MessageIdentifier is a reserved keyword and might conflict in designs with mixed languages

Default Severity

Warning

Description

The identifier is a reserved keyword for Verilog or VHDL.

Example

In the following example, logic is a System Verilog keyword (see line 2):

module test (input din, output logic);assign logic = din;endmodule ;



RTL20.1

Message

Pre-defined attribute is not supported

Default Severity

Warning

Description

The specified pre-defined attribute in the design is not supported. Remodel the design toavoid this error.

Example

In the following example, the last_attribute in line 21 is not supported:library IEEE;use IEEE.std_logic_1164.all;entity lat isport ( din: in bit;

clk :in bit;din1 : in bit_vector(1 downto 0);dout : out bit_vector(2 downto 0);dout1 : out bit_vector(1 downto 0));

end lat;architecture behave of lat issignal clk1 : bit;component lat_bit isport ( d: in bit;

clk :in bit;q : out bit);

end component;begindout(0) <= din;process(clk1,din)beginif clk1’last_value = ’0’ and clk1 = ’1’ thendout(2 downto 1) <= din1;

end if;end process;I1 : lat_bit port map(din, clk, dout1(1));I0 : lat_bit port map(din, clk, dout1(0));

end behave;



RTL20.2

Message

Function is not supported

Default Severity

Warning

Description

The referenced function is not supported (1’bx will be returned).

Example

In the following example, the sqrt function (line 10) is not supported:library ieee;use ieee.math_real.all;ENTITY test_constant_reals ISPORT (sample_out : OUT integer );

END test_constant_reals;

ARCHITECTURE rtl OF test_constant_reals ISBEGINsample_out <= integer(sqrt(1.375));

END rtl;



RTL20.3

Message

Could not find configuration

Default Severity

Warning

Description

The refered configuration could not be found.

Example

In the following example, if the configuration bug2_cfg is not defined before configurationbug_cfg, this message will be issued....configuration bug_cfg of bug is...use configuration work.bug2_cfg...



SPICE Netlist Format

This category of rules applies to SPICE netlists used for Conformal Custom. The followingtable lists the SPICE (SPI) rule numbers and their messages.

Rule Number Message

SPI1.1 Diode instance is ignored

SPI1.2 Incorrect diode instance is ignored

SPI1.3 SPICE element/card is ignored

SPI1.4 Subckt name duplicated and previous ones are ignored

SPI3.2 Model redefined. Using last definition and ignoring earlier ones

SPI4.1 .GLOBAL statement for pin is redefined. Previous definition isignored

SPI4.2 .GLOBAL statement for pin with type ’C’ is not supported and isignored

SPI5.1 Implicit bulk VDD Net reset to GND due to .GLOBAL declaration

SPI5.2 Implicit bulk GND Net reset to VDD due to .GLOBAL declaration

SPI7.1 Duplicated pin in subckt. Creating new pin

SPI7.2 Duplicate pin of subckt with different pin connections in instance

SPI8.1 Undefined Pin in ’*.PININFO’ is ignored



SPI1.1

Message

Diode instance is ignored

Default Severity

Warning

Description

The checker is ignoring one or more diode instances in the SPICE netlist.

Example

The checker reports the following:

SPI1.1: Ignoring diode instanceType: Golden design Severity: Warning Occurrence: 11: ant/D1on line 3 in file 'test.sp'

That is, the checker ignores a diode instance called D1 in the SPICE netlist.

.SUBCKT ant yD1 y vss.ENDS



SPI1.2

Message

Incorrect diode instance is ignored

Default Severity

Warning

Description

The checker is ignoring one or more incorrectly instantiated diode instances in the SPICEnetlist.

The checker ignores diodes in all cases. See SPI1.1 on page 721.

Example

In the following example, the checker generates the SPI1.2 message for line 3 (in bold)because D should be followed by some alphanumeric characters. (Also, since the checkerignores all diodes, line 2 triggers the SPI1.1 message.)

.subckt foo a bD1 a bD a b

.ends



SPI1.3

Message

SPICE element/card is ignored

Default Severity

Warning

Description

The SPICE element or card is ignored.



SPI1.4

Message

Subckt name duplicated and previous ones are ignored

Description

The checker encountered a subcircuit name that was already used in the SPICE netlist. Whenthis duplication happens, the checker retains the last definition encountered and ignoresearlier ones.



SPI3.2

Message

Model redefined. Using last definition and ignoring earlier ones

Default Severity

Warning

Description

The checker encountered a redefined model in the SPICE netlist. When this redefinitionoccurs, the checker uses the last definition encountered and ignores earlier ones.

Example

In the following SPICE netlist example, P1 is defined as PMOS and redefined as NMOS. In thiscase, the checker recognizes NMOS as the definition for P1.

.model P1 PMOS

.model P1 NMOS



SPI4.1

Message

.GLOBAL statement for pin is redefined. Previous definition is ignored

Default Severity

Warning

Description

The checker encountered a redefined .GLOBAL statement in the SPICE netlist. When thisredefinition occurs, the checker uses the last definition encountered and ignores earlier ones.

Example

In the following SPICE netlist example, pin pr is defined as power and redefined as ground.In this case, the checker recognizes ground as the definition for pin pr.

.global pr:P

.global pr:G



SPI4.2

Message

.GLOBAL statement for pin with type ’C’ is not supported and is ignored

Default Severity

Warning

Description

The checker encountered a .GLOBAL statement with pin type ‘C’ in the SPICE netlist. Whenthis occurs, the checker ignores that pin type.

Example

In the following SPICE netlist example, pin type ’C’ of the global net ’a’ will be ignored:

.global vdd:P a:C;



SPI5.1

Message

Implicit bulk VDD Net reset to GND due to .GLOBAL declaration

Default Severity

Warning

Description

The SPICE netlist includes a .global declaration that overrides an implicit VDD assignment.

By default, the checker assumes that the bulk node of PMOS is VDD. The net connected to thebulk node is thus implicitly assigned as VDD. However, if there is a .global declaration for aPMOS net, the global declaration takes precedence over the implicit assignment.

Example

In the following example, net a retains its definition as assigned by the .global statementon line 1 (in bold). The checker ignores the implicit meaning of this net based on the bulkconnection (see line 5). Also refer to SPI5.2 on page 729.

.global a:G

.global b:P

.subckt inv aa bb outM1 aa bb VDD a PMOSM2 aa bb VSS b NMOS.ends



SPI5.2

Message

Implicit bulk GND Net reset to VDD due to .GLOBAL declaration

Default Severity

Warning

Description

The SPICE netlist includes a .global declaration that overrides an implicit GND assignment.

By default, the checker assumes that the bulk node of NMOS is GND. The net connected to thebulk node is thus implicitly assigned as GND. However, if there is a .global declaration foran NMOS net, the global declaration takes precedence over the implicit assignment.

Example

In the following example, net b retains its definition as assigned by the .global statementon line 2 (in bold). The checker ignores the implicit meaning of this net based on the bulkconnection (see line 6). Also refer to SPI5.1 on page 728.

.global a:G

.global b:P

.subckt inv aa bb outM1 aa bb VDD a PMOSM2 aa bb VSS b NMOS.ends



SPI7.1

Message

Duplicated pin in subckt. Creating new pin

Default Severity

Warning

Description

The checker encountered a duplicate pin name in the subckt definition while reading a SPICEnetlist. When this duplication occurs, the checker creates a new name for the second pin withthe following format: <duplicate_pin_name>_vplx_redundant_<number>.

Example

In the following SPICE netlist example, pin a is defined on line 2 (in bold) and repeated in thesubckt definition on line 3 (in bold). The checker creates a new pin for the second a itencountered. The new pin is named a_vplx_redundant_0.

.subckt inv a b a outM1 a b VDD VDD PMOSM2 a b VSS VSS NMOS.ends



SPI7.2

Message

Duplicate pin of subckt with different pin connections in instance

Default Severity

Warning

Description

The checker is detecting an instance with duplicated pins in the SPICE netlist:

Example

In the following SPICE netlist example, the second pin of instance x1 of subckt inv isredundant and will be ignored:

.global vdd gnd;

.subckt inv in in;m1 vdd in out vdd p;m2 out in gnd gnd n;.ends inv;.subckt top o i;x1 o i inv;.ends top;



SPI8.1

Message

Undefined Pin in ’*.PININFO’ is ignored

Default Severity

Warning

Description

A SPICE *.PININFO statement includes an undefined pin. *.PININFO can be used todefine pins as input (I), output (O) or bidirectional (B). If I, O or B is missing for the pin definedin a PININFO statement, the checker ignores the undefined pin and issues a warning.

Example

In the following PININFO example, pin a is defined as I. However, on line 2 (in bold) thedefinition for pin b is missing. When the checker encounters line 2, it generates the SPI8.1message.

*.pininfo a:I*.pininfo b:



System Verilog

This category of rules applies to System Verilog designs. The following table lists the SystemVerilog (SV) rule numbers and messages.

Rule Number Message

SV1.1 covergroup usage is unsupported and ignored

SV1.2 ’assert property’ is unsupported and ignored

SV1.3 ’assume property’ is unsupported and ignored

SV1.4 ’cover property’ is unsupported and ignored

SV1.5 ’void’ type is not allowed in object declaration

SV1.6 Missing argument list for function call

SV1.7 Unbounded range parameter ’$’ is not supported

SV1.8 Procedural assertion is unsupported and ignored

SV1.9 ’distribution weight’ is unsupported and ignored

SV1.10 Sequence operation is unsupported and ignored

SV1.11 Sequence concatenation is unsupported and ignored

SV1.12 number_of_ticks is not a constant value

SV1.13 number_of_ticks must be 1 or greater

SV1.14 Sequence method is unsupported and ignored

SV1.15 Recursive properties are unsupported and ignored

SV2.1 Packed type cannot contain real/shortreal/unpacked type

SV2.2 All elements must have same size in a packed union type

SV3.1 Modules can neither be declared nor instantiated in interfaces



SV1.1

Message

covergroup usage is unsupported and ignored

Default Severity

Warning

Description

The covergroup usage is not supported and is ignored.

Example

In the following example, g2 (line 2) is unsupported:module test( input logic [7:0] in1, reg clk, output logic [7:0] out1);covergroup g2 @(posedge clk);endgroupalways@( posedge clk)beginout1 = in1;

endendmodule



SV1.2

Message

’assert property’ is unsupported and ignored

Default Severity

Warning

Description

The assert property is not supported and is ignored.

Example

In the following example, assert property p1 (line 3) is ignoredmodule prop1 (input clk,output logic [7:0] count1);logic [7:0] counter1 = ’0;assert property (p1) count1 = counter1;

endmodule



SV1.3

Message

’assume property’ is unsupported and ignored

Default Severity

Warning

Description

The assume property is not supported and is ignored.

Example

In the following example, assume property p1 is ignored:module prop1 (input clk,output logic [7:0] count1);logic [7:0] counter1 = ’0;assume property (p1) count1 = counter1;

endmodule



SV1.4

Message

’cover property’ is unsupported and ignored

Default Severity

Warning

Description

The cover property is not supported and is ignored.

Example

In the following example, cover property p1 is ignored:module prop1 (input clk,output logic [7:0] count1);logic [7:0] counter1 = ’0;cover property (p1) count1 = counter1; <b>

endmodule



SV1.5

Message

’void’ type is not allowed in object declaration

Default Severity

Error

Description

The ’void’ type is not allowed in the object declaration.

Example

In the following example, it is illegal to declare a void type variable for var1:void var1;



SV1.6

Message

Missing argument list for function call

Default Severity

Error

Description

Indicates that the function call does not have an argument list.

Example

In the following example, in line 11, the argument list is missing:

module test(in, out);input in;output out;function func;input din;beginfunc = din;

endendfunctionalways @(in)out = func;

endmodule



SV1.7

Message

Unbounded range parameter ’$’ is not supported

Default Severity

Error

Description

Indicates that the unbounded range parameter ’$’ is not supported. This is for System Verilogonly.

Example

In the following example, in line 6, ’$’ is used as parameter.

module test #(parameter p1 = 1)(input int i, output int out);always @(i)out = i+p1;

endmodulemodule top(input int in, output int dout);test #($) sub(in,dout);endmodule



SV1.8

Message

Procedural assertion is unsupported and ignored

Default Severity

Warning

Description

Indicates that the procedural assertion is unsupported and is ignored. This is for SystemVerilog only.

Example

In the following example, the procedural assertion in line 3 is unsupported and ignored.

module test (input logic clk,input logic in);always @(posedge clk)

if (in == ’1) assert (req1 || req2);else begin$error("assert failed" );end

endmodule



SV1.9

Message

’distribution weight’ is unsupported and ignored

Default Severity

Warning

Description

The usage of distribution weight is described in SystemVerilog LRM 13.4.4 Distribution.

The usage of distribution weight is unsupported and is ignored by all Conformal softwaretools.

Example

In the following example, x is equal to 100, 200, or 300 with weighted ratio of 1-2-5. Theusage of the distribution weight will trigger this warning.

x dist {100 := 1, 200 := 2, 300 := 5}



SV1.10

Message

Sequence operation is unsupported and ignored

Default Severity

Warning

Description

The usage of sequence is described in SystemVerilog LRM 17.5 Sequences.

The usage of sequence is unsupported and is ignored by all Conformal software tools.

Example

In the following example, the usage of sequence operation (first_match in line 5) willtrigger this warning.

sequence t1;te1 ## [2:5] te2;

endsequencesequence ts1;

first_match(te1 ## [2:5] te2);endsequence



SV1.11

Message

Sequence concatenation is unsupported and ignored

Default Severity

Warning

Description

The usage of sequence is described in SystemVerilog LRM 17.5 Sequences.

The usage of sequence is unsupported and is ignored by all Conformal software tools.

Example

In the following example, using cycle delay ##1 will trigger this warning.

@(posedge clk0) sig0 ##1 @(posedge clk1) sig1



SV1.12

Message

number_of_ticks is not a constant value

Default Severity

Error

Description

The usage of $past() is described in SystemVerilog LRM 17.7.3 The sampled value is:$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

where the number_of_ticks must be 1 or greater. If number_of_ticks is not specified,it defaults to 1. The SV1.12 error is reported if number_of_ticks is not evaluated to be aconstant value.

Example

The following example will trigger this error if input_port_N is not a constant expression:

$past( bet1, input_port_N)



SV1.13

Message

number_of_ticks must be 1 or greater

Default Severity

Error

Description

The usage of $past() is described in SystemVerilog LRM 17.7.3 The sampled value is:$past( expression1 [, number_of_ticks] [, expression2] [, clocking_event])

where number_of_ticks must be 1 or greater. If number_of_ticks is not specified, then itdefaults to 1. The SV1.13 error is reported if number_of_ticks is not evaluated to be 1 orgreater.

Example

The following example will trigger this error because -1 is not 1 or greater than 1:

$past( bet1, -1)



SV1.14

Message

Sequence method is unsupported and ignored

Default Severity

Warning

Description

The sequence usage is described in SystemVerilog LRM 17.5 Sequences.

The sequence methods are described in SystemVerilog LRM 17.12.6.

The SV1.14 warning is reported if sequence methods are used.

Example

The following example will trigger this warning because an ended method is used (line 5):

sequence e1;@(posedge sysclk) $rose(ready) ##1 proc1 ##1 proc2 ;

endsequencesequence rule;

@(posedge sysclk) reset ##1 inst ##1 e1.ended ##1 branch_back;endsequence



SV1.15

Message

Recursive properties are unsupported and ignored

Default Severity

Warning

Description

The sequence usage is described in SystemVerilog LRM 17.11.4 Recursive property.

The SV1.15 warning is reported if recursive properties are used.

Example

■ The following example shows a simple recursive property case, where a propertyinstantiation prop_always is inside the prop_always property declaration. Thiscauses a recursive property problem.

property prop_always(p);p and (1’b1 |=> prop_always(p));

endproperty

■ The following example shows a mutually recursive case, where in property declarationcheck_phase1, there is an instantiation check_phase2, and in property declarationcheck_phase2, there is an instantiation check_phase1. This causes a mutuallyrecursive property problem.

property check_phase1;s1 |-> (phase1_prop and (1’b1 |=> check_phase2));

endpropertyproperty check_phase2;

s2 |-> (phase2_prop and (1’b1 |=> check_phase1));endproperty



SV2.1

Message

Packed type cannot contain real/shortreal/unpacked type

Default Severity

Error

Description

Noninteger data types, such as real and shortreal, are not allowed in packed structures orunions. Neither are unpacked arrays.

Example

In the following packed struct type example, the errors are shown by comments:

typedef struct packed {bit [3:0] GFC;+real VPI; // real type is not allowed in a packed structurebit PT [3:0] ; // unpacked type is not allowed a packed structurebit [7:0] HEC;

} myPackedType;



SV2.2

Message

All elements must have same size in a packed union type

Default Severity

Error

Description

A packed union shall contain members that must be packed structures, or packed arrays orinteger data types all of the same size (in contrast to an unpacked union, where the memberscan be different sizes). This ensures that a union member that was written as anothermember can be read back.

Example

In the following packed union type example, the errors are shown by comments:

typedef union packed {bit [7:0] v1;bit [3:0][1:0] v2;bit [8:0] v3; // ERROR: v3 has 9 bits, but both v1 and v2 have 8 bits

} badPkUnionType;



SV3.1

Message

Modules can neither be declared nor instantiated in interfaces

Default Severity

Error

Description

Interfaces can be declared and instantiated in modules (either flat or hierarchical), butmodules can neither be declared nor instantiated in interfaces.

Example

In the following example, the module instantiation is not allowed in the interface declaration:

module mod1 (input aa, bb; output zz);assign zz = aa && bb;

endmodule

interface simple_bus; // Define the interfacelogic req, gnt;logic [7:0] addr, data;logic [1:0] mode;logic start, rdy;mod1 u0(req, gnt, rdy); // ERROR: SV3.1 violation.

endinterface: simple_bus



User-Defined Primitive

This category of rules applies to designs that include user-defined primitives. The followingtable lists the User-Defined Primitive (UDP) rule numbers and their messages.

Rule Number Message

UDP1.1 Swapped set and reset of DFF/DLAT

UDP1.2 Removed set-domination logic of DFF/DLAT

UDP1.3 Unknown set and reset domination. Implemented as resetdomination

UDP2.1 Inverter on data input of DFF/DLAT is moved to output

UDP2.2 Inverter on data input of DFF/DLAT is not moved to output

UDP3 Merged redundant user-defined DFF/DLAT primitive(s)

UDP3.1 Conflicting entries are detected in the outputs

UDP3.2 Primitive has unspecified term(s)

UDP4.1 Primitive contains illegal symbol ’z’

UDP4.2 Primitive contains an ’x’ output without an ’x’ input



UDP1.1

Message

Swapped set and reset of DFF/DLAT

Default Severity

Note

Description

The checker swapped a set and reset for a user-defined DFF or DLAT primitive. Automaticswapping of DFF and DLAT set and reset occurs only when there is a need to accommodatea conversion (for example, merging DFFs).

Example

Two warnings occurred for the following example:

1. On lines 5 through 8 (in bold), instance U1 is merged into instance U2 because they havethe same connection (except q and qb for outputs).

2. The checker swaps set and reset of instance U2 to accommodate merging instance U1.

module RSLTA (Q,QB,S,R,notifier);input S,R;output Q,QB;input notifier;rsltaq U1(.q(Q),.s(S),.r(R),.notify(notifier));rsltaqb U2(.qb(QB),.s(S),.r(R),.notify(notifier));

endmodule



UDP1.2

Message

Removed set-domination logic of DFF/DLAT

Default Severity

Note

Description

One or more user-defined DFF or DLAT primitives have multiple sets of set-dominant logic.The checker removed the redundant set of set-dominant logic.

Example

On line 11 of the following example, the design includes an OR logic to ensure a set-dominantDFF, but the DESFQ primitive was already defined in line 1 as a set-dominant DFF. Thus, thedesign includes two set-dominant logics (shown in lines 1 and 11).

primitive DESFQ = a set-dominant DFF

module test ( N01, H01, H02, H03, H04);input H01;input H02;input H03;input H04;output N01;not ( _G005, H03 );not ( _G002, H04 );or ( N01, _G008, H04 );DESFQ ( .Q(_G008), .D(H01), .CP(H02),

.RB(_G005), .SB(_G002), .notifier(notifier) );endmodule



UDP1.3

Message

Unknown set and reset domination. Implemented as reset domination

Default Severity

Warning

Description

A UDP is interpreted as a sequential DLAT or DFF logic, and:

■ DLAT or DFF has both asynchronous set and reset logic

■ set and reset logic might result in 1 at the same time

■ no domination on set or reset

Exampleprimitive srq0 ( Q, S, RX );output Q; reg Q;input S;input RX;

tableS RX : Q- : Q+1 1 : ? : 1 ;0 0 : ? : 0 ;? 1 : 1 : 1 ;0 ? : 0 : 0 ;0 1 : ? : - ;

endtableendprimitive

The Conformal software will generate a DLAT circuit with asynchronous set and reset:

■ set = S

■ reset = RX’

■ d = 0

■ clock = 0



The UDP does not specify the behavior when S = 1 and RX = 0. The Conformal softwareimplements the circuit as a reset dominated logic, which implies that when S = 1 and RX = 0,Q = 0. This is usually caused by UDP table incompletion.



UDP2.1

Message

Inverter on data input of DFF/DLAT is moved to output

Default Severity

Warning

Description

One or more user-defined DFF or DLAT primitives (UDP) include an inverter on the data port.By default, the checker relocates inverters from data port to output port.

Example

In the following example, primitive dff_simple has an inverter at the data port of the DFF,but the checker moves it to the output port of the DFF.

primitive dff_simple(Q, S, R, CK, D);output Q;input S, R, CK, D;reg Q;

table1 0 ? ? : ? : 1;? 1 ? ? : ? : 0;0 0 r 0 : ? : 1;0 0 r 1 : ? : 0;0 0 (?0) ? : ? : -;




UDP2.2

Message

Inverter on data input of DFF/DLAT is not moved to output

Default Severity

Warning

Description

One or more user-defined DFF or DLAT primitives (UDP) include an inverter on the data port.By default, the checker relocates inverters from data port to output port. However, in this case,you specified that the checker will not move the DFF or DLAT when you used the followingcommand:

add udp model dff_simple -nomove_inverter

Example

In this example, primitive dff_simple has an inverter at the data port of the DFF, but thechecker did not move it since the user applied the -nomove_inverter option.

primitive dff_simple(Q, S, R, CK, D);output Q;input S, R, CK, D;reg Q;

table1 0 ? ? : ? : 1;? 1 ? ? : ? : 0;0 0 r 0 : ? : 1;0 0 r 1 : ? : 0;0 0 (?0) ? : ? : -;


Input:

SETUP>add udp model dff_simple -nomove_inverterSETUP>read design test.v -verilog



UDP3

Message

Merged redundant user-defined DFF/DLAT primitive(s)

Default Severity

Note

Description

The design includes one or more redundant user-defined DFF or DLAT primitives. Thechecker merges all redundant user-defined DFF and DLAT primitives.

Example

In the following example, DFF UDP_A is redundant and merged into DFF UDP_B. See lines 7through 10 (in bold).

module test ( N01, N02, H01, H02, notifier );input H01;input H02;input notifier;output N01;output N02;DESFQ UDP_A(.Q(N01), .D(H01), .CP(H02), .RB(1'b1),.SB(1'b1), .notifier(notifier));DESFQ UDP_B(.Q(N02), .D(H01), .CP(H02),.RB(1'b1), .SB(1'b1), .notifier(notifier));

endmodule



UDP3.1

Message

Conflicting entries are detected in the outputs

Default Severity

Warning

Description

There are conflict entries in the user-defined primitive outputs.

Example

In the following example, the two lines have the same input values but different output values:// D CK RB SB FLAG : Qt : Qt+1

? ? 0 0 ? : ? : 1;//? ? 0 0 ? : ? : 0;//



UDP3.2

Message

Primitive has unspecified term(s)

Default Severity

Warning

Description

There are unspecified term(s) in the UDP table.

Example

In the following example, term ’010’ and ’011’ is unspecified:primitive udp_inv_clr0 (qn, clr, pre, inp);

output qn;input clr, pre, inp;table// clr pre inp : qn

0 0 ? : 0;1 ? 0 : 1;1 ? 1 : 0;// ? 1 0 : 1;// ? 1 1 : 0;x x 1 : 0;x x 0 : 1;




UDP4.1

Message

Primitive contains illegal symbol ’z’

Default Severity

Warning

Description

The UDP contains an entry that has illegal symbol ’z’.

Example

In the following example, because the entry in line 11 has symbol ’z’, mydff will beblackboxed:primitive mydff (qq, clk, dd, ss, rr);output qq; reg qq;input clk, dd, ss, rr;table// clk dd ss rr : qq : qq+

r 0 0 0 : ? : 0 ;r 1 0 0 : ? : 1 ;f ? 0 0 : ? : - ;? ? 1 0 : ? : 1 ;? ? 0 1 : ? : 0 ;? ? 1 1 : ? : z ;




UDP4.2

Message

Primitive contains an ’x’ output without an ’x’ input

Default Severity

Warning

Description

The UDP contains an entry that has an ’x’ value output without an ’x’ value input.

Example

In the following example, the last line of the table has ’x’ as an output, and its input does notcontain ’x’:

primitive mydff (qq, clk, dd, ss, rr);output qq; reg qq;input clk, dd, ss, rr;

table// clk dd ss rr : qq : qq+

r 0 0 0 : ? : 0 ;r 1 0 0 : ? : 1 ;f ? 0 0 : ? : - ;? ? 1 0 : ? : 1 ;? ? 0 1 : ? : 0 ;? ? 1 1 : ? : x ;




Verilog

This category of rules applies to designs that are written in Verilog language. RTL rules applyto Verilog designs and VHDL designs (see “Register Transfer Level” on page 603).

The following table lists the Verilog (VLG) rule numbers and their messages.

Rule Number Message

VLG1.1 Case inequality operators are treated as logical inequalityoperators

VLG1.2 Case equality operators are treated as logical equality operators

VLG1.3 Wild inequality is treated as inequality

VLG1.4 Wild equality is treated as equality

VLG2.1 Non-constant case-item is used in casex/casez statement

VLG2.2 Non-binary case-item is used in casex/casez statement

VLG2.3 default keyword is not the last item in case statement(s)

VLG3.1 Unsized constant(s) with leading X/Z value is extended beyond32 bits

VLG3.2 Verilog event expression in always block(s) are complex

VLG3.3 Replication is not a constant or it contains X or Z values

VLG3.4 Zero replication is treated as NULL in concatenation

VLG3.5 Null expression is not allowed (caused by zero replication)

VLG3.6 Negative replication is not allowed

VLG3.7 Unsized constant value is set to 32-bit in concatenation

VLG4.1 Wire type wand is used

VLG4.2 Wire type wor is used

VLG4.3 Implicit declared net is generated

VLG4.4 Cutpoint not found

VLG5.1 Primitive output port has multiple bits. Ignored all but LSB bit

VLG5.2 Primitive input port has multiple bits. Ignored all but LSB bit

VLG5.3 Wire and port size declaration(s) do not match



VLG5.4 Port size of array instance does not match

VLG5.5 Named port association ignored for primitive gate

VLG5.6 Named port association is ignored for primitive gate

VLG6.1 Globally referenced variable is unresolved

VLG6.2 Globally referenced variable resolved

VLG6.3 Unsupported system function call (converted to 1'b1)

VLG6.3a Unsupported system task call

VLG6.4 Supported system datapath function call

VLG6.5 Time literal is unsupported

VLG6.6 Event object is unsupported

VLG6.7 Hierarchical function call is not supported (blackboxed)

VLG6.8 Specify block is ignored

VLG6.10 Intra-assignment event specification is not supported

VLG6.12 fork-join constructs are not supported

VLG6.13 force-release constructs are not supported

VLG6.14 Global reference on the left side of the assignment is notsupported

VLG6.15 disable construct is not supported

VLG6.16 wait construct is not supported

VLG7 Nets renamed after removing backslash

VLG8 Buffer inserted

VLG9 Names conflict with previous declarations

VLG9.1 Text macro is redefined

VLG9.2 ‘define macro is used

VLG9.4 Instance name conflicts with previous declarations

VLG10 Non-blocking assignment is in disabled block

VLG10.1 Non-blocking assignment encountered in function

Rule Number Message



VLG10.2 deassign statements cannot be synthesized and are notsupported

VLG10.3 Sequential assign statement is not supported

VLG11.1 Combinational logic is inferred in an always_latch block

VLG11.2 Latches are inferred in an always_comb block

VLG12.1 Null statement ’;’ is not allowed inside a begin-end block and isignored

VLG13.1 Unpacked dimension is not allowed

VLG13.2 Unsized dimension is not allowed

VLG13.3 Associative dimension is not allowed

VLG14.1 Missing module instance name

VLG15.1 Block name is previously declared

VLG16.1 Syntax error in Verilog instantiation

Rule Number Message



VLG1.1

Message

Case inequality operators are treated as logical inequality operators

Default Severity

Warning

Description

The design includes one or more case inequality operators that the checker treats as logicalinequality operators.

Inequality operators syntax:

!== is a case inequality operator.

!= is a logical inequality operator.

Example

In the following example, the checker treats the case inequality operator as a logical inequalityoperator. See line 7 (in bold).

module VLGT (clk,cond,in0,in1,out0);input clk,in0,in1;input [1:0] cond;output out0;reg out0;always @(posedge clk) beginif (cond[0] !== cond[1])out0 <= in0;

elseout0 <= in1;

endendmodule



VLG1.2

Message

Case equality operators are treated as logical equality operators

Default Severity

Warning

Description

The design includes one or more case equality operators that the checker treats as logicalequality operators.

Equality operators syntax:

=== is a case equality operator.

== is a logical equality operator.

Example

In the following example, the checker treats the case equality operator as a logical equalityoperator. See line 7 (in bold).

module VLGT (clk,cond,in0,in1,out0);input clk,in0,in1;input [1:0] cond;output out0;reg out0;always @(posedge clk) beginif (cond[0] === cond[1])out0 <= in0;

elseout0 <= in1;

endendmodule



VLG1.3

Message

Wild inequality is treated as inequality

Default Severity

Warning

Description

The checker does not support the !?= SystemVerilog operator with the exact semanticssupported in simulation. The checker treats !?= as !=.

Example

In the following example, the checker encounters !?= on line 4 (in bold) and treats it as !=.Similarly, on line 5, the checker treats !== (case inequality) as !=. (Refer to VLG1.1 onpage 767.)

module test(aa, bb, o1, o2);input aa, bb;output o1, o2;assign o1 = aa !?= bb;assign o2 = aa !== bb;

endmodule



VLG1.4

Message

Wild equality is treated as equality

Default Severity

Warning

Description

The checker does not support the =?= SystemVerilog operator with the exact semanticssupported in simulation. The checker treats =?= as ==.

Example

In the following example, the checker encounters =?= on line 4 (in bold) and treats it as ==.Similarly, on line 5, the checker treats === (case equality) as ==. (Refer to VLG1.2 onpage 768.)

module test(aa, bb, o1, o2);input aa, bb;output o1, o2;assign o1 = aa =?= bb;assign o2 = aa === bb;

endmodule



VLG2.1

Message

Non-constant case-item is used in casex/casez statement

Default Severity

Note

Description

The design includes one or more case_items that use a non-constant value in a casex orcasez statement.

Sample casex statement syntax:

casex (case_expression)

case_item1 : case_item_statement1;


default : case_item_statement3;

endcase

Example

In the following example, the design uses primary input a for the second case_item (see line9).

module test ( a, b, c, sel, out0);input a, b, c;input sel;output out0;reg out0;always @(sel or a or b or c) begincasex(sel)1'b1 : out0 = a;a : out0 = b;default: out0 = c;

endcaseend

endmodule



VLG2.2

Message

Non-binary case-item is used in casex/casez statement

Default Severity

Note

Description

The design includes one or more case_items that use a non-binary value in a casex or casezstatement.

Example casex statement syntax:

case (case_expression)




endcase

Example

In the following example, the design uses an X value for the second case_item. See line 9 (inbold).

module test ( a, b, c, sel, out0);

input a, b, c;input sel;output out0;reg out0;always @(sel or a or b or c) begincasex(sel)1'b1 : out0 = a;1'bx : out0 = b;default: out0 = c;

endcaseend

endmodule



VLG2.3

Message

default keyword is not the last item in case statement(s)

Default Severity

Warning

Description

The default keyword is not the last case_item in one or more case statements.

Sample case statement syntax:

case (case_expression)




endcase

Example

In the following example, the keyword default is not the last case_item. See line 9 (in bold).

module test ( a, b, c, sel, out0);input a, b, c;input sel;output out0;reg out0;always @(sel or a or b or c) begincasex(sel)1'b1 : out0 = a;default: out0 = c;1'b0 : out0 = b;

endcaseend

endmodule



VLG3.1

Message

Unsized constant(s) with leading X/Z value is extended beyond 32 bits

Default Severity

Warning

Description

One or more unsized constants with a leading X/Z value are extend beyond 32 bits.

Example

In the following example, the design assigns an unsized constant with leading X value 'bx toa 34-bit output out0 (see line 5).

module test(out0,y,in);output [33:0] out0;output y;input in;assign out0 = 'bx;assign y = in;endmodule



VLG3.2

Message

Verilog event expression in always block(s) are complex

Default Severity

Warning

Description

The Verilog event expressions used in one or more always blocks are complex.

Example

In the following example, event expression a|b is considered complex (see line 5).

module test (a, b, q);input [3:0] a, b;output [3:0] q;reg [3:0] q;always @ (a | b ) beginq = a & b;

endendmodule



VLG3.3

Message

Replication is not a constant or it contains X or Z values

Default Severity

Warning

Description

A replication multiplier is not a constant or it contains X or Z values.

Note: This check has a warning default severity level, but the module is blackboxed.

Example

In the following example, replication 2’bx is illegal value (see line 6).

module test (a, q);input [3:0] a;output [4:0] q;reg [4:0] q;always @ (a ) beginq = {{2’b1x{1’b1}}, 1’b0};

endendmodule



VLG3.4

Message

Zero replication is treated as NULL in concatenation

Default Severity

Warning

Description

A replication multiplier is a constant 0 but the entire concatenation remains valid. Thereplicated concatenation portion is treated as NULL as if the portion is removed from theentire concatenation.

Example

In the following example, replication 2’b0 is illegal value (see line 6).

module test (a, q);input [3:0] a;output [4:0] q;reg [4:0] q;always @ (a ) beginq = {{2’b0{2’b1}}, 1’b0};

endendmodule



VLG3.5

Message

Null expression is not allowed (caused by zero replication)

Default Severity

Warning

Description

A replication multiplier is a constant 0 and the entire concatenation becomes NULL. Thereplicated concatenation portion is treated as NULL as if the portion is removed from theentire concatenation.


Example

In the following example, on line 6 the replication multiplier is a constant 0 and the entireconcatenation becomes NULL, which is not allowed.module test (a, q);input [3:0] a;output [4:0] q;reg [4:0] q;always @ (a ) beginq = {2’b0{2’b1}};

endendmodule



VLG3.6

Message

Negative replication is not allowed

Default Severity

Warning

Description

A replication multiplier is a negative integer constant.


Example

In the following example, replication -1 is not allowed (see line 6).

module test (a, q);input [3:0] a;output [4:0] q;reg [4:0] q;always @ (a ) beginq = {{-1{2’b1}}, 4’b1};

endendmodule



VLG3.7

Message

Unsized constant value is set to 32-bit in concatenation

Default Severity

Warning

Description

The unsized constant value is set to 32-bit in concatenation.

Example

In the following example, 1 is an unsized constant value, will be set to 32-bit in concatenation(see line 6).

module test (a, q);input [3:0] a;output [4:0] q;reg [4:0] q;always @ (a ) beginq = {1, 4’b1};

endendmodule



VLG4.1

Message

Wire type wand is used

Default Severity

Warning

Description

The design includes a user-specified wire-AND resolution for one or more multi-driven nets.

Example

In the following example, the design declares wire wand, which is used for multi-driven outputq. See line 4 (in bold).

module test (a,b,q);input a, b;output q;wand q;assign q = aassign q = b;endmodule



VLG4.2

Message

Wire type wor is used

Default Severity

Warning

Description

The design includes a user-specified wire-OR resolution for one or more multi-driven nets.

Example

In the following example, the design declares wire wor, which is used for multi-driven out0.See line 5 (in bold).

module test ( a, b, c, sel, out0);input a, b, c;input sel;output out0;wor out0;assign out0 = a;assign out0 = b;endmodule



VLG4.3

Message

Implicit declared net is generated

Default Severity

Warning

Description

An implicit declared net is generated.

Example

In the following example, in_top is an implicit declared net (see line 13):

`default_nettype nonemodule test(out,in);input in;output out;reg out;always @(in)beginif (in ) out = in; else out = ~in;

endendmodulemodule top (out_top);output out_top;test s1(out_top,in_top);endmodule



VLG4.4

Message

Cutpoint not found

Default Severity

Warning

Description

Cannot find the specified cutpoint.

Example

In the following example, the pragma cutpoint ram2 cannot be found in the design (see line 7):

module test(clk, addr, din, dout);input clk;input [1:0] addr;input [0:0] din;output [0:0] dout;reg [0:0] ram [3:0];// pragma cutpoint "ram2"

always @(clk or addr or din) beginif (clk && ram[0] ) ram[addr[1:0]] = din;

endassign dout = ram[addr[1:0]];endmodule



VLG5.1

Message

Primitive output port has multiple bits. Ignored all but LSB bit

Default Severity

Warning

Description

The design includes one or more primitive output ports with multiple bits. The checker ignoresall but the least significant bit (LSB) of the primary vector output.

Example

In the following example, output o has three bits. The checker only keeps the LSB. See line4 (in bold).

module test(o,a,b);output [2:0] o;input a,b;and(o,a,b);endmodule



VLG5.2

Message

Primitive input port has multiple bits. Ignored all but LSB bit

Default Severity

Warning

Description

One or more primitive input ports have multiple bits. The checker changes all primitive vectorinput ports to scalar input ports by applying OR logic reduction.

Example

In the following example, the checker reduces the two-bit input a to a single-bit input a byOR-ing a[0] and a[1] together. See line 5 (in bold).

module test ( a, out0);input[1:0] a;output out0;wire out0;not (out0,a);endmodule



VLG5.3

Message

Wire and port size declaration(s) do not match

Default Severity

Warning

Description

In one or more cases, the design’s wire and port size declarations do not match.

Example

In the following example, the declared size of input ports a and b is [3:0], but the declaredsize of wires a and b is [4:0]. See lines 2 and 4 (in bold).

module test (a, b, q);input [3:0] a, b;output [3:0] q;wire [4:0] a, b;assign q = a & b;endmodule



VLG5.4

Message

Port size of array instance does not match

Default Severity

Warning

Description

In one or more cases, port sizes of an array instance do not match.

Example

In the following example, output o has a port size of [2:0], but inputs a and b have a portsize of [1:0] for instance array u1[1:0]. See lines 2 and 3.

module test(o,a,b);output [2:0] o;input [1:0] a,b;and u1[1:0] (o,a,b);endmodule



VLG5.5

Message

Named port association ignored for primitive gate

Default Severity

Warning

Description

The checker triggers this rule check when it encounters an internal primitive. This rule checkhelps identify module instances that you should treat as blackboxes.

Example

In the following example, you might want to treat AND as a blackbox. See line 2.

module test4(input aa, bb, output oo);AND u0(oo, aa, bb);

endmodule



VLG5.6

Message

Named port association is ignored for primitive gate

Default Severity

Warning

Description

The checker ignores the named port association for the primitive gate.

Example

In the following example, line 2 uses the named port association:

module test(input aa, bb, output oo);AND u0(.o(oo), .a(aa), .b(bb));

endmodule



VLG6.1

Message

Globally referenced variable is unresolved

Default Severity

Warning

Description

The checker cannot find the globally referenced variable. Thus, the variable remainsunresolved.

Example

In the following example, on line 16 (in bold), the checker cannot find variable x in modulesub. Thus, variable x remains as an undriven net.

module sub (a, b, c);input [7:0] a, b;output [7:0] c;wire [7:0] wiretmp ;

assign wiretmp = a & b;assign c = wiretmp ;endmodule

module main (i1, i2, o1, o2);input [7:0] i1, i2;output [7:0] o1;output o2;

sub inst1 (i1, i2, o1);assign o2= inst1.x;endmodule



VLG6.2

Message

Globally referenced variable resolved

Default Severity

Note

Description

The checker found the globally referenced variable.

Example

In the following example, on line 16 (in bold), the checker finds variable tmp in module sub.

module sub (a, b, c);input [0:0] a, b;output [0:0] c;wire [0:0] tmp ;

assign tmp = a & b;assign c = tmp ;endmodule

module main (i1, i2, o0, o1, o2, o3);input [0:0] i1, i2;output o0;output [0:0] o1, o2, o3;

sub inst1 (.a(i1), .b(i2), .c(o1));assign o2 = inst1.tmp ;endmodule



VLG6.3

MessageUnsupported system function call (converted to 1'b1)

Default Severity

Warning

Description

The checker does not support the $system/$user_pli function calls; instead, the checkerapproximates the $system/$user_pli function call to 1'b1.

Example

In the following example, the checker approximates $random and $time to 1’b1. See lines4 and 5.

module test(aa, bb, o1, o2);input aa, bb;output o1, o2;assign o1 = $random;assign o2 = $time;

endmodule



VLG6.3a

Message

Unsupported system task call

Default Severity

Error

Description

$systemtask(...) is called as a concurrent statement in Verilog.

Note: This check has default error severity level, but you can set it to lower severity level toskip the error checking.

Example

In the following example, concurrent systemtask $mytask is not supported

module m1(aa, bb, oo);input aa, bb;output oo;$mytask(aa, bb, oo);

endmodule



VLG6.4

Message

Supported system datapath function call

Default Severity

Note

Description

The checker triggers this rule check when it encounters any supported datapath functions.Conformal supports the following datapath functions.

$abs()$blend()$carrysave()$compge()$intround()$inttrunc()$lead0()$lead1()$log2()$max()$min()$rotatel()$rotater()$round()$sat()$sgnmult()



VLG6.5

Message

Time literal is unsupported

Default Severity

Warning

Description

The checker does not support time literals, such as 1fs, 2ps, and 3ns, and that it convertedthe time literals to 1’b1.

Example

In the following example, Conformal converts (2ns > 1ns) to (1’b1 > 1’b1). See line 4.

module test5(input aa, bb, output oo);reg oo;always @* begin

if (2ns > 1ns) oo = !aa;else if (aa || bb) oo = aa;else oo = 1’b0;

endendmodule



VLG6.6

Message

Event object is unsupported

Default Severity

Warning

Description

The event object is not supported.

Example

In the following example, -> ev (see line 7) is not supported:

module top (input in, output out);test test1(in, out);endmodulemodule test(input aa, output oo);event ev;always begin-> ev;oo = aa;endendmodule



VLG6.7

Message

Hierarchical function call is not supported (blackboxed)

Default Severity

Warning

Description

The hierachical function call is not supported and will be blackboxed.

Example

In the following example, line 16 shows the unsupported hierachical function call:

module mod1 (input in1, output out1);reg out1;function ftn1;input in1;beginif (in1 == 0) ftn1 = in1;else ftn1 = 1;endendfunctionalways @(in1)out1 = ftn1(in1);endmodulemodule mod2 (input in2, output out2);reg out2;always @(in2)out2 = mod1.ftn1(in2);endmodule



VLG6.8

Message

Specify block is ignored

Default Severity

Ignore

Description

The specify block is ignored. In a design, Verilog specify blocks contain path delay informationthat is not used in static verification. As a result, the contents of a specify block are ignored.Some library cells may have notifier registers used in a specify block that can potentially affectthe logic. Specify blocks are non-synthesizable.

Example

In the following example, specify (line 5) is ignored:module specify_blk ( o, i);input i;output o;buf(o, i);specifyspecparam T1RISE$ = 2.7;( i *> o ) =( 183:311:549 , 179:304:536 );

endspecifyendmodule



VLG6.10

Message

Intra-assignment event specification is not supported

Default Severity

Warning

Description

This construct is not supported because intra-assignment event specifications are notsynthesizable. Cadence recommends that you remodel your HDL source code.

Example

In the following example, the intra-assignment in line 8 is not supported:module intra_assign_evt (clk, cout);input clk;output [3:0] cout;reg [3:0] cout;always @(posedge clk)begin

cout = 4’b0;cout = @(posedge clk) cout + 1;

endendmodule



VLG6.12

Message

fork-join constructs are not supported

Default Severity

Warning

Description

The design includes fork-join constructs. The fork-join constructs cannot be synthesized, andare not supported. To avoid this error, remodel the design.

Example

In the following example, the fork and join contructs (lines 7 and 10) are not supported:module neg_fork_join (clk, cout);input clk;output cout;reg cout;always @(posedge clk)beginfork

cout = 1’b0;cout = 1’b1;

joinend

endmodule



VLG6.13

Message

force-release constructs are not supported

Default Severity

Warning

Description

The design includes force-release constructs. The force-release constructs cannot besynthesized. To avoid this error, remodel your design.

Example

In the following example, the force and release contructs (lines 7 and 10) are not supported:module force_release (clk, cin, cout);input clk;input cin;output cout;reg cout;always @ (posedge clk)begin

force cout = 1’b1; <b>cout = cin;release cout; <b>

endendmodule



VLG6.14

Message

Global reference on the left side of the assignment is not supported

Default Severity

Warning

Description

A global reference on left side of the assignment is not supported.

Example

In the following example, botInst.memNd (line 5) is a global reference on left side of theassignment and is not supported:module test(d);input [1:0] d;bot botInst();always @(d)botInst.memNd[0] = d;

endmodulemodule bot();reg [1:0] memNd [7:0];endmodule



VLG6.15

Message

disable construct is not supported

Default Severity

Warning

Description

The disable construct is supported only when applied to an enclosing named block. TheConformal software cannot disable tasks and non-enclosing named blocks. Remodel thedesign to avoid this error.

Example

In the following example, specify (line 5) is ignored: xxxxxxxxxxxxxxxmodule test;alwaysbegin : breakendendmodulemodule top;test t();integer i;alwaysbeginif (i==1)begin:contdisable top.t.break;

endend

endmodule



VLG6.16

Message

wait construct is not supported

Default Severity

Warning

Description

The design includes a Verilog wait event control, which is not supported. You will need toremodel the design.

Example

In the following example, the wait event control (line 7) is not supported:module neg_wait (enable, a, b, c, d);input enable, b, d;output a, c;reg a, c;always @(enable or b or d)begin

wait (!enable) #10 a = b;#10 c = d;

endendmodule



VLG7

Message

Nets renamed after removing backslash

Default Severity

Warning

Description

The checker has renamed one or more net names. The checker renames all net names thatinclude a backslash (\).

Example

In the following example, net name \out3[0] will be renamed out3[0]1. See line 4 (inbold).

module test ( in1, in2, out3 );output [1:0] out3;input in1, in2;wire \out3[0] ;

assign \out3[0] = in1 & in2;assign out3[1] = \out3[0] ;assign out3[0] = \out3[0] ;

endmodule



VLG8

Message

Buffer inserted

Default Severity

Note

Description

The checker has inserted one or more buffers because the design includes the $setupholdor $recrem timing checks from the Verilog IEEE Std P1364-Y2K.

Example

In the following example, the design uses the $setuphold timing check. See line 11 (inbold).

module test (CK,D,O);output O;reg O;input CK,D;wire D_del,CK_del;buf (CK_del,CK);buf (D_del,D);always @(posedge CK_del)O <= D;specify$setuphold (posedge CK,posedge D, tsu_d_h_ck,th_ck_d_l, notifier,,,CK_del,D_delendspecifyendmodule



VLG9

Message

Names conflict with previous declarations

Default Severity

Warning

Description

The checker found a name conflict among declarations.

Example

In the following example on line 12 (in bold), instance a has the same name as input a at line9 (in bold).

module test (din, dout);input din;output dout;

assign dout=din;endmodule

module top (a , b);input a;output b;

test a (a,b);endmodule



VLG9.1

Message

Text macro is redefined

Default Severity

Warning

Description

The text macro is redefined.

Example

In the following example, val1 is redefined (see line 2):

define val1 0`define val1 1module test (din, dout);input din;output dout;assign dout=din;endmodule



VLG9.2

Message

‘define macro is used

Default Severity

Note

Description

The ‘define macro is used in the Verilog files.

Example

In the following example, ‘define macro is used (see line 1):

`define VALmodule test(in,out);input in;output out;assign out = in;endmodule



VLG9.4

Message

Instance name conflicts with previous declarations

Default Severity

Error

Description

The checker found a name conflict among instance declarations.

Example

In the following example, u0 is redefined (see line 6):

module GCLK (clko, clki, ena);input clki, ena;output clko;not u0 (clki, clki);DLAT l0 (q0, 1’b0, 1’b0, clki_, ena);and u0 (clko, q0, clki);endmodule



VLG10

Message

Non-blocking assignment is in disabled block

Default Severity

Warning

Description

There are non-blocking assignments in a disabled block. These kind of assignments mighthave undefined behavior.

Example

In the following example, the disabled blk1 block contains a non-blocking assignment on line6 (in bold).

module test (clk, a,b);input clk,a;output b;

always @(posedge clk) begin:blk1b <= a;disable blk1;

endendmodule



VLG10.1

Message

Non-blocking assignment encountered in function

Default Severity

Error

Description

Non-blocking assignment was detected inside the function. You should not use non-blockingstatements inside functions. Such usage can lead to compilation failures.

Example

In the following example, get_address (line 12) is a non-blocking assignment:module top (clk, result);input clk;output [3:0] result;reg [3:0] result;reg [1:0] state_var;function [3:0] get_address;input [1:0] state_var;

begincase (state_var)2’b00:beginget_address <= "0000";

endendcase

endendfunctionalways @(posedge clk)beginresult = get_address(2’b0);

endendmodule



VLG10.2

Message

deassign statements cannot be synthesized and are not supported

Default Severity

Warning

Description

The deassign statements cannot be synthesized.

Example

In the following example, the deassign statment in line 13 is not supported:module DeassignMod(a,b);input a;output b;reg b;reg reset, clk;alwaysbeginif(clk)b = a;

else if(reset)b = ~a;

elsedeassign b;endendmodule



VLG10.3

Message

Sequential assign statement is not supported

Default Severity

Warning

Description

Sequential ’assign’ statement is not supported.

Example

In the following example, the sequential assign statment in line 13 is not supported:module assignMod(a,b);input a;output b;reg b;reg reset, clk;alwaysbeginif(clk)b = a;

else if(reset)b = ~a;

elseassign b = 0;endendmodule



VLG11.1

Message

Combinational logic is inferred in an always_latch block

Default Severity

Warning

Description

There is combinational logic inferred in an always_latch block. Latches are expected tohave inferred logic.

Example

In the following example, the always_latch block contains combinational logic on line 7.

module test(a,in1,in2,o);input a;input byte in1, in2;output byte o;

always_latch begino = in1 & in2;

endendmodule



VLG11.2

Message

Latches are inferred in an always_comb block

Default Severity

Warning

Description

This rule check tells that there are inferred latches in an always_comb block. Combinationallogic is expected to have inferred logic.

Example

In the following example, the always_comb block contains an inferred latch on line 7 (inbold).

module test(a,in1,in2,o);input a;input byte in1, in2;output byte o;

always_comb beginif (a)o = in1 & in2;

endendmodule



VLG12.1

Message

Null statement ’;’ is not allowed inside a begin-end block and is ignored

Default Severity

Warning

Description

The null statement ‘:’ is not allowed inside a begin-end block and will be ignored.

Example

In the following example, the extra null statement (line 7) will be ignored.module test(clk, out1, in1);input clk, in1;output out1;reg out1;always @(posedge clk)beginout1 <= in1;;

endendmodule



VLG13.1

Message

Unpacked dimension is not allowed

Default Severity

Warning

Description

The unpacked dimension declaration is not allowed. It is only allowed for SystemVerilog.

Example

In the following example, in line 4, the unpacked dimension for the wire declaration is onlyallowed in SystemVerilog.module test (aa, bb, oo);input aa, bb;output oo;wire tt[1:0];assign tt[0] = aa;assign tt[1] = bb;assign oo = tt[0] && tt[1];endmodule



VLG13.2

Message

Unsized dimension is not allowed

Default Severity

Warning

Description

The unsized dimension is not allowed. Using unsized dimension in an array declaration willcause SystemVerilog module to be blackboxed.

Example

The following SystemVerilog examples are not allowed and will cause modules to beblackboxed:task foo( string arr[] ); // Dynamic array of stringsbit [3:0] nibble[]; // Dynamic array of 4-bit vectorsinteger mem[]; // Dynamic array of integers



VLG13.3

Message

Associative dimension is not allowed

Default Severity

Warning

Description

The SystemVerilog associative dimension is not allowed. Using associative dimension willcause SystemVerilog module to be blackboxed.

Example

The following SystemVerilog examples are not allowed and will cause module to beblackboxed:integer i_array[*]; // associative array of integer (unspecified index)bit [20:0] array_b[string];// associative array of 21-bit vector, indexed by string

event ev_array[myClass]; // associative array of event indexed by class myClass



VLG14.1

Message

Missing module instance name

Default Severity

Error

Description

The instance name is missing for the module.

Example

In the following example, in line 3, the instance name is missing for instantiation of modulesub:module top();wire m, n, k;sub (.o(k), .a(m), .b(n));

endmodule



VLG15.1

Message

Block name is previously declared

Default Severity

Error

Description

Indicates that the block name is previously declared in the same scope.

Example

In the following example, in line 9, block name ’b1’ in redeclared:module test(clk,in, out);input in,clk;output reg out;always @(clk)beginbegin:b1out = in;

endbegin: b1out = ~in;

endendendmodule



VLG16.1

Message

Syntax error in Verilog instantiation

Default Severity

Error

Description

Indicates that a syntax error was found in the Verilog instantiation.

The correct syntax is ’<modname> <mod_instance_name>(...)’.

Example

In the following example, in line 4, the correct syntax is ’test sub(...)’.module top(din, dout);input din;output dout;test sub;endmodule



4Modeling Messages

This chapter lists and describes the modeling messages you encounter when the systemmode changes from Setup to LEC in the Encounter® Conformal® software.


Encounter Conformal Equivalence Checking Reference ManualModeling Messages

F1

MessageModeled multiple-driven net(s)

Description

A multi-driven net has been remodeled into Boolean logic based on how the SET WIRERESOLUTION command is set.

Example

Sample modeling message:

F1: Modeled multiple-driven net(s) (Occurrence: 1)1: /n1 (and)

In this message:

■ /n1 is a multi-driven net

■ (and) indicates that SET WIRE RESOLUTION is set to AND

The following code illustrates a circuit with a net “n1” that has multiple drivers “u0” and “u1”:

not u0 (n1,a);not u1 (n1,b);not u2 (z,n1);

Associated Commands

SET WIRE RESOLUTION



F2

MessageInserted user cut point(s)

Description

Conformal inserted a cut point to break a combinational loop. This operation is enabled whenyou use the ADD CUT POINT command.

Example


F2: Inserted user cut point(s) (Occurrence: 1)1: CUT /n1

In this message:

■ CUT indicates the gate type

■ /n1 indicates the net name

You get this message when you add a cut point at net “n1” using thefollowing command:

add cut point n1 -golden

Circuit example:

mux u0 (n1,n1,d,ck);xor u1 (q,n1);

Associated Commands

ADD CUT POINT



F3

MessageInserted system cut point(s)

Description

A cut point has been inserted automatically to break a combinational loop.

Example


F3: Inserted system cut point(s) (Occurrence: 1)1: MUX /u0

In this message:

■ MUX is the gate type

■ /u0 is the driver instance name

The following circuit example inserts CUT gate at the output of a MUX instance “u0”:




F5

MessageFolded DLAT(s) into DFF(s)

Description

D-latches (DLATs) were folded into D flip-flops (DFFs). This operation is enabled when youuse the SET FLATTEN MODEL -LATCH_FOLD command, which specifies that two latchesthat are in a master-slave configuration should be converted into a single DFF gate. Thisoperation is also affected by the SET FLATTEN MODEL-LATCH_FOLD_MASTER command.

Example


F5: Folded DLAT(s) into DFF(s) (Occurrence: 1)1: /l1 /l0

In this message, /l1 and /l0 are the instance names of the folded DLATs.

You would get this modeling message if you use the following command to convert twomaster-slave DLATs “l0” and “l1” into a DFF:

set flatten model -latch_fold

Circuit example:

not u0 (ck_,ck);DLAT l0 (n1,,1’b0,1’b0,ck_,d);DLAT l1 (q ,,1’b0,1’b0,ck,n1);

Associated Commands

SET FLATTEN MODEL -LATCH_FOLD

SET FLATTEN MODEL -LATCH_FOLD_MASTER



F6

MessageCreated DLAT(s) due to trireg net(s) or combinational loop(s)

Description

A DLAT was created due to trireg net or a series of buffers/inverters that wereimplemented as a bus-holder.

Example


F6: Created DLAT(s) due to trireg net(s) or combinational loop(s)(Occurrence: 1)1: DLAT /n1 due to trireg net

This message indicates that a DLAT was created on net “n1” for trireg, which is illustratedin the following circuit example:

trireg n1;

bufif0 u0 (n1,a,s0);bufif0 u1 (n1,b,s1);buf u2 (z,n1);



F7

MessageSet DLAT data port(s) as ZERO due to disabled clock port(s)

Description

DLAT data ports were set to zero because there were disabled clock ports. This operation isenabled when you use the SET FLATTEN MODEL -LATCH_FOLD command.

Example


F7: Set DLAT data port(s) as ZERO due to disabled clock port(s)(Occurrence: 1)1: Set DLAT ’q_reg’ data port ’/d’ to ZERO due to disabled clock port

This message indicates that data port “d” of register “q_reg” is tied to logic ZERO becauseclock port of register “q_reg” is always disabled (logic ZERO).

You would get this message if you issue the following command:

set flatten model -latch_fold

Circuit example:

and u0 (g,1’b0,ck);

always @(d or g)begin

if (g)q <= d;

end



F8

MessageConverted DLAT(s) to BUF(s) due to transparency

Description

DLATs were converted into buffers because of transparency. This operation is enabled whenyou use the SET FLATTEN MODEL -LATCH_TRANSPARENT command, which specifies thatDLATs should be converted into buffers if the DLAT clock ports are always enabled.

Example


F8: Converted DLAT(s) to BUF(s) due to transparency (Occurrence: 1)1: DLAT /q_reg

This message indicates that a buffer was converted “buf (q,d),” because the clock ofregister “q_reg” is always enabled (logic ONE).


set flatten model -latch_transparent

Circuit example:

or u0 (g,1’b1,ck);always @(d or g)begin

if (g)q <= d;

end

Associated Commands

SET FLATTEN MODEL -LATCH_TRANSPARENT



F10

MessageRemoved redundant AND/NAND/OR/NOR fanin gate(s) for DFF/DLAT(s)

Description

Redundant AND/NAND/OR/NOR fan-in gates for DFFs and DLATs were removed. Thisoperation is enabled when you use the SET FLATTEN MODEL-SEQ_REDUNDANT command.

Example


F10: Removed redundant AND/NAND/OR/NOR fanin gate(s) for DFF/DLAT(s)(Occurrence: 1)1: Removed connection from INV /u0 to AND /u1 for DFF /f0_reg

This message indicates that the fan-in AND “u1” and INV “u0” gates were optimized for DFF“f0_reg” due to redundant logic.

You would get this command if you issue the following command:


Circuit example:

not u0 (rst_,rst);and u1 (sr,set,rst_);DFF f0_reg(q,,sr,rst,ck,d);

Associated Commands

SET FLATTEN MODEL -SEQ_REDUNDANT



F11

MessageRemoved redundant AND/NAND/OR/NOR fanout gate(s) for DFF/DLAT(s)

Description

Redundant AND/NAND/OR/NOR fan-out gates for DFFs and DLATs were removed. Thisoperation is enabled when you use the SET FLATTEN MODEL -SEQ_REDUNDANT command.

Example


F11: Removed redundant AND/NAND/OR/NOR fanout gate(s) for DFF/DLAT(s)(Occurrence: 1)1: Remodeled AND /u0 for DFF /n1_reg

This message indicates that the fan-out AND gate “u0” was optimized for DFF “n1_reg” dueto redundant logic.

You would get this command if you issue the following command:


Circuit example:

always @(posedge ck or negedge rst )begin

if (!rst)n1 <= 0;

elsen1 <= d;

endand u0 (q,n1,rst);

Associated Commands

SET FLATTEN MODEL -SEQ_REDUNDANT



F12

MessageConverted DFF(s) to DLAT(s) due to disabled clock port(s)

Description

DFFs were converted into DLATs due to disabled clock ports. This operation is enabled whenyou use the SET FLATTEN MODEL -DFF_TO_DLAT_ZERO, which converts a DFF to aDLAT when the clock port is zero.

Example


F12: Converted DFF(s) to DLAT(s) due to disabled clock port(s)(Occurrence: 1)1: DLAT /q_reg

This message indicates DFF “q_reg” was converted to a DLAT because the clock of theregister is always disabled (logic ZERO).

You would get this message with the following command:

set flatten model -DFF_TO_DLAT_ZERO

Circuit example:

and u0 (ck1,1’b0,ck);always @(posedge ck1)begin

q <= d;end

Note: The -DFF_TO_DLAT_ZERO option is enabled by default.

Associated Commands

SET FLATTEN MODEL -DFF_TO_DLAT_ZERO



F13

MessageConverted DFF(s) to DLAT(s) due to direct feedback

Description

DFFs were converted to DLATs due to direct feedback. This operation is enabled when youuse the SET FLATTEN MODEL -DFF_TO_DLAT_FEEDBACK command, which converts aDFF to a DLAT if the DFF’s output feeds back directly to the DFF’s input.

Example


F13: Converted DFF(s) to DLAT(s) due to direct feedback(Occurrence: 1)1: DLAT /q_reg

This message indicates that DFF “q_reg” was converted to a DLAT because of directfeedback from output “q” of the register to its input “d”.


set flatten model -DFF_TO_DLAT_FEEDBACK

Circuit example:

always @(posedge ck)beginq <= q;

end

Note: The -DFF_TO_DLAT_FEEDBACK option is enabled by default.

Associated Commands

SET FLATTEN MODEL -DFF_TO_DLAT_FEEDBACK



F14

MessageRemodeled gated-clock DFF(s) or DLAT(s) to mux-feedback

Description

Gated-clock logic for DFFs or DLATs were remodeled to MUX-feedback. This operation isenabled when you run the SET FLATTEN MODEL command with the -GATED_CLOCK option,which remodels gated-clock logic of the clock port of a DFF.

Example


F14: Remodeled gated-clock DFF(s) or DLAT(s) to mux-feedback(Occurrence: 1)1: /q_reg (DFF)

This message indicates that the de-glitch gating clock DLAT “l0” and enable logic “u1” forregister DFF “q_reg” was converted to a mux-feedback DFF

You would get this message when issue the following command:

set flatten model -GATED_CLOCK

Circuit example:

not u0 (ck_,ck);DLAT l0 (en,,1’b0,1’b0,ck_,ena);and u1 (ck1,ck,en);always @(posedge ck1)begin

q <= d;end

Associated Commands

SET FLATTEN MODEL -GATED_CLOCK



F14.1

MessageRemodeled gated-clock DFF(s) or DLAT(s) without latch to mux-feedback

Description

Conformal remodeled gated-clock logic for DFFs or DLATs without deglitching to MUX-feedback. This operation is enabled when you use the SET FLATTEN MODEL-GATED_CLOCK, which remodels gated-clock logic of the clock port of a DFF. This operationmight need the ADD CLOCK command to define the clock pin

Example


F14.1: Remodeled gated-clock DFF(s) or DLAT(s) without latch to mux-feedback(Occurrence: 1)1: /q_reg (DFF)

This message indicates that the gated-clocking enable logic “u1” for register DFF “q_reg”was converted to a mux-feedback DFF.

You get this message when you issue the following commands:

add clock 0 ckset flatten model -GATED_CLOCK

Circuit example:

and u0 (ck1,ck,ena);always @(posedge ck1)beginq <= d;

end

Associated Commands

ADD CLOCK



SET FLATTEN MODEL -GATED_CLOCK



F16

MessageConverted DLAT(s) to MUX(s) due to clock inversion relation

Description

DLATs were converted into MUXes due to clock inversion relationships.

Example


F16: Converted DLAT(s) to MUX(s) due to clock inversion relation(Occurrence: 1)1: /l0

This message indicates that a dual-port DLAT “l0” was converted to a MUX - mux l0(q,d0,d1,ck) due to the clock inversion relationship on the dual-port DLAT clock ports.

Circuit example:

not u0 (ck_,ck);DLAT l0 (q,,1’b0,1’b0,ck_,d0,ck,d1);



F17

MessageConverted DLAT(s) to BUF(s)/INV(s) due to set/reset inversion relation

Description

DLATs were converted to buffers/inverters due to set/reset inversion relationships.

Example


F17: Converted DLAT(s) to BUF(s) due to set/reset inversion relation(Occurrence: 1)1: /l0

This message indicates that a DLAT “l0” was converted to a buffer, buf l0 (q,a),because of set/reset inversion relationships on asynchronous set/reset of DLAT.

Circuit example:

not u0 (a_,a);DLAT l0 (q,,a,a_,ck,1’b0);



F18

MessageConverted DFF/DLAT(s) to ZERO/ONE

Description

Conformal converted a DFF or a DLATs to a ZERO or ONE gate. This operation is enabledwhen you use the SET FLATTEN MODEL -SEQ_CONSTANT command, which converts aDFF or DLAT to a ONE or ZERO gate if the data port is a one or zero. This operation is alsoaffected by the SET FLATTEN MODEL -SEQ_CONSTANT_FEEDBACK command.

Example


F18: Converted DFF/DLAT(s) to ZERO/ONE (Occurrence: 1)1: DFF /n1_reg (ZERO)

This message indicates that DFF “n1_reg” was converted to logic ZERO because data portis tied to logic ZERO.



Circuit example:

always @ (posedge ck)n1 <= 1’b0;assign q = a | n1;

Associated Commands

SET FLATTEN MODEL -SEQ_CONSTANT

SET FLATTEN MODEL -SEQ_CONSTANT_FEEDBACK



F19

MessageMerged DFF(s) or DLAT(s) in clock cones

Description

Sequentially equivalent DFFs or DLATs in clock cones were merged. This operation isenabled when you use the SET FLATTEN MODEL -SEQ_MERGE command.

Example


F19: Merged DFF(s) or DLAT(s) in clock cones (Occurrence: 1)1: DFF /ck0_reg /ck1_reg

This message indicates that DFF “ck0_reg” and DFF “ck_reg” were merged into a singleDFF because the two DFFs were sequentially equivalent.

You would get this message when you issue the following command:


Circuit example:

always @ (posedge ck)begin

ck0 <= a;ck1 <= a;

end

always @ (posedge ck0)q0 <= d;

always @ (posedge ck1)q1 <= d;

Associated Commands

SET FLATTEN MODEL -SEQ_MERGE



F20

MessageMerged DFF(s) or DLAT(s)

Description

Sequentially equivalent DFFs and DLATs were merged. This operation is enabled when youuse the SET FLATTEN MODEL -ALL_SEQ_MERGE command, which merges commongroups of sequential elements into one sequential element in a logic cone of a key point.

Example


F20: Merged DFF(s) or DLAT(s) (Occurrence: 1)1: DFF /q0_reg /q1_reg

This message indicates that DFF “q0_reg” and DFF “q_reg” were merged into a single DFFbecause the two DFFs are sequentially equivalent.

You would get this message if you use the following command:

set flatten model -all_seq_merge

Circuit example:

always @ (posedge ck)beginq0 <= d;q1 <= d;end

Associated Commands

SET FLATTEN MODEL -ALL_SEQ_MERGE



F21

MessageMerged DFF(s) or DLAT(s) defined by user

Description

User-defined DFFs or DLATs were merged using the ADD INSTANCE EQUIVALENCEScommand.

Example


F21: Merged DFF(s) or DLAT(s) defined by user (Occurrence: 1)1: DFF /q0_reg /q1_reg

This message indicates that you merged two DFFs “q0_reg” and DFF “q1_reg” into a singleDFF using the following command:

add instance equivalences /q0_reg /q1_reg -golden

Circuit example:

always @ (posedge ck)beginq0 <= d;q1 <= d;

end

Associated Commands




F23

MessageMerged DFF(s) or DLAT(s) multiple ports into single port due to equivalence

Description

Multiple ports belonging to DFFs or DLATs into one single port due to equivalence weremerged.

Example


F23: Merged DFF(s) or DLAT(s) multiple ports into single port due toequivalence (Occurrence: 1)1: DFF /f0

This message indicates that a dual-port DFF “f0_reg” with equivalent data and clock portwas merged into a single port DFF - DFF f0_reg (q,,1’b0,1’b0,ck,d).

Circuit example:

buf n0 (d0,d);buf n1 (d1,d);DFF f0_reg (q,,1’b0,1’b0,ck,d0,ck,d1);

Associated Commands

None.



F25

MessagePipeline-retimed DFF(s) to outputs

Description

DFFs to outputs were pipeline-retimed. This operation is enabled when you use the ADDMODULE ATTRIBUTE -PIPELINE_RETIME, which checks specified modules for pipelineretiming and remodels when necessary.

Example

Sample modeling messages:

Report modeling message for RevisedF25: Pipeline-retimed DFF(s) to outputs (Occurrence: 1)1: Pipeline retimed DFF ’q_reg’ to output

Report modeling message for RevisedF25: Pipeline-retimed DFF(s) to outputs (Occurrence: 2)1: Pipeline retimed DFF ’a1_reg’ to output2: Pipeline retimed DFF ’b1_reg’ to output

These messages indicate that the DFF “a1_reg” and DFF “b1_reg” performed pipeline-retiming to the outputs.

You would get these messages if you issue the following command:

add module attribute ckt -pipeline_retime

Circuit example:

Golden:assign n1 = a & b;

always @(posedge ck)q <= n1;

Revised:always @(posedge ck)begin



a1 <= a;b1 <= b;

endassign q = a1 & b1;

Associated Commands

ADD MODULE ATTRIBUTE -PIPELINE_RETIME



F26

MessageMerged dual-port DLAT(s) into single port DLAT(s)

Description

Dual-port DLATs were merged into single-port DLATs. This operation is enabled when youuse the SET FLATTEN MODEL -LATCH_MERGE_PORT command.

Example


F26: Merged dual-port DLAT(s) into single port DLAT(s)(Occurrence: 1)1: Merged multi-port DLAT ’/l0’ into single port DLAT

This message indicates that dual-port DLAT “l0” was merged into a single port DLAT usingthe following command:

set flatten model -latch_merge_port

Circuit example:

DLAT l0 (q,,1’b0,1’b0,ck,d0,sck,d1);

Result :

and u0 (n1,d0,ck);and u1 (n2,d1,sck);or u2 (din,n1,n2);or u3 (ck_or,ck,sck);DLAT l0 (q,,1’b0,1’b0,ck_or,din);

Associated Commands

SET FLATTEN MODEL -LATCH_MERGE_PORT



F27

MessageConverted internal input port(s) to inout port(s)

Description

Internal input ports were converted into inout ports because the input port does not drive anyinstances.

Example


F27: Converted internal input port(s) to inout port(s)(Occurrence: 1)1: port /u0/y in module AN2

This message indicates that port “y” of module “AN2” does not drive any load.

Circuit example:

module AN2 (y,z,a,b);input a,b,y;output z;

and u0 (z,a,b);buf u1 (y,a);

endmodule

module ckt (y,z,a,b);input a,b;output y,z;

AN2 u0 (y,z,a,b);

endmodule



F28

MessageConverted internal output port(s) to inout port(s)

Description

Internal output ports were converted to inout ports because the output port is not driven.

Example


F28: Converted internal output port(s) to inout port(s)(Occurrence: 1)1: port /u0/a in module AN3 due to high-impedance (Z) gates

This message indicates that port “a” of module “AN3” is not driven by any driver.

Circuit example:

module AN3 (z,a,b,c);input b,c;output z,a;

and u0 (z,a,b,c);

endmodule

module ckt (z,a,b,c);input a,b,c;output z;

AN3 u0 (z,a,b,c);

endmodule



F30

MessageIgnored weak device(s) due to the existence of strong device(s)

Description

Any weak devices were ignored due to the existence of a stronger device in a multiple-drivennet.

Example


F30: Ignored weak device(s) due to the existence of strong device(s)(Occurrence: 1)1: n1

This message indicates that a weak device buffer “u0” driving net “n1” was ignored due to theexistence of stronger buffer device “u1” driving the same net “n1”.

Circuit example:

buf (weak0,weak1)u0 (n1,a);buf u1 (n1,b);buf u2 (z,n1);



F32

MessageCreated Z gate(s) for floating net(s) and floating pin(s)

Description

Z gates were created for floating nets and floating pins.

Example


F32: Created Z gate(s) for floating net(s) and floating pin(s)(Occurrence: 1)1: c

This message indicates that a net “c” of instance “u0” is not driven.

Circuit example:

module ckt (z,a,b);input a,b;output z;wire c;

and u0 (z,a,b,c);

endmodule



F34

MessageConvert X assignment(s) as don’t care(s)

Description

X assignments were converted to “don’t cares”. This operation is enabled when you use theSET X CONVERSION command.

Example


F34: Convert X assignment(s) as don’t care(s) (Occurrence: 1)1: Converted ’X assignment’ at ’N$1’ be don’t care

This message indicates that assignment in RTL code “default: z = 1’bx” is convertedto don’t cares through the following command:

set x conversion DC -golden

Note: This option in the golden design is enabled by default.

Circuit example:

always @(a or b or sel) begin case (sel) 2’b01 : z = a; 2’b10 : z = b; default : z = 1’bx;endcaseend

Associated Commands

SET X CONVERSION



F34.1

MessageConvert X assignment(s) as zero(s)

Description

X assignments were converted to zero. This operation is enabled when you use the SET XCONVERSION command.

Example


F34.1: Convert X assignment(s) as zero(s) (Occurrence: 1)1: Converted X assignment ’N$1’ as 0

This message indicates that X assignment in RTL code “default: z = 1’bx” wasconverted to logic ZERO using the following command:

set x conversion 0

Circuit example:

always @(a or b or sel)begincase (sel) 2’b01 : z = a; 2’b10 : z = b; default : z = 1’bx;endcase

end

Associated Commands

SET X CONVERSION



F34.2

MessageConvert X assignment(s) as one(s)

Description

X assignments were converted to one. This operation is enabled when you use the SET XCONVERSION command.

Example


F34.2: Convert X assignment(s) as one(s) (Occurrence: 1)1: Converted X assignment ’N$1’ as 1

This message indicates that an X assignment in the RTL code “default: z = 1’bx” wasconverted to logic ONE using the following command:

set x conversion 1

Circuit example:

always @(a or b or sel) begin case (sel) 2’b01 : z = a; 2’b10 : z = b; default : z = 1’bx;

endcaseend

Associated Commands

SET X CONVERSION



F34.3

MessageConverted 1 X assignment(s) as E(s)

Description

An X assignment was converted to an error (E) gate . This operation is enabled when you usethe SET X CONVERSION command. If the X assignment space of the Revised design is withinthe X assignment space of the Golden design, then the E gate is marked as an extraunmapped point (redundant gate).

Example


F34.2: Convert 1 X assignment(s) as E (Occurrence: 1)1: Converted X assignment ’N$1’ as E

This message indicates that an X assignment in the RTL code “default: z = 1’bx” wasconverted to logic E using the following command:

set x conversion E

Circuit example:

always @(a or b or sel) begin case (sel) 2’b01 : z = a; 2’b10 : z = b; default : z = 1’bx;

endcaseend

Associated Commands

SET X CONVERSION



F36

MessageDon’t care(s) added due to $constraint(s)

Description

“don’t cares” were added due to $constraints.

Example


F36: Don’t care(s) added due to $constraint(s) (Occurrence: 1)1: u0: DFF q_reg

This message indicates that constraint “cstr_0” for register “q_reg” is added to don’t cares.

Circuit example:

always @(a or b or sel) begin

case (sel) 2’b01 : z = a; 2’b10 : z = b; default : z = 1’bx; endcase

end$constraint cstr_0 ($one_hot (sel));

always @(posedge ck)q <= z;



F39

MessageAdded output Z gate(s)

Description

Output Z gates were added. This operation is enabled by SET FLATTEN MODEL-OUTPUT_Z, which is enabled by default.

Example


F39: Added output Z gate(s) (Occurrence: 1)1: /z

This message indicates that a Z gate was added at the output “z” using the followingcommand:

set flatten model -output_z

Circuit example:

module ckt (z,a,sel);input a,sel;output z;

bufif0 u0 (z,a,sel);

endmodule

Associated Commands

SET FLATTEN MODEL -OUTPUT_Z



F41

MessageConverted set/reset loop(s) to data-hold(s)

Description

The Conformal software converted a data-hold function that is modeled using anasynchronous set and an asynchronous reset functions, to a mux data-hold function

Example


F41: Converted set/reset loop(s) to data-hold(s) (Occurrence: 1)1: DFF ’Q_reg’

Circuit example:

assign RN = !Q & EN;assign SET = Q & EN;

always @(posedge CK or posedge RN or posedge SET)beginif (RN)Q <= 1’b0;

else if (SET)Q <= 1’b1;

elseQ <= D;

end



F42

MessageUnfolded DFF to latches

Description

A DFF was unfolded into two DLATs. This operation is enabled when you use the REMODEL-UNFOLD_DFF command, which specifies that a DFF should be converted into two DLATsthat are in a master-slave configuration.

Example


F42: Unfolded DFF to latches (Occurrence: 1)1: /q_reg

This message indicates you converted a single DFF into a master-slave DLATs using thefollowing command:

remodel -unfold_dff

Circuit example:

always @(posedge ck)q <= d;

Associated Commands

REMODEL -UNFOLD_DFF



F43

MessageAdded DLATs to cut loops

Description

DLATs were added to cut combination loops.This operation is enabled by the SET FLATTENMODEL command.

Example


F43: Added DLATs to cut loops (Occurrence: 1)1: /u0

This message indicates that a DLAT was added at instance driver “u0” to cut thecombinational loop using the following command:

set flatten model -loop_as_dlat

Circuit example:


Associated Commands

SET FLATTEN MODEL



5Tcl Command Entry Mode Support

Tcl Design Access Commands

■ find on page 865

■ get_compare_points on page 866

■ get_compare_result on page 866

■ get_exit_code on page 867

■ get_current_module on page 868

■ get_fanins on page 868

■ get_fanouts on page 868

■ get_gate_count on page 868

■ get_gate_id on page 868

■ get_gate_type on page 868

■ get_handle_type on page 869

■ get_instances on page 869

■ get_keypoint on page 870

■ get_map_points on page 871

■ get_module_definition on page 871

■ get_names on page 872

■ get_nets on page 872

■ get_parent on page 873

■ get_pins on page 874

■ get_ports on page 875


Encounter Conformal Equivalence Checking Reference ManualTcl Command Entry Mode Support

■ get_primitive_type on page 876

■ get_property on page 877

■ get_root_module on page 878

■ get_unmap_points on page 878

■ set_current_module on page 879

Tcl Utility Commands

■ echo_result on page 879

■ get_license_mode on page 879

■ get_version_info on page 879

■ help on page 880

■ objtype on page 880

■ usage on page 880



findfind <-Module | -Instance | -Port [-Input | -Output | -Bidir]

| -Pin [ -Input | -Output| -Bidir]| -Net | -Gate | -Id>

[-Golden | -Revised | -Both][-Single] <object_name>

Returns a design database object handle or list of handles for a design object or list of objects.

-Module The specified object_name is a module name.

-Instance The specified object_name is an instance name.

-Port The specified object_name is a port name.

-Input specifies an input port.

-Output specifies an output port.

-Bidir specifies a bidirectional port.

-Pin The specified object_name is a pin name.

-Input specifies an input pin.

-Output specifies an output pin.

-Bidir specifies a bidirectional pin.

-Net The specified object_name is a net name.

-Gate Specifies a flattened gate name.

-Id Specifies the ID of a flattened gate.

Note: Conformal automatically assigns ID numbers. They candiffer from one version to another. Always use ID numbersassigned by the Conformal version you are currently running.

-Golden Applies to the Golden design only.

-Revised Applies to the Revised design only.

-Both Applies to the Golden and Revised designs.

-Single Returns none or the first found object handle instead of a list.

<object_name> This is the name of a specified design object. It is a name inmodule context or hierarchical context.

Note: Hierarchical objects start with “/”.



Example

The following example shows how the return value of the command can be saved to avariable for later reference:

set abc1 [find -instance /u1/U2]set abc2 [find -single -instance /u1/U2]

…

get_nets [lindex $abc1 0]get_nets $abc2

get_compare_pointsget_compare_points

[key_point_types] [result_types][sort_type] [-count]

Queries for multiple objects and returns a list of compare point object handles or a count ofthe selected compare points. A compare point handle is a MAP_POINT object handle.

get_compare_resultget_compare_result <obj_handle>

Returns compare results for the specified compare point. The key point is an object handleof the COMPARE_POINT type. The returned result is POS_EQ, NEG_EQ, DIFF,NOT_COMPARED, or ABORT.

key_point_types Specifies the key point type(s), which can be one or more of-PO, -DFF, -DLAT, -BBOX, or -CUT.

result_types Specifies the result type(s), which can be one or more of-POS_EQ, -NEG_EQ, -DIFF, -ABORT, or -UNKNOWN.

sort_type Specifies the sort type, which can be either -Size or-Support.

-count Returns a count of the selected compare points rather than alist of compare point handles.



get_exit_codeget_exit_code

Returns the run status without exiting the Conformal software. The status codes are:

Note: For bits 0, and 2 through 5, once they are set to 1, they will remain at 1. For bit 1, onceit is set to 0, it will remain at 0.

Examples

■ Case 1:

Start Conformal and then exit immediatelyStatus = 2 (00010 in binary). There are no equivalent points since there was nocomparison. Thus, bit 1 is set.

■ Case 2:

Comparison produced a non-equivalent point, an abort point, and an equivalent point.Status = 48 (110000 in binary). Bits 4 and 5 are set to flag the abort and non-equivalentpoints.

■ Case 3:

Comparison produced all non-equivalent points.Status = 18 (010010 in binary). Bits 1 and 4 are set to show two conditions: During thissession, Conformal found no equivalent points and the comparison producednon-equivalent points.

Bit Condition

0 Internal Error

1 Status before comparison

2 Command error

3 Unmapped points or extra POs

4 Non-equivalent points during comparison

5 Abort or uncompared points exist during any comparisons.

6 Abort or uncompared points exist during the last comparision or hierarchicalcomparison.



get_current_moduleget_current_module

Returns the MODULE handle for the current module.

get_faninsget_fanins <obj_handle>

Queries for multiple objects and returns a list of fan-in gate handles for the specified gateobject handle. The type of object handle is a FLAT_GATE.

get_fanoutsget_fanouts <obj_handle>

Queries for multiple objects and returns a list of fan-out gate handles for the specified gateobject handle. The type of object handle is a FLAT_GATE. The syntax is as follows:

get_gate_countget_gate_count [-golden |-revised]

Returns the gate count for the specified design. The default design is Golden.

get_gate_idget_gate_id <obj_handle>

Returns the gate id for the specified flattened gate object handle.

Note: The Conformal software automatically assigns ID numbers. They can differ from oneversion to another. Always use ID numbers assigned by the software version you are running.

get_gate_typeget_gate_type <obj_handle>

Returns the gate type of the specified obj_handle. The type of object handle isFLAT_GATE.



get_handle_typeget_handle_type <obj_handle>

Returns the object type of the specified object handle. The returned result is one of thefollowing strings:

■ MODULE

■ MODULE_INSTANCE

■ MODULE_PORT

■ MODULE_INSTANCE_PIN

■ MODULE_NET

■ HIERARCHY_INSTANCE

■ HIERARCHY_PORT

■ HIERARCHY_INSTANCE_PIN

■ HIERARCHY_NET

■ FLAT_GATE

■ MAP_POINT

get_instancesget_instances [-all_hierarchy] <obj_handle>

Queries for multiple objects and returns a list of instances associated with the specified objecthandle.

-all_hierarchy Use this argument in combination with the HIERARCHY_NETobject handle type. It returns a list of hierarchical instanceobject handles that are associated with the given hierarchicalnet object.



get_keypointget_keypoint [-golden | -revised] <obj_handle>

Returns the key point (FLAT_GATE type) of a specified compare point. The object handle willbe a MAP_POINT type.

<obj_handle> The specified obj_handle as one of the following types:

■ MODULE: lists the instances in the module

■ MODULE_INSTANCE: lists the instance that identifies itself

■ MODULE_PORT: not applicable

■ MODULE_INSTANCE_PIN: lists the instances whose pinsare listed in the specified object handle

■ MODULE_NET: lists the instances that connect with the net

■ HIERARCHY_INSTANCE: lists the hierarchical instance thatidentifies itself

■ HIERARCHY_PORT: lists the hierarchical instance of whichpins include this pin

■ HIERARCHY_INSTANCE_PIN: lists the hierarchicalinstance of which pins include this pin

■ HIERARCHY_NET: lists the hierarchical instances thatconnect with the net in a hierarchical context

■ FLAT_GATE: lists the hierarchical instance that representsthe flattened gate

■ MAP POINT: not applicable



get_map_pointsget_map_points


Queries for multiple objects and returns a list of map point object handles or a count of theselected map points. A map point handle is a MAP_POINT object handle.

get_module_definitionget_module_definition <obj_handle>

Returns a module definition for the specified object handle, where <obj_handle> is one ofthe following types:

■ MODULE: define itself

■ MODULE_INSTANCE: define the module of the specified instance

■ MODULE_PORT: not applicable

■ MODULE_INSTANCE_PIN: not applicable

■ MODULE_NET: not applicable

■ HIERARCHY_INSTANCE: define the module of the specified instance in a hierarchicalcontext.

■ HIERARCHY_PORT: not applicable

■ HIERARCHY_INSTANCE_PIN: not applicable

key_point_types Specifies the key point type(s), which can be one or more of-PO, -DFF, -DLAT, -BBOX, or -CUT.

result_types Specifies the result type(s), which can be one or more of-POS_EQ, -NEG_EQ, -DIFF, -ABORT, or -UNKNOWN.


-count Returns a count of the selected map points rather than a listof map point handles.



■ HIERARCHY_NET: not applicable

■ FLAT_GATE: define the module of the specified flattened gate


get_namesget_names <obj_handles>

Queries for multiple objects and returns a name or list of names for the specified objecthandles.

get_netsget_nets [-all_hierarchy] <obj_handle>

Queries for multiple objects and returns a list of nets for the specified object handle.

-all_hierarchy Use this argument in combination with the HIERARCHY objecthandle type. It returns a list of hierarchical net object handlesthat are associated with the given hierarchical design object (forexample, HIERARCHY_INSTANCE).



get_parentget_parent <obj_handle>

Returns a handle to the parent of the specified object handle, where <obj_handle> is oneof the following types:

■ MODULE: not applicable

■ MODULE_INSTANCE: return the module that contains the specified instance

■ MODULE_PORT: return the module that contains the specified port

■ MODULE_INSTANCE_PIN: return the module that contains the specified pin

■ MODULE_NET: return the module that contains the specified net


■ MODULE: lists the nets of the specified module

■ MODULE_INSTANCE: lists the nets that connect with thespecified instance

■ MODULE_PORT: lists the nets that connect with the specifiedport

■ MODULE_INSTANCE_PIN: lists the nets that connect withthe specified pin

■ MODULE_NET: lists the net that identifies itself

■ HIERARCHY_INSTANCE: lists the nets that connect with thespecified instance in a hierarchical context

■ HIERARCHY_PORT: lists the nets that connect with thespecified port in a hierarchical context

■ HIERARCHY_INSTANCE_PIN: lists the nets that connectwith the specified pin in a hierarchical context

■ HIERARCHY_NET: lists the net that identifies itself

■ FLAT_GATE: lists the nets that connect with the specifiedflattened gate in a hierarchical context




■ HIERARCHY_INSTANCE: return the module definition of the instance

■ HIERARCHY_PORT: return the hierarchical instance that contains the specified port in ahierarchical context

■ HIERARCHY_INSTANCE_PIN: return the hierarchical instance that contains thespecified pin in a hierarchical context

■ HIERARCHY_NET: return the hierarchical instance that contains the specified net in ahierarchical context

■ FLAT_GATE: return the hierarchical instance that contains the specified flattened gate ina hierarchical context


get_pinsget_pins [-all_hierarchy] <obj_handle>

Queries for multiple objects and returns a list of pins associated with the specified objecthandle.

-all_hierarchy Use this argument in combination with the HIERARCHY_NETobject handle type. It returns a list of hierarchical instance pinobject handles that are associated with the given hierarchicalnet object.



get_portsget_ports [-all_hierarchy] <obj_handle>

Queries for multiple objects and returns a list of ports associated with the specified objecthandle.


■ MODULE: lists the pins of the specified module

■ MODULE_INSTANCE: lists the pins of the specified instance

■ MODULE_PORT: lists the pins that connect with the net of thespecified port

■ MODULE_INSTANCE_PIN: lists the pin that identifies itself

■ MODULE_NET: lists the pins that connect with the specifiednet

■ HIERARCHY_INSTANCE: lists the pins of the specifiedinstance in a hierarchical context

■ HIERARCHY_PORT: lists the pins that connect with the netof the specified port in a hierarchical context

■ HIERARCHY_INSTANCE_PIN: lists the nets that connectwith the specified pin in a hierarchical context

■ HIERARCHY_NET: lists the pin that identifies itself

■ FLAT_GATE: lists the pins of the specified flattened gate ina hierarchical context


-all_hierarchy Use this argument in combination with the HIERARCHY_NETobject handle type. It returns a list of hierarchical port objecthandles that are associated with the given hierarchical netobject.



get_primitive_typeget_primitive_type <obj_handle>

Returns the primitive type for the specified instance object handle, where <obj_handle> isone of the following:

■ MODULE_INSTANCE


■ FLAT_GATE


■ MODULE: lists the ports of the specified module

■ MODULE_INSTANCE: lists the ports of the specifiedinstance

■ MODULE_PORT: lists the port that identifies itself

■ MODULE_INSTANCE_PIN: returns the relative port of thespecified pin

■ MODULE_NET: lists the ports that connect with the specifiednet

■ HIERARCHY_INSTANCE: lists the ports of the specifiedinstance in a hierarchical context

■ HIERARCHY_PORT: lists the port that identifies itself

■ HIERARCHY_INSTANCE_PIN: returns the relative port ofthe specified pin in a hierarchical context

■ HIERARCHY_NET: lists the ports that connect with thespecified net in a hierarchical context

■ FLAT_GATE: lists the ports of the specified flattened gate




get_propertyget_property <obj_handle> <property_type>

Returns the property of the specified object handle. The following lists the object handle oneof the following types, with their property types and return values.

■ MODULE

Property Type: BlackBox; Return Value: YES, NO

Property Type: InLib; Return Value: YES, NO

Include the InLib property to test whether the module definition is defined in the libraryspace (YES) or design space (NO)—that is, it tests whether the module definition isimported by the READ LIBRARY or READ DESIGN command.

■ MODULE_INSTANCE

Property Type: Primitive; Return Value: YES, NO

Property Type: CutPoint; Return Value: YES, NO

Include the CutPoint property to test whether the module definition is a cut point—that is,it tests whether you have run the ADD CUT POINT command on this module definition.

■ MODULE_PORT

Property Type: Direction; Return Value: INPUT, OUTPUT, BIDIR

■ MODULE_INSTANCE_PIN


■ MODULE_NET

Property Type: NetType; Return Value: TIE0, TIE1, WAND, WOR, TRI, TRI0, TRI1,TRIAND, TRIOR, TRIREG, REG, GLOBAL, TIEX, TIEZ, WIRE

Note: GLOBAL applies to those signals that cross multiple modules (for example,assertions).



■ HIERARCHY_PORT




■ HIERARCHY_INSTANCE_PIN


■ HIERARCHY_NET

Property Type: NetType; Return Value: TIE0, TIE1, WAND, WOR, TRI, TRI0, TRI1,TRIAND, TRIOR, TRIREG, REG, GLOBAL, TIEX, TIEZ, WIRE

Note: GLOBAL applies to those signals that cross multiple modules (for example,assertions).

■ FLAT_GATE


Property Type: Golden; Return Value: YES, NO

Property Type: Revised; Return Value: YES, NO


Property Type: Result; Return Value: POS_EQ, NEG_EQ, DIFF, ABORT, UNKNOWN

get_root_moduleget_root_module [-golden | -revised]

Returns the name of the root module for the specified design. The default design is Golden.

get_unmap_pointsget_unmap_points


Queries for multiple objects and returns a list of unmap point object handles or a count of theselected unmap points. An unmap point handle is a MAP_POINT object handle.

key_point_types Specifies the key point type(s), which can be one or more of-PI, -PO, -DFF, -DLAT, -BBOX, or -CUT.

result_types Specifies the result type(s), which can be one or more of-Extra, -UNReachable, or -NOTmapped.




set_current_moduleset_current_module <[which_design] module_name | obj_handle>

Changes the current module. By default, the current module is the root module.

echo_resultecho_result [-on | -off]

Turns the command result printing on or off.

get_license_modeget_license_mode

Returns the current license mode. For example, custom, ultra, asic, lp, rcv, verify,and ccd.

get_version_infoget_version_info

Returns a TCL list of the version related info, including version_num, build_date, 32 or64 bit, host name, and platform.

-count Returns a count of the selected unmap points rather than alist of unmap point handles.

which_design Includes one or more of the following options.

Note: which_design is ignored if you use <obj_handle>.

-golden sets the current module for the Golden design. Thisoption is the default value.

-revised sets the current module for the Revised design.

<module_name> The specified name is a module name.

<obj_handle> This argument is a MODULE handle.



helphelp [command_name]

Returns the command usage of the specified command or a list of all Conformal Tclcommands if you do not specify a command.

objtypeobjtype <obj_handle>

Returns the type of an native TCL object, for example string and list, or Conformal designobject handle type (i.e. vpxhandle).

usageusage [-CPU | -MEM]

Displays usage values in Tcl scripts for total CPU run time and peak memory use.



Index

Numerics3-2-1 rule 26

A-all option 30

B-both option 31

Ccase sensitivity

in command syntax 26commands

shorthand for entry 26conventions for syntax 30

Ddirectives

rule check numbers and messages 522

HHELP command 27hierarchical design, naming rules

report 300

MMAN command 27man directory 27messages

generated by HDL (RTL) rule check, see

individual messages 526

Oonline help

Tcl commands 27

Rreports, examples of

environment 300

Sshorthand, for command entry 26SPICE

HDL rules 720syntax

rules 26System Verilog

HDL rules 733

UUNIX commands, using in Conformal

with exclamation (!) point 30with system command 30

usage, command syntax help (Tcl) 27


Conformal Ref

Documents

Transcript of Conformal Ref