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Confirmed

Dual Edge Clocking

Programmable or Variable Burst Length

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United States Patent 6,715,020Farmwald , et al. March 30, 2004

Synchronous integrated circuit device

AbstractA controller device for controlling a synchronous dynamic random access memory device. Thecontroller device includes output driver circuitry to output block size information to the memorydevice. The block size information defines an amount of data to be output by the memory device.In addition, the controller device includes input receiver circuitry to receive the amount of dataoutput by the memory device.

What is claimed is:

1. A controller device for controlling a synchronous dynamic random access memory device, the

controller device comprises: first output driver circuitry to output block size information to thememory device, wherein the block size information defines an amount of data to be output by thememory device; and input receiver circuitry to receive the amount of data output by the memorydevice.

3. The controller device of claim 2 wherein the operation code is included in a packet.

4. The controller device of claim 3 wherein the block size information and the operation code areincluded in the packet.

6. The controller device of claim 2 wherein the first output driver circuitry and the second outputdriver circuitry output address information to the memory device.

7. The controller device of claim 6 wherein the block size information, the address informationand the operation code are output to the memory device via an external bus.

8. The controller device of claim 7 wherein the external bus includes a plurality of signal lines tocarry, in a multiplexed format, the block size information, the operation code and the addressinformation.

9. The controller device of claim 1 further including delay looked loop circuitry, coupled to theinput receiver circuitry, to generate an internal clock signal, wherein the input receiver circuitrysamples the amount of data in response to the internal clock signal.

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10. The controller device of claim 1 further including delay locked loop circuitry, coupled to thefirst output driver circuitry, to generate an internal clock signal, wherein the first output drivercircuitry outputs the block size information synchronously with respect to the internal clock signal.

11. The controller device of claim 10 wherein the delay locked loop circuitry includes at least onevariable delay line used in the generation of the internal clock signal.

12. The controller device of claim 11 wherein the delay locked loop circuitry includes more thanone variable delay line used in the generation of the internal clock signal.

13. The controller device of claim 1 wherein the block size information is a binary code.

14. The controller device of claim 1 wherein the input receiver circuitry samples: a first portion ofthe amount of data during a first half of a clock cycle of an external clock signal; and a secondportion of the amount of data during a second half of the clock cycle of the external clock signal.

15. The controller device of claim 1 wherein the input receiver circuitry samples: a first portion ofthe amount of data in response to a rising edge of an external clock signal; and a second portionof the amount of data in response to a falling edge of the external clock signal.

16. The controller device of claim 1 further including a clock receiver to receive an external clocksignal, wherein, during a clock cycle of an external clock signal, the input receiver receives twobits of data from an external signal line, wherein the two bits of data are included in the amount ofdata output by the memory device.

39. The controller device of claim 38 wherein the operation code is included in a packet.

40. The controller device of claim 39 wherein the block size information and the operation codeare included in the packet.

42. The controller device of claim 38 wherein both the first plurality of output drivers and thesecond plurality of output drivers output address information to the memory device.

43. The controller device of claim 42 wherein the block size information, the operation code, andthe address information are output, in a multiplexed format, to the memory device via an externalbus.

44. The controller device of claim 38 further including a clock receiver to receive an external clocksignal, wherein the first plurality of output drivers outputs the block size information synchronouslywith respect to the external clock signal.

45. The controller device of claim 44 further including a delay locked loop coupled to the clockreceiver and the plurality of input receivers, wherein the delay locked loop generates an internalclock signal, and wherein the plurality of input receivers samples the amount of data in responseto the internal clock signal.

46. The controller device of claim 44 further including a delay locked loop coupled to the firstplurality of output drivers and the clock receiver, wherein the delay locked loop generates aninternal clock signal, and wherein the first plurality of output drivers outputs the block sizeinformation in response to the internal clock signal.

47. The controller device of claim 38 wherein the block size information is a binary code.

48. The controller device of claim 38 further including a clock receiver to receive an external clocksignal, wherein: the plurality of input receivers samples a first portion of the amount of data during

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a first half of a clock cycle of the external clock signal; and the plurality of input receivers samplesa second portion of the amount of data during a second half of the clock cycle of the externalclock signal.

49. The controller device of claim 38 wherein, during a clock cycle of an external clock signal, theplurality of input receivers samples two bits of data of the amount of data output by the memorydevice via an external signal line.

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United States Patent 6,697,295Farmwald , et al. February 24, 2004

Memory device having a programmable register

AbstractThe present invention includes a memory subsystem comprising at least two semiconductordevices, including at least one memory device, connected to a bus, where the bus includes aplurality of bus lines for carrying substantially all address, data and control information needed bysaid memory devices, where the control information includes device-select information and thebus has substantially fewer bus lines than the number of bits in a single address, and the buscarries device-select information without the need for separate device-select lines connecteddirectly to individual devices. The present invention also includes a protocol for master and slavedevices to communicate on the bus and for registers in each device to differentiate each deviceand allow bus requests to be directed to a single or to all devices. The present invention includesmodifications to prior-art devices to allow them to implement the new features of this invention. Ina preferred implementation, 8 bus data lines and an AddressValid bus line carry address, data

and control information for memory addresses up to 40 bits wide.

What is claimed is:

1. A method of operation of a synchronous memory device, wherein the memory device includesan array of memory cells and a programmable register, the method of operation of the memorydevice comprises: sampling a first operation code synchronously with respect to a transition of anexternal clock signal; receiving a binary value synchronously with respect to the external clocksignal, wherein the binary value is representative of a delay time to transpire before the memorydevice is to output data in response to a second operation code, wherein the second operationcode specifies a read operation to the memory device; and storing the binary value in theprogrammable register in response to the first operation code.

2. The method of claim 1 wherein the first operation code is included in a control register accessrequest packet.

3. The method of claim 2 wherein the first operation code and the binary value are included in thesame control register access request packet.

4. The method of claim 1 wherein the delay time is representative of a number of clock cycles ofthe external clock signal.

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5. The method of claim 4 further including: receiving the second operation code; and outputtingthe data, in response to the second operation code, after the number of clock cycles of theexternal clock signal transpire.

6. The method of claim 5 further including sampling address information synchronously withrespect to the external clock signal.

7. The method of claim 6 wherein the address information and the second operation code areincluded in a read request packet.

8. The method of claim 1 further including: receiving block size information, wherein the blocksize information is representative of an amount of data to be output; receiving the secondoperation code; and outputting the amount of data, in response to the second operation code,after the delay time transpires.

9. The method of claim 8 wherein the block size information further defines an amount of data tobe input in response to a third operation code, wherein the third operation code specifies a writeoperation to the memory device, the method further including: receiving the third operation code;and inputting the amount of data in response to the third operation code.

10. The method of claim 9 wherein the third operation code is included in a write request packet.

11. The method of claim 10 wherein the block size information and the third operation code areincluded in the same write request packet.

12. The method of claim 1 further including: receiving the second operation code; and outputtingdata in response to the second operation code, wherein the data is output synchronously withrespect to consecutive rising and falling edge transitions of the external clock signal.

13. The method of claim 1 wherein the first operation code is received during an initializationsequence after power is applied to the memory device.

14. The method of claim 1 wherein the first operation code is sampled from an external bus.

15. The method of claim 14 wherein the external bus includes a plurality of signal lines, andwherein the binary value and the first operation code are multiplexed over the plurality of signallines.

16. A method of controlling a synchronous memory device by a controller, wherein the memorydevice includes an array of memory cells and a programmable register, the method of controllingthe memory device comprises: issuing a first operation code to the memory device, wherein thefirst operation code specifies an access of the programmable register in the memory device inorder to store a binary value, wherein the binary value is representative of control information;and providing the binary value to the memory device, wherein the memory device stores thebinary value in the programmable register in response to the first operation code.

17. The method of claim 16 wherein the control information is representative of a number of clockcycles of an external clock signal to transpire before the memory device outputs data in responseto a second operation code.

18. The method of claim 17 further including: issuing the second operation code to the memorydevice; and receiving data output by the memory device after the number of clock cycles of theexternal clock signal transpire.

19. The method of claim 18 further including providing address information to the memory devicesynchronously with respect to the external clock signal.

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20. The method of claim 19 wherein the address information and the second operation code areincluded in a request packet.

21. The method of claim 16 further including: providing block size information to the memorydevice, wherein the block size information defines an amount of data to be output by the memorydevice in response to a second operation code; issuing the second operation code to the memorydevice; and receiving the amount of data output by the memory device.

22. The method of claim 21 wherein the block size information further defines an amount of datato be input by the memory device in response to a third operation code, the method furtherincluding: issuing the third operation code to the memory device; and providing the amount ofdata to the memory device.

23. The method of claim 16 wherein the first operation code and the binary value are included ina request packet.

24. The method of claim 23 wherein the first operation code and the binary value are included inthe same request packet.

25. The method of claim 16 wherein the first operation code is issued to the memory device viaan external bus.

26. The method of claim 25 wherein the external bus includes a plurality of signal lines, andwherein the binary value and the first operation code are multiplexed over the plurality of signallines.

27. The method of claim 16 wherein the control information includes a device type identifier.

28. The method of claim 16 wherein the control information identifies a location of a defectiveportion of the array of memory cells.

29. The method of claim 16 wherein the control information identifies a range of addressable

locations of the array of memory cells.

30. The method of claim 16 wherein the control information includes a device identification valueto identify the memory device uniquely among a plurality of memory devices.

31. A synchronous memory device including an array of memory cells, the synchronous memorydevice comprising: a clock receiver to receive an external clock signal; a plurality of inputreceivers to sample a first operation code synchronously with respect to a transition of theexternal clock signal; and a programmable register to store a binary value that is representative ofcontrol information, wherein the memory device stores the binary value in the programmableregister in response to the first operation code.

32. The memory device of claim 31 wherein the control information is representative of a number

of clock cycles of the external clock signal to transpire before the memory device outputs data,and wherein the memory device outputs the data in response to a second operation code.

33. The memory device of claim 32 further including a plurality of output drivers to output thedata, after the number of clock cycles of the external clock signal transpire, in response to thesecond operation code.

34. The memory device of claim 31 further including a plurality of output drivers to output data inresponse to a second operation code, wherein the second operation code specifies a readoperation, and wherein the plurality of output drivers output a first portion of the data

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synchronously with respect to a rising edge transition of the external clock signal and output asecond portion of the data synchronously with respect to a falling edge transition of the externalclock signal.

35. The memory device of claim 31 wherein the first operation code is included in a requestpacket.

36. The memory device of claim 31 wherein the first operation code and the binary value areeach included in a request packet.

37. The memory device of claim 36 wherein the first operation code and the binary value areincluded in the same request packet.

38. The memory device of claim 31 wherein the plurality of input receivers are operative toreceive a second operation code, wherein the second operation code specifies a write operationto the memory device, and wherein the memory device further includes additional input receiversto input data in response to the second operation code.

39. The memory device of claim 31 wherein the array of memory cells includes dynamic randomaccess memory cells.

40. The memory device of claim 31 wherein the plurality of input receivers sample the firstoperation code from an external bus.

41. The memory device of claim 40 wherein the external bus includes a plurality of signal lines,and wherein the first operation code and the binary value are multiplexed over the plurality ofsignal lines.

42. The memory device of claim 41 wherein data, the first operation code and the binary valueare multiplexed over the plurality of signal lines.

46. The memory device of claim 45 wherein the programmable register is included in a plurality ofprogrammable registers of the memory device, each register of the plurality of registers to store a

corresponding binary value.

47. The memory device of claim 31 wherein the control information includes a device identifier.

48. The memory device of claim 31 wherein the control information identifies a location of adefective portion of the array of memory cells.

49. The memory device of claim 31 wherein the control information identifies a range ofaddressable locations of the array of memory cells.

50. The memory device of claim 31 wherein the control information includes a deviceidentification value to identify the memory device uniquely among a plurality of memory devices.

51. The memory device of claim 31 further including a plurality of registers, wherein theprogrammable register is included in the plurality of registers, and wherein the plurality ofregisters further includes at least one of: a first register to store a value that identifies the memorydevice uniquely among a plurality of memory devices; a second register to store a value thatidentifies a range of addressable locations of the array of memory cells; and a third register tostore a value that identifies a location of a defective portion of the array of memory cells.

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United States Patent 6,324,120Farmwald , et al. November 27, 2001

Memory device having a variable data output length

AbstractA synchronous memory device and methods of operation and controlling such a device. Themethod of controlling the memory device includes providing block size information to the memorydevice, synchronously with respect to an external clock signal, wherein the block size informationdefines an amount of data to be output by the memory device in response to a read request. Themethod further includes issuing a first read request to the memory device, wherein the memorydevice receives the first read request synchronously with respect to a transition of the externalclock signal.

What is claimed is:

12. The method of claim 1 further including:

receiving a value which is representative of a number of clock cycles of the external clock signalto transpire before the memory device outputs the data; and

receiving a third operation code wherein the third operation code instructs the memory device tostore the value in a programmable register on the memory device.

13. The method of claim 12 wherein the memory device outputs the data on an external bus afterthe number of clock cycles of the external clock signal transpire.

14. The method of claim 12 wherein the external bus includes a plurality of signal lines tomultiplex control information, address information, and the amount of data.

17. The method of claim 15 further including providing a binary value to the memory device,wherein the binary value is representative of a number of clock cycles of the external clock signalto transpire before the memory device outputs the amount of data in response to the firstoperation code

19. The method of claim 15 wherein the first operation code is issued synchronously with respectto a rising or falling edge transition of the external clock signal.

28. The memory device of claim 27 wherein a first portion of the amount of data is outputsynchronously with respect to a rising edge transition of the external clock signal and a second

portion of the amount of data is output synchronously with respect to a falling edge transition ofthe external clock signal.

33. The memory device of claim 29 wherein the first operation code includes prechargeinformation.

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