Concurrent Signal Assignment...
Transcript of Concurrent Signal Assignment...
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RTL Hardware Design Chapter 4 1
Concurrent Signal Assignment
Statements
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RTL Hardware Design Chapter 4 2
Outline
1. Combinational versus sequential circuit
2. Simple signal assignment statement
3. Conditional signal assignment statement
4. Selected signal assignment statement
5. Conditional vs. selected signal assignment
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RTL Hardware Design Chapter 4 3
1. Combinational vs. sequential circuit
• Combinational circuit:
– No internal state
– Output is a function of inputs only
– No latches/FFs or closed feedback loop
• Sequential circuit:
– With internal state
– Output is a function of inputs and internal state
• Sequential circuit to be discussed later
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RTL Hardware Design Chapter 4 4
2. Simple signal assignment
statement
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RTL Hardware Design Chapter 4 5
• Simple signal assignment is a special case
of conditional signal assignment
• Syntax:
signal_name <= projected_waveform;
• E.g.,
y <= a + b + 1 after 10 ns;
• Timing info ignored in synthesis
and δ-delay is used:
signal_name <= value_expression
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RTL Hardware Design Chapter 4 6
• E.g.,
status <= '1';
even <= (p1 and p2) or (p3 and p4);
arith_result <= a + b + c - 1;
• Implementation of last statement
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RTL Hardware Design Chapter 4 7
Signal assignment statement with a
closed feedback loop
• a signal appears in both sides of a
concurrent assignment statement
• E.g.,
q <= ((not q) and (not en)) or (d and en);
• Syntactically correct
• Forms a closed feedback loop
• Should be avoided
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RTL Hardware Design Chapter 4 8
3. Conditional signal assignment
statement
• Syntax
• Examples
• Conceptual implementation
• Detailed implementation examples
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RTL Hardware Design Chapter 4 9
Syntax
• Simplified syntax:signal_name
<= value_expr_1 when boolean_expr_1 else
value_expr_2 when boolean_expr_2 else
value_expr_3 when boolean_expr_3 else
. . .
value_expr_n
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RTL Hardware Design Chapter 4 10
E.g., 4-to-1 mux
• Function table:
a
c
b
s
d
x
2
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RTL Hardware Design Chapter 4 11
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RTL Hardware Design Chapter 4 12
E.g., 2-to-22 binary decoder
• Function table:
s
2
x0x1x2x3
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RTL Hardware Design Chapter 4 13
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RTL Hardware Design Chapter 4 14
E.g., 4-to-2 priority encoder
• Function table:
2r0r1r2r3
code
active
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RTL Hardware Design Chapter 4 15
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RTL Hardware Design Chapter 4 16
E.g., simple ALU
• Function table:
![Page 17: Concurrent Signal Assignment Statementsfpga-fhu.user.jacobs-university.de/wp-content/uploads/2014/09/chap04.pdfSignal assignment statement with a closed feedback loop • a signal](https://reader030.fdocuments.in/reader030/viewer/2022040206/5e032a8fd9e2ea2f204210c1/html5/thumbnails/17.jpg)
RTL Hardware Design Chapter 4 17
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RTL Hardware Design Chapter 4 18
Conceptual implementation
• Syntax:signal_name
<= value_expr_1 when boolean_expr_1 else
value_expr_2 when boolean_expr_2 else
value_expr_3 when boolean_expr_3 else
. . .
value_expr_n;
• Evaluation in descending order
• Achieved by “priority-routing network”
• Top value expression has a “higher priority”
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RTL Hardware Design Chapter 4 19
2-to-1 “abstract” mux
• sel has a data type of boolean
• If sel is true, the input from “T” port is connected to output.
• If sel is false, the input from “F” port is connected to output.
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RTL Hardware Design Chapter 4 20
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RTL Hardware Design Chapter 4 21
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RTL Hardware Design Chapter 4 22
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RTL Hardware Design Chapter 4 23
Detailed implementation examples
• 2-to-1 mux
![Page 24: Concurrent Signal Assignment Statementsfpga-fhu.user.jacobs-university.de/wp-content/uploads/2014/09/chap04.pdfSignal assignment statement with a closed feedback loop • a signal](https://reader030.fdocuments.in/reader030/viewer/2022040206/5e032a8fd9e2ea2f204210c1/html5/thumbnails/24.jpg)
RTL Hardware Design Chapter 4 24
• E.g.,
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RTL Hardware Design Chapter 4 25
• E.g.,
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RTL Hardware Design Chapter 4 26
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RTL Hardware Design Chapter 4 27
• E.g.,
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RTL Hardware Design Chapter 4 28
4. Selected signal assignment
statement
• Syntax
• Examples
• Conceptual implementation
• Detailed implementation examples
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RTL Hardware Design Chapter 4 29
Syntax
• Simplified syntax:
with select_expression select
signal_name <=
value_expr_1 when choice_1,
value_expr_2 when choice_2,
value_expr_3 when choice_3,
. . .
value_expr_n when choice_n;
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RTL Hardware Design Chapter 4 30
• select_expression
– Discrete type or 1-D array
– With finite possible values
• choice_i
– A value of the data type
• Choices must be
– mutually exclusive
– all inclusive
– others can be used as last choice_i
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RTL Hardware Design Chapter 4 31
E.g., 4-to-1 mux
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RTL Hardware Design Chapter 4 32
• Can “11” be used to replace others?
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RTL Hardware Design Chapter 4 33
E.g., 2-to-22 binary decoder
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RTL Hardware Design Chapter 4 34
E.g., 4-to-2 priority encoder
![Page 35: Concurrent Signal Assignment Statementsfpga-fhu.user.jacobs-university.de/wp-content/uploads/2014/09/chap04.pdfSignal assignment statement with a closed feedback loop • a signal](https://reader030.fdocuments.in/reader030/viewer/2022040206/5e032a8fd9e2ea2f204210c1/html5/thumbnails/35.jpg)
RTL Hardware Design Chapter 4 35
• Can we use ‘-’?
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RTL Hardware Design Chapter 4 36
E.g., simple ALU
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RTL Hardware Design Chapter 4 37
E.g., Truth table
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RTL Hardware Design Chapter 4 38
Conceptual implementation
• Achieved by a
multiplexing circuit
• Abstract (k+1)-to-1
multiplexer
– sel is with a data type
of (k+1) values:
c0, c1, c2, . . . , ck
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RTL Hardware Design Chapter 4 39
– select_expression is with a data type of 5
values: c0, c1, c2, c3, c4
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RTL Hardware Design Chapter 4 40
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RTL Hardware Design Chapter 4 41
Detailed implementation examples
• 4-to-1 mux
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RTL Hardware Design Chapter 4 42
• E.g.,
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RTL Hardware Design Chapter 4 43
3. Conditional vs. selected signal
assignment
• Conversion between conditional vs.
selected signal assignment
• Comparison
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RTL Hardware Design Chapter 4 44
From selected assignment to
conditional assignment
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RTL Hardware Design Chapter 4 45
From conditional assignment to
selected assignment
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RTL Hardware Design Chapter 4 46
Comparison
• Selected signal assignment:
– good match for a circuit described by a
functional table
– E.g., binary decoder, multiplexer
– Less effective when an input pattern is given
a preferential treatment
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RTL Hardware Design Chapter 4 47
• Conditional signal assignment:
– good match for a circuit a circuit that needs to
give preferential treatment for certain
conditions or to prioritize the operations
– E.g., priority encoder
– Can handle complicated conditions. e.g.,
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RTL Hardware Design Chapter 4 48
– May “over-specify” for a functional table
based circuit.
– E.g., mux
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RTL Hardware Design Chapter 4 49
Synthesis Guidelines
• No closed feedback loops
• Cond + Sel signal assignments = routing,
not sequential control
• Conditional assignment infers priority
Many statements = long cascading chain
• Selected assignment = multiplexer
Large number of choices = wide MUX