ComputerSystems - Pepperdine Universityesc 001 1011 1b fs 001 1100 1c gs 001 1101 1d rs 001 1110 1e...

16
Computer Systems Fifth edition Documentation for Exam Handouts J. Stanley Warford February 4, 2019

Transcript of ComputerSystems - Pepperdine Universityesc 001 1011 1b fs 001 1100 1c gs 001 1101 1d rs 001 1110 1e...

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Computer SystemsFifth edition

Documentation for Exam Handouts

J. Stanley Warford

February 4, 2019

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Pep/9 Instruction set

Instruction Mnemonic Instruction Addressing StatusSpecifier Mode Bits0000 0000 STOP Stop execution U0000 0001 RET Return from CALL U0000 0010 RETTR Return from trap U0000 0011 MOVSPA Move SP to A U0000 0100 MOVFLGA Move NZVC flags to A⟨12..15⟩ U0000 0101 MOVAFLG Move A⟨12..15⟩ to NZVC flags U

0000 011r NOTr Bitwise invert r U NZ0000 100r NEGr Negate r U NZV0000 101r ASLr Arithmetic shift left r U NZVC0000 110r ASRr Arithmetic shift right r U NZC0000 111r ROLr Rotate left r U C0001 000r RORr Rotate right r U C

0001 001a BR Branch unconditional i, x0001 010a BRLE Branch if less than or equal to i, x0001 011a BRLT Branch if less than i, x0001 100a BREQ Branch if equal to i, x0001 101a BRNE Branch if not equal to i, x0001 110a BRGE Branch if greater than or equal to i, x0001 111a BRGT Branch if greater than i, x0010 000a BRV Branch if V i, x0010 001a BRC Branch if C i, x0010 010a CALL Call subroutine i, x

0010 011n NOPn Unary no operation trap U0010 1aaa NOP Nonunary no operation trap i

0011 0aaa DECI Decimal input trap d, n, s, sf, x, sx, sfx NZV0011 1aaa DECO Decimal output trap i, d, n, s, sf, x, sx, sfx0100 0aaa HEXO Hexadecimal output trap i, d, n, s, sf, x, sx, sfx0100 1aaa STRO String output trap d, n, s, sf, x

0101 0aaa ADDSP Add to stack pointer (SP) i, d, n, s, sf, x, sx, sfx0101 1aaa SUBSP Subtract from stack pointer (SP) i, d, n, s, sf, x, sx, sfx

0110 raaa ADDr Add to r i, d, n, s, sf, x, sx, sfx NZVC0111 raaa SUBr Subtract from r i, d, n, s, sf, x, sx, sfx NZVC1000 raaa ANDr Bitwise AND to r i, d, n, s, sf, x, sx, sfx NZ1001 raaa ORr Bitwise OR to r i, d, n, s, sf, x, sx, sfx NZ

1010 raaa CPWr Compare word to r i, d, n, s, sf, x, sx, sfx NZVC1011 raaa CPBr Compare byte to r⟨8..15⟩ i, d, n, s, sf, x, sx, sfx NZVC1100 raaa LDWr Load word r from memory i, d, n, s, sf, x, sx, sfx NZ1101 raaa LDBr Load byte r⟨8..15⟩ from memory i, d, n, s, sf, x, sx, sfx NZ1110 raaa STWr Store word r to memory d, n, s, sf, x, sx, sfx1111 raaa STBr Store byte r⟨8..15⟩ to memory d, n, s, sf, x, sx, sfx

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Pep/9 RTL specification of the instruction set

Instruction Register transfer language specificationSTOP Stop executionRET PC←Mem[SP] ; SP← SP+2RETTR NZVC←Mem[SP]⟨4..7⟩ ; A←Mem[SP+1] ; X←Mem[SP+3] ; PC←Mem[SP+5] ; SP←Mem[SP+7]MOVSPA A← SPMOVFLGA A⟨8..11⟩ ← 0 , A⟨12..15⟩ ← NZVCMOVAFLG NZVC← A⟨12..15⟩

NOTr r←¬r ; N← r< 0 , Z← r= 0NEGr r←−r ; N← r< 0 , Z← r= 0 , V←{overflow}ASLr C← r⟨0⟩ , r⟨0..14⟩ ← r⟨1..15⟩ , r⟨15⟩ ← 0 ; N← r< 0 , Z← r= 0 , V←{overflow}ASRr C← r⟨15⟩ , r⟨1..15⟩ ← r⟨0..14⟩ ; N← r< 0 , Z← r= 0ROLr C← r⟨0⟩ , r⟨0..14⟩ ← r⟨1..15⟩ , r⟨15⟩ ← CRORr C← r⟨15⟩ , r⟨1..15⟩ ← r⟨0..14⟩ , r⟨0⟩ ← C

BR PC← OprndBRLE N= 1∨Z= 1⇒ PC← OprndBRLT N= 1⇒ PC← OprndBREQ Z= 1⇒ PC← OprndBRNE Z= 0⇒ PC← OprndBRGE N= 0⇒ PC← OprndBRGT N= 0∧Z= 0⇒ PC← OprndBRV V= 1⇒ PC← OprndBRC C= 1⇒ PC← OprndCALL SP← SP−2 ; Mem[SP]← PC ; PC← Oprnd

NOPn Trap: Unary no operationNOP Trap: Nonunary no operation

DECI Trap: Oprnd←{decimal input}DECO Trap: {decimal output}← OprndHEXO Trap: {hexadecimal output}← OprndSTRO Trap: {string output}← Oprnd

ADDSP SP← SP+OprndSUBSP SP← SP−Oprnd

ADDr r← r+Oprnd ; N← r< 0 , Z← r= 0 , V←{overflow} , C←{carry}SUBr r← r−Oprnd ; N← r< 0 , Z← r= 0 , V←{overflow} , C←{carry}ANDr r← r∧Oprnd ; N← r< 0 , Z← r= 0ORr r← r∨Oprnd ; N← r< 0 , Z← r= 0

CPWr T← r−Oprnd ; N← T< 0 , Z← T= 0 , V←{overflow} , C←{carry} ; N← N⊕VCPBr T← r⟨8..15⟩−byte Oprnd ; N← T< 0 , Z← T= 0 , V← 0 , C← 0LDWr r← Oprnd ; N← r< 0 , Z← r= 0LDBr r⟨8..15⟩ ← byte Oprnd ; N← 0 , Z← r⟨8..15⟩= 0STWr Oprnd← rSTBr byte Oprnd← r⟨8..15⟩Trap T←Mem[FFF6] ; Mem[T−1]← IR⟨0..7⟩ ; Mem[T−3]← SP ; Mem[T−5]← PC ; Mem[T−7]← X ;

Mem[T−9]← A ; Mem[T−10]⟨4..7⟩ ← NZVC ; SP← T−10 ; PC←Mem[FFFE]

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Pep/9 ASCII chart

FIGURE A.2 The relationship between hexadecimal and binary.

Char Bin HexNUL 000 0000 00SOH 000 0001 01STX 000 0010 02ETX 000 0011 03EOT 000 0100 04ENQ 000 0101 05ACK 000 0110 06BEL 000 0111 07BS 000 1000 08HT 000 1001 09LF 000 1010 0AVT 000 1011 0BFF 000 1100 0CCR 000 1101 0DSO 000 1110 0ESI 000 1111 0FDLE 001 0000 10DC1 001 0001 11DC2 001 0010 12DC3 001 0011 13DC4 001 0100 14NAK 001 0101 15SYN 001 0110 16ETB 001 0111 17CAN 001 1000 18EM 001 1001 19SUB 001 1010 1AESC 001 1011 1BFS 001 1100 1CGS 001 1101 1DRS 001 1110 1EUS 001 1111 1F

Char Bin HexSP 010 0000 20! 010 0001 21" 010 0010 22# 010 0011 23$ 010 0100 24% 010 0101 25& 010 0110 26' 010 0111 27( 010 1000 28) 010 1001 29* 010 1010 2A+ 010 1011 2B, 010 1100 2C− 010 1101 2D. 010 1110 2E/ 010 1111 2F0 011 0000 301 011 0001 312 011 0010 323 011 0011 334 011 0100 345 011 0101 356 011 0110 367 011 0111 378 011 1000 389 011 1001 39: 011 1010 3A; 011 1011 3B< 011 1100 3C= 011 1101 3D> 011 1110 3E? 011 1111 3F

Char Bin Hex@ 100 0000 40A 100 0001 41B 100 0010 42C 100 0011 43D 100 0100 44E 100 0101 45F 100 0110 46G 100 0111 47H 100 1000 48I 100 1001 49J 100 1010 4AK 100 1011 4BL 100 1100 4CM 100 1101 4DN 100 1110 4EO 100 1111 4FP 101 0000 50Q 101 0001 51R 101 0010 52S 101 0011 53T 101 0100 54U 101 0101 55V 101 0110 56W 101 0111 57X 101 1000 58Y 101 1001 59Z 101 1010 5A[ 101 1011 5B\ 101 1100 5C] 101 1101 5Dˆ 101 1110 5E_ 101 1111 5F

Char Bin Hex‛ 110 0000 60a 110 0001 61b 110 0010 62c 110 0011 63d 110 0100 64e 110 0101 65f 110 0110 66g 110 0111 67h 110 1000 68i 110 1001 69j 110 1010 6Ak 110 1011 6Bl 110 1100 6Cm 110 1101 6Dn 110 1110 6Eo 110 1111 6Fp 111 0000 70q 111 0001 71r 111 0010 72s 111 0011 73t 111 0100 74u 111 0101 75v 111 0110 76w 111 0111 77x 111 1000 78y 111 1001 79z 111 1010 7A{ 111 1011 7B| 111 1100 7C} 111 1101 7D~ 111 1110 7EDEL 111 1111 7F

SOH 000 0001 01 ! 010 0001 21 A 100 0001 41 a 110 0001 61

FIGURE A.3 The American Standard Code for Information Interchange (ASCII).

Hexadecimal Binary

0 0000

1 0001

2 0010

3 0011

Hexadecimal Binary

4 0100

5 0101

6 0110

7 0111

Hexadecimal Binary

8 1000

9 1001

A 1010

B 1011

Hexadecimal Binary

C 1100

D 1101

E 1110

F 1111

784 APPENDIX Pep/9 Architecture

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FIGURE A.4The central processing unit of the Pep/9 computer.

Central processing unit (CPU)

Status bits (NZVC)

Accumulator (A)

Index register (X)

Program counter (PC)

Stack pointer (SP)

Instruction register (IR)

N Z V C

FIGURE A.5The Pep/9 instruction format.

Instructionspecifier

Operandspecifier

(a) The two parts of a nonunary instruction.

(b) A unary instruction.

Instructionspecifier

Abbreviations for Control Characters

NUL null, or all zerosSOH start of headingSTX start of textETX end of textEOT end of transmissionENQ enquiryACK acknowledgeBEL bellBS backspaceHT horizontal tabulationLF line feedVT vertical tabulation

FF form feedCR carriage returnSO shift outSI shift inDLE data link escapeDC1 device control 1DC2 device control 2DC3 device control 3DC4 device control 4NAK negative acknowledgeSYN synchronous idleETB end of transmission block

CAN cancelEM end of mediumSUB substituteESC escapeFS fi le separatorGS group separatorRS record separatorUS unit separatorSP spaceDEL delete

785APPENDIX Pep/9 Architecture

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Pep/9 Addressing modesFIGURE A.4The central processing unit of the Pep/9 computer.

Central processing unit (CPU)

Status bits (NZVC)

Accumulator (A)

Index register (X)

Program counter (PC)

Stack pointer (SP)

Instruction register (IR)

N Z V C

FIGURE A.5The Pep/9 instruction format.

Instructionspecifier

Operandspecifier

(a) The two parts of a nonunary instruction.

(b) A unary instruction.

Instructionspecifier

Abbreviations for Control Characters

NUL null, or all zerosSOH start of headingSTX start of textETX end of textEOT end of transmissionENQ enquiryACK acknowledgeBEL bellBS backspaceHT horizontal tabulationLF line feedVT vertical tabulation

FF form feedCR carriage returnSO shift outSI shift inDLE data link escapeDC1 device control 1DC2 device control 2DC3 device control 3DC4 device control 4NAK negative acknowledgeSYN synchronous idleETB end of transmission block

CAN cancelEM end of mediumSUB substituteESC escapeFS fi le separatorGS group separatorRS record separatorUS unit separatorSP spaceDEL delete

785APPENDIX Pep/9 Architecture

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FIGURE A.4The central processing unit of the Pep/9 computer.

Central processing unit (CPU)

Status bits (NZVC)

Accumulator (A)

Index register (X)

Program counter (PC)

Stack pointer (SP)

Instruction register (IR)

N Z V C

FIGURE A.5The Pep/9 instruction format.

Instructionspecifier

Operandspecifier

(a) The two parts of a nonunary instruction.

(b) A unary instruction.

Instructionspecifier

Abbreviations for Control Characters

NUL null, or all zerosSOH start of headingSTX start of textETX end of textEOT end of transmissionENQ enquiryACK acknowledgeBEL bellBS backspaceHT horizontal tabulationLF line feedVT vertical tabulation

FF form feedCR carriage returnSO shift outSI shift inDLE data link escapeDC1 device control 1DC2 device control 2DC3 device control 3DC4 device control 4NAK negative acknowledgeSYN synchronous idleETB end of transmission block

CAN cancelEM end of mediumSUB substituteESC escapeFS fi le separatorGS group separatorRS record separatorUS unit separatorSP spaceDEL delete

785APPENDIX Pep/9 Architecture

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FIGURE A.6The Pep/9 instruction specifier fields.

Addressing Mode aaa Letters Operand

Immediate 000 i OprndSpec

Direct 001 d Mem[OprndSpec]

Indirect 010 n Mem[Mem[OprndSpec]]

Stack-relative 011 s Mem[SP + OprndSpec]

Stack-relative deferred 100 sf Mem[Mem[SP + OprndSpec]]

Indexed 101 x Mem[OprndSpec + X]

Stack-indexed 110 sx Mem[SP + OprndSpec + X]

Stack-deferred indexed 111 sfx Mem[Mem[SP + OprndSpec] + X]

FIGURE A.7The Pep/9 addressing modes.

Immediate 000 i OprndSpec

aaa Addressing Mode

000 Immediate

001 Direct

010 Indirect

011 Stack-relative

100 Stack-relative deferred

101 Indexed

110 Stack-indexed

111 Stack-deferred indexed

(a) The addressing-aaa fi eld.

a Addressing Mode

0 Immediate

1 Indexed

(b) The addressing-a fi eld.

r Register

0 Accumulator, A

1 Index register, X

(c) The register-r fi eld.

786 APPENDIX Pep/9 Architecture

9781284079630_APPx_783_794.indd 786 29/01/16 8:29 pm

FIGURE A.6The Pep/9 instruction specifier fields.

Addressing Mode aaa Letters Operand

Immediate 000 i OprndSpec

Direct 001 d Mem[OprndSpec]

Indirect 010 n Mem[Mem[OprndSpec]]

Stack-relative 011 s Mem[SP + OprndSpec]

Stack-relative deferred 100 sf Mem[Mem[SP + OprndSpec]]

Indexed 101 x Mem[OprndSpec + X]

Stack-indexed 110 sx Mem[SP + OprndSpec + X]

Stack-deferred indexed 111 sfx Mem[Mem[SP + OprndSpec] + X]

FIGURE A.7The Pep/9 addressing modes.

Immediate 000 i OprndSpec

aaa Addressing Mode

000 Immediate

001 Direct

010 Indirect

011 Stack-relative

100 Stack-relative deferred

101 Indexed

110 Stack-indexed

111 Stack-deferred indexed

(a) The addressing-aaa fi eld.

a Addressing Mode

0 Immediate

1 Indexed

(b) The addressing-a fi eld.

r Register

0 Accumulator, A

1 Index register, X

(c) The register-r fi eld.

786 APPENDIX Pep/9 Architecture

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Pep/9 Memory map

The shaded portion is ROM.

FC52FFFEFC17FFFCFC16FFFAFC15FFF8FC0FFFF6FB8FFFF4

Traphandler

FC52

LoaderFC17

Systemglobals

FC0F

Output portFC16Input portFC15

Systemstack

FB8F

Run-timestack

Heap

Applicationprogram

Globals0000

Opera

ting s

ystem

Appli

catio

n

Mem

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Pep/9 Arithmetic Logic Unit

adder only by the addition of a single control line labeled Sub. When Sub = 0, the circuit acts like an adder. When Sub = 1, the circuit acts like a subtracter.

Figure 10 . 53 (b) is the implementation. With the adder circuit, you only need a half adder for the LSB. Th e adder/subtracter replaces it with a full adder. Consider the situation when Sub = 0. In that case, Cin of the least signifi cant full adder is 0 and it acts like a half adder. Furthermore, the left input of each of the top four XOR gates is also 0, which allows the B signals to pass through them unchanged. Th e circuit computes the sum of A and B.

Now consider the case when Sub = 1. Because the left input of the top four XOR gates is 1, the values of all the bits in B are inverted. Furthermore, Cin of the least signifi cant full adder is 1, adding 1 to the result. Consequently, the sum is the sum of A and the negation of B.

Arithmetic Logic Unit Th e Pep/9 instructions that perform processing include ADDr , ANDr , and ORr . Th e addition is an arithmetic operation, whereas AND and OR are logical operations. Th e CPU typically contains a single combinational circuit called the arithmetic logic unit (ALU) that performs these computations.

FIGURE 10.54 shows the ALU for the Pep/9 CPU. A line with a slash represents more than one control line, with the number by the slash specifying the number of lines. Th e line labeled ALU represents four wires. Th e ALU has a total of 21 input lines—8 lines for the A input, 8 lines for the B input, 4 lines to specify the function that the ALU performs, and the Cin line. It has 12 output lines—8 lines for Result, plus the 4 NZVC values corresponding to Result. Th e carry output line is labeled Cout to distinguish

FIGURE 10 . 54 Block diagram of the Pep/9 ALU.

A B

Cout

Zout

Cin

V

N

ALUALU

4

Result

61710.4 Combinational Devices

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ANDr r ← r ∧ Oprnd ; N ← r < 0 , Z ← r = 0ORr r ← r ∨ Oprnd ; N ← r < 0 , Z ← r = 0

CPWr T ← r − Oprnd ; N ← T < 0 , Z ← T = 0 , V ← {overfl ow} , C ← {carry} ; N ← N ⊕ VCPBr T ← r⟨8..15⟩ − byte Oprnd ; N ← T < 0 , Z ← T = 0 , V ← 0 , C ← 0LDWr r ← Oprnd ; N ← r < 0 , Z ← r = 0LDBr r⟨8..15⟩ ← byte Oprnd ; N ← 0 , Z ← r⟨8..15⟩ = 0STWr Oprnd ← rSTBr byte Oprnd ← r⟨8..15⟩

Trap T ← Mem[FFF6] ; Mem[T − 1] ← IR⟨0..7⟩ ; Mem[T − 3] ← SP ; Mem[T − 5] ← PC ; Mem[T − 7] ← X ; Mem[T − 9] ← A ; Mem[T − 10]⟨4..7⟩ ← NZVC ; SP ← T − 10 ; PC ← Mem[FFFE]

FIGURE A.12 The 16 functions of the Pep/9 ALU.

ALU Control Status Bits

(bin) (dec) Result N Zout V Cout

0000 0 A N Z 0 0

0001 1 A plus B N Z V C

0010 2 A plus B plus Cin N Z V C

0011 3 A plus B plus 1 N Z V C

0100 4 A plus B plus Cin N Z V C

0101 5 A · B N Z 0 0

0110 6 A · B N Z 0 0

0111 7 A + B N Z 0 0

1000 8 A + B N Z 0 0

1001 9 A ⊕ B N Z 0 0

1010 10 A N Z 0 0

1011 11 ASL A N Z V C

1100 12 ROL A N Z V C

1101 13 ASR A N Z 0 C

1110 14 ROR A N Z 0 C

1111 15 0 A<4> A<5> A<6> A<7>

791APPENDIX Pep/9 Architecture

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Pep/9 CPU data section

A0 1

X2 3

SP4 5

PC6 7

IR8

9 10

T111

T212 13

T314 15

T416 17

T518 19

T620 21

0x00M122

0x0123

0x02M224

0x0325

0x04M326

0x0827

0xF0M428

0xF629

0xFEM530

0xFF31

CPU registers

ALU

LoadCk

C5

B5

A5

MARB

MARA

MDR

MDRMux

Mem

Addr

Data

SystemBus

AMux

CMux

CMuxALU

Cin

S

CSMux

C

V

Z

N

SCk

CCk

VCk

ZCk

NCk

Cout

AndZAndZ

CSMux

MemWriteMemRead

0000

MDRMuxAMux

4

Zout

MARCk

MDRCk

BBusABusCBus

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Pep/9 CPU data section with two-byte data bus

ALU

MDREven

MDREMux

AMux

CMux

CMuxALU

Cin

S

CSMux

C

V

Z

N

SCk

CCk

VCk

ZCk

NCk

Cout

AndZAndZ

CSMux

MemWriteMemRead

0000

MDRECk

AMux

4

Zout

MARCk

BBusABusCBus

MARB

MARA

SystemBus

Addr

Data

MDROdd

MDROMux

EOMux

MDREMux

MDROMux

EOMux

MARMux

MARMux

MDROCk

A0 1

X2 3

SP4 5

PC6 7

IR8

9 10

T111

T212 13

T314 15

T416 17

T518 19

T620 21

0x00M122

0x0123

0x02M224

0x0325

0x04M326

0x0827

0xF0M428

0xF629

0xFEM530

0xFF31

CPU registers

LoadCk

C5

B5

A5

Mem

Addr

Data

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Pep/9 System bus protocols

The memory read bus protocol

The bus protocol for a memory read over the Pep/9 system bus requires three consecutive cycles, with MemRead asserted on each cycle.The read operation must adhere to the following specification:

■ You must clock the address into the MAR before the first MemRead cycle.

■ You must clock the data into the MDR from the system bus on or before the third MemRead cycle.

■ On the third MemRead cycle, you cannot clock a new value into MAR in anticipation of a following memory operation.

The memory write bus protocol

The bus protocol for a memory write requires three consecutive cycles, with MemWrite asserted on each cycle. The write operationmust adhere to the following specification:

■ You must clock the address into the MAR before the first MemWrite cycle.

■ On the first or second MemWrite cycle, you can clock the data to be written into the MDR.

■ On the thirdMemWrite cycle, you can clock a new data value into theMDR in anticipation of a followingmemory write. However,you cannot clock a new address value into the MAR in anticipation of a following memory operation.

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MIPS Registers FIGURE 12 . 35 Comparison of the 32-bit MIPS and Pep/9 CPU registers.

(a) MIPS registers.

(b) Pep/9 registers.

0 0x000000001

2345

67

89

1011

12131415

$zero$at

$v0$v1$a0$a1

$a2$a3

$t0$t1$t2$t3

$t4$t5$t6$t7

32

AX

PCSP

16

1617

18192021

2223

24252627

28293031

$s0$s1

$s2$s3$s4$s5

$s6$s7

$t8$t9$k1$k0

$gp$sp$fp$ra

the fi rst byte of each instruction to be stored at an address evenly divisible by four. FIGURE 12.36 shows the von Neumann cycle for the MIPS machine. Th ere is no if statement to determine the size of the instruction.

Figure 12 . 36 shows the von Neumann cycle for MIPS as an endless loop, which is more realistic than the cycle for Pep/9. Real machines have no STOP instruction because the operating system continues to execute when an application terminates.

The Addressing Modes In contrast to Pep/9, which has eight addressing modes, MIPS has the fi ve addressing modes of FIGURE 12.37 . Each of the fi ve addressing modes uses one of the three instruction types—either I-type, R-type, or J-type.

744 CHAPTER 12 Computer Organization

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MIPS Addressing modes

FIGURE 12.38 shows the instruction format for each addressing mode. Instructions with the addressing modes immediate, base, and PC-relative are I-type instructions. Instructions with register addressing are R-type, and instructions with pseudodirect addressing are J-type instructions. A MIPS instruction always consists of a six-bit opcode to specify the instruction and one or more operand specifi ers. Th e rs fi eld, when present, is always at bit location 6..10, the rt fi eld is always at 11..15, and rd is always at 16..20. Th is chapter specifi es bit locations starting with the left most bit as 0 and numbering from left to right to be consistent with Pep/9 notation. Standard MIPS notation is to start with the rightmost bit as 0 and to number from right to left .

MIPS bit numbering notation

do { Fetch the instruction at the address in PC PC ← PC + 4 Decode the instruction specifi er Execute the instruction fetched }while (true)

FIGURE 12 . 36 A pseudocode description of the MIPS von Neumann execution cycle.

Addressing Mode

Instruction Type

Operands

Destination Source Source

Immediate I-type Reg[rt] Reg[rs] SE(im)

Register R-type Reg[rd] Reg[rs] Reg[rt]

Base with load I-type Reg[rt] Mem[Reg[rb] + SE(im)]

Base with store I-type Mem[Reg[rb] + SE(im)] Reg[rt]

PC-relative I-type PC PC + 4 SE(im × 4)

Pseudodirect J-type PC (PC + 4)⟨0..3⟩ : (ta × 4)

Mode Type Destination Source Source

FIGURE 12 . 37 The MIPS addressing modes.

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FIGURE 12 . 38 The MIPS instruction formats corresponding to the addressing modes.

165

32

rsSource register

rtDest register

opOpcode

immediateImmediate

56

(a) Immediate addressing with the I-type instruction.

rsSource register

rtSource register

opOpcode

rdDest register

shamtShift amount

functFunction field

556 55 6

(b) Register addressing with the R-type instruction.

165

rsBase register

rtTarget register

opOpcode

immediateAddress displacement

56

(c) Base addressing with the I-type instruction.

165

rsSource register

rtBranch cond

opOpcode

immediateBranch displacement

56

(d) PC-relative addressing with the I-type instruction.

26

opOpcode

targetTarget address

6

(e) Pseudodirect addressing with the J-type instruction.

Because there are 32 registers in the register bank in Figure 12 . 35 (a), and 2 5 is 32, it takes fi ve bits to access one of them. Th e designations rs, rt, and rd are standard MIPS notations for fi ve-bit register fi elds in an instruction. Figure 12 . 37 shows that rs is always a source register, and rd is always a destination register; but rt, which stands for target register, can be either a source or a destination register. Th e notation Reg in Figure 12 . 37 stands for register and is analogous to Mem, which stands for memory. Reg[r] indicates the content of the register r. For example, if an instruction with immediate addressing executes, Figure 12 . 37 shows Reg[rt] as the destination operand. If the fi ve-bit rt fi eld in Figure 12 . 38 (a) has the value 10011 (bin), which is 19 (dec), then the destination register $s3 will contain the result of the operation because $s3 is register 19 in Figure 12 . 35 .

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MIPS Instruction set

Mnemonic Meaning Binary Instruction Encoding

add Add 0000 00ss ssst tttt dddd d000 0010 0000

addi Add immediate 0010 00ss sssd dddd iiii iiii iiii iiii

sub Subtract 0000 00ss ssst tttt dddd d000 0010 0010

and Bitwise AND 0000 00ss ssst tttt dddd d000 0010 0100

andi Bitwise AND immediate 0011 00ss sssd dddd iiii iiii iiii iiii

or Bitwise OR 0000 00ss ssst tttt dddd d000 0010 0101

ori Bitwise OR immediate 0011 01ss sssd dddd iiii iiii iiii iiii

sll Shift left logical 0000 0000 000t tttt dddd dhhh hh00 0000

sra Shift right arithmetic 0000 0000 000t tttt dddd dhhh hh00 0011

srl Shift right logical 0000 0000 000t tttt dddd dhhh hh00 0010

lb Load byte 1000 00bb bbbd dddd aaaa aaaa aaaa aaaa

lw Load word 1000 11bb bbbd dddd aaaa aaaa aaaa aaaa

lui Load upper immediate 0011 1100 000d dddd iiii iiii iiii iiii

sb Store byte 1010 00bb bbbt tttt aaaa aaaa aaaa aaaa

sw Store word 1010 11bb bbbt tttt aaaa aaaa aaaa aaaa

beq Branch if equal to 0001 00ss ssst tttt aaaa aaaa aaaa aaaa

bgez Branch if greater than or equal to zero 0000 01ss sss0 0001 aaaa aaaa aaaa aaaa

bgtz Branch if greater than zero 0001 11ss sss0 0000 aaaa aaaa aaaa aaaa

blez Branch if less than or equal to zero 0001 10ss sss0 0000 aaaa aaaa aaaa aaaa

bltz Branch if less than zero 0000 01ss sss0 0000 aaaa aaaa aaaa aaaa

bne Branch if not equal to 0001 01ss ssst tttt aaaa aaaa aaaa aaaa

j Jump 0000 10aa aaaa aaaa aaaa aaaa aaaa aaaa

jr Jump register 0000 00bb bbb0 0000 0000 0000 0000 1000

FIGURE 12 . 39 A few instructions from the MIPS instruction set.

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MIPS CPU data section FIGURE 12 . 40 The MIPS data section. Sequential circuits are shaded.

ALU

L1 data cache

16

26

28

4

5

32

32

IFInstruction fetch

IDInstruction decode/register fileread

ExExecute/address calculation

MemMemory access

WBWrite back

JMux

Plus4

ASL2

PC

Decode instruction

Register bank

L1 instruction cache

C

CBus ABus BBus

address

address

A B

Address

Instruction

Address

Data out

Data in

AMux ASL2

Sign extend

Adder

CMux

55

PCMux

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MIPS CPU control signals FIGURE 12 . 41 The control signals from the Decode unit in the MIPS data section.

ALU

L1 data cache

PC

Register bank

L1 instruction cache

C

CBus ABus BBus

A B

Address

Instruction

Address

Data out

Data in

AMux

CMux

PCCk

LoadCk

DCCk

Decode instruction

JMux

PCMux

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MIPS CPU pipelining FIGURE 12 . 43 The MIPS data section with pipelining.

ALU

L1 data cache

IFInstruction fetch

IF/ID registers

IDInstruction decode/register fileread

ID/Ex registers

ExExecute/address calculation

Ex/Mem registers

MemMemory access

WBWrite back

Mem/WB registers

Decode instruction

Register bank

C

CBus ABus BBus

address

A B

Address

Data out

Data in

AMux ASL2

Sign extend

Adder

CMux

JMux

Plus4

ASL2

PC

L1 instruction cache

address

Address

Instruction

PCMux

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