Computer Organization and Design Transistors & Logic - II Montek Singh Wed, Oct 16, 2013 Lecture 10.
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Transcript of Computer Organization and Design Transistors & Logic - II Montek Singh Wed, Oct 16, 2013 Lecture 10.
Computer Organization and Computer Organization and DesignDesign
Transistors & Logic - IITransistors & Logic - II
Montek SinghMontek Singh
Wed, Oct 16, 2013Wed, Oct 16, 2013
Lecture 10Lecture 10
Today’s TopicsToday’s Topics Synthesis using standard gatesSynthesis using standard gates
Truth tablesTruth tables Universal gates: NAND and NORUniversal gates: NAND and NOR Gates with more than 2 inputsGates with more than 2 inputs Sum-of-ProductsSum-of-Products DeMorgan’s LawDeMorgan’s Law
2
Now WeNow We’’re Ready to Design Stuff!re Ready to Design Stuff! We need to start somewhereWe need to start somewhere
usually itusually it’’s the functional specifications the functional specification
A
B YIf C is 1 thencopy B to Y,
otherwise copyA to YC
If you are like most engineers you’d rather see a table, or formula than parse a logic puzzle. The fact is, any combinational function can be expressed as a table.
These “truth tables” are a concise description of the combinational system’s function. Conversely, any computation performed by a combinational system can expressed as a truth table.
C B A Y
0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
Truth Table
We Can Make Most Gates Out of We Can Make Most Gates Out of OthersOthers
How many different gates do we really need?How many different gates do we really need?
AB Y
00 001 110 011 0
B>A
AB
y
AB Y
00 0 01 1 10 1 11 0
XOR
AB
Y
AB
Y
One Will Do!One Will Do! NANDs and NORs are universalNANDs and NORs are universal
one can make one can make anyany circuit out of just NANDs, or just circuit out of just NANDs, or just NORs!NORs!
Ah! But what if we want more than 2-inputs?Ah! But what if we want more than 2-inputs?
=
=
=
=
=
=
Gate TreesGate Trees
Suppose we have some 2-input XOR gates:(same idea holds for AND and OR gates)
And we want an N-input XOR:
A1
A3 A4 AN
A2
A
BC
A0011
B0101
C0110
tpd = 1(latency)
tpd (latency)= O( ___ ) -- WORST CASE.
output = 1 iff number of 1s in input is ODD (“ODD PARITY”)
Can we compute N-input XOR faster?
N
Gate TreesGate Trees
A1
A2
A4
A3
AN
N-input TREE has O( ______ ) levels...
Signal propagation takes O( _______ ) gate delays.
log N
log N
21222
log2N
Design Approach: Sum-of-Design Approach: Sum-of-ProductsProductsThree steps:Three steps:
1.1. Write functional spec as a Write functional spec as a truth tabletruth table
2.2. Write down a Boolean expression for Write down a Boolean expression for every every ‘‘11’’ in the output in the output
3.3. Wire up the gates!Wire up the gates!
This approach will always give us This approach will always give us logic expressions in a particular logic expressions in a particular form: form:
SUM-OF-PRODUCTS (“SOP”)SUM-OF-PRODUCTS (“SOP”) ““SUM” actually means ORSUM” actually means OR ““PRODUCT” actually means ANDPRODUCT” actually means AND
C B A Y
0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
Truth Table
CBAACBBACABCY
Straightforward SynthesisStraightforward Synthesis We can implement SUM-OF-PRODUCTS…We can implement SUM-OF-PRODUCTS…
……with just three levels of logic:with just three levels of logic: INVERTERS/AND/ORINVERTERS/AND/OR
ABC
ABC
ABC
ABC
Y
CBAACBBACABCY
NotationsNotations Symbols and Boolean operators:Symbols and Boolean operators:
DeMorgan’s LawsDeMorgan’s Laws Change ANDs into ORs and vice-versaChange ANDs into ORs and vice-versa
AB=A+B
Useful Gate StructuresUseful Gate Structures NAND-NANDNAND-NAND
NOR-NORNOR-NOR
C
A
B
Y
C
A
BY
C
A
B
Y
zyxxyz
C
A
BY
yxyx
C
A
B
Y
C
A
BY
AB=A+B “Pushing Bubbles”
DeMorgan’s Laws
An Interesting 3-Input Gate: An Interesting 3-Input Gate: MultiplexerMultiplexer Based on C, select the A or B input to be Based on C, select the A or B input to be
copied to the output Y.copied to the output Y.
C B A Y
0 0 0 00 0 1 10 1 0 00 1 1 11 0 0 01 0 1 01 1 0 11 1 1 1
Truth Table
A
BY
C
If C is 1 thencopy B to Y,
otherwise copyA to Y
2-input Multiplexer
B
C
A
Y
“schematic”diagram
A
B
C
0
1
Gatesymbol
Multiplexer (MUX) ShortcutsMultiplexer (MUX) Shortcuts
0101S
0101S
0101S
I0I1
I2I3
Y
S0 S1
A 4-input Mux(implemented as a
tree)
0101S
0101S
A2
B2
A3
B3
Y0
S
0101S
0101S
A0
B0
A1
B1
Y1
Y2
Y3
A 4-bit wide 2-input Mux
ABCDS
0123
YA0-3
B0-3
S
Y0-3
Let’s do some practice Let’s do some practice examplesexamples
On whiteboardOn whiteboard
Next ClassNext Class Arithmetic circuitsArithmetic circuits