Module I (10hours) CPU Arithmetic: Signed addition and subtractionBCD adder Multiplication Array multiplier Booths Algorithm, Division Restoring and non-restoring division.

Module I

CPU Arithmetic: Signed addition and subtractionBCD adder Multiplication Array multiplier Booths Algorithm, Division Restoring and non-restoring division.

Computer OrganizationComputer organizationrefers to the operational units and their interconnection that realize the architecture specification.It defines how the hardware operates.

Computer DesignIt defines the hardware structure of the system.It defines how the hardware is arranged.Computer ArchitectureComputer architectureis a set of disciplines that describes acomputersystem by specifying its parts and their relations.

DIGITAL COMPUTERIt is a digital system that performs various computational tasks.It use binary number system which has only two digits ie..1 and 0.A binary digits is called a bit.Information is represented as a group of bits.A group of 8 bits is called a byte.A computer system is divided into 2 functional entities:HardwareSoftwareA hardware consists of all components and electromechanical devices that comprise the physical entity of a devices.A software consists of instructions or data that the computer manipulate to perform various data processing task.

ProgramA sequence of instructions for the computer to perform a task.Data baseThe memory in which data manipulated by the program is stored.Operating systemIt is the interface between user and the machine.Eg:-Windows.LinuxHardware part of a computer is divided into threeI/O systemMemoryCPUCPU is again divided into 3Register -Stores informationALU -It performs arithmetic and logic operations.Control Unit -It controls the functioning of the system.CPUAcentral processing unit(CPU) (formerly also referred to as acentral processor unit) is thehardwarewithin acomputerthat carries out theinstructionsof acomputer programby performing the basic arithmetical, logical, andinput/outputoperations of the system.CPU

MemoryRAM ROMRAMVolatile.Data can be changedROMNon volatile.Data cannot be changedTranslatorProgram that translates high level language to machine language.Two types:Interpreter compiles line by lineCompiler compiles the code as a whole.InterruptNormal execution of programs may be preempted if some device requires urgent servicing.The normal execution of the current program must be interrupted the device raises an interrupt signal.Interrupt-service routineAfter servicing the interrupt , the execution of the current program is again started.19Bus StructuresThere are many ways to connect different parts inside a computer together.A group of lines that serves as a connecting path for several devices is called a bus.There are different types of buses.Address busData busControl bus

Address Bus

Through the address bus, processor issues the address of the instruction byte or word to the memory system.Through the address bus, processor execution unit, when required, issues the address of the data (byte or word) to the memory system.

Data Bus

When the Processor issues the address of the instruction, it gets back the instruction through the data bus. When it issues the address of the data, it loads the data through the data bus.When it issues the address of the data, it stores the data in the memory through the data bus.

Control Bus

Issues signals to control the timing of various actions during interconnection.Bus signals to synchronize the subsystems.SINGLE BUSIt is also called system bus.Asystem busis a singlecomputer busthat connects the major components of a computer system. The technique was developed to reduce costs and improve modularity. It combines the functions of a data busto carry information, anaddress busto determine where it should be sent, and acontrol busto determine its operation.

All units are connected to a single bus, so it provides the sole means of interconnection. Single bus structure has advantages of simplicity and low cost.Single bus structure has disadvantages of limited speed since usually only two units can participate in a data transfer at any one time. This means that an arbitration system is required and that units will be forced to wait.Only two units can actively use the bus at any given time. Bus control lines are used to arbitrate multiple requests for the use of the bus.Buffer Registersare used to hold information during transfers.

TWO BUS STRUCTURE

In the first configuration, the processor is placed between the I/O unit and the memory unit. The processor is responsible for any data transfer between the I/O unit and the memory unit. The processor acts as a messenger. In this structure, the processor performance and capability is not being maximized. Most of the time, the processor is doing data transfer between these units instead of performing more complex applications. Also, the processor is idle most of the time waiting for these slow devices.

In the second configuration, I/O transfers are made directly to or from the memory. A special purpose processor called peripheral processor or I/O channel is needed as part of the I/O equipment to control and facilitate such transfers. This special processor is the direct memory access(DMA) controller. It allows main memory to perform data transfer between I/O units.

NUMBER REPRESENTATIONThere are three ways for representing numbersSign & magnitude1s complement2s complement In all the 3 systems, the left most bit is zero for +ve numbers and 1 for ve numbers.Sign & MagnitudeIn the sign & magnitude system, the ve values are represented by changing the MSB from 0 to 1.Sign and Magnitude Representation

High order bit is sign: 0 = positive (or zero), 1 = negativeThree low order bits is the magnitude: 0 (000) thru 7 (111)

33331s complementIn this system, -the negative values are obtained by complementing each bit of the corresponding +ve numbers.1s complement of a given number is equivalent to subtracting that number from 2n-1 ie 1111Ones Complement RepresentationSubtraction implemented by addition & 1's complement

36362S COMPLEMENTIt is obtained by adding 1 to the 1s complement of that number.Twos Complement Representation

like 1's compexcept shiftedone positionclockwise3838Addition & Subtraction There are two rules for adding and subtracting 2 binary numbers using 2s complement system.Addition ruleSubtraction ruleAddition ruleTo add 2 numbers, convert the 2 +ve numbers into binary form and omit carry bit. If there is a ve value , convert it into +ve value by finding the 2s complement & add it with the binary form of the other number and discard the carry.Binary form0 00001 00012 00103 00114 01005 01016 01107 01118 1000

Eg: 3 + 5 =8 0 1 1+ 1 0 1 -------- 1 0 0 0Eg: 3 + -5 ie 3-5=-2First find the binary of 3 ie 0011Find the binary of -5 ie 0101 (5) 1s complement of 5 ie 1010 2s complement of 5 ie 1010+1=1011Add 0011 (3) and 1011(-5)=1110 =-2Binary of -2=0010=1101+1=1110

Subtraction Rule

To subtract 2 +ve numbers , convert it into binary form, find the ones complement of the 2nd number and add it to the first number. In the case of a ve number, find the 2s complement of the ve number and then find the 2s complement of that number.Eg: -7 - -5-701111000+11001-501011010+11011 10110100+10101 1 0 0 1+ 0 1 0 1 ------------ 1 1 1 0

Eg: -3- -4-300111100+11101-401001011+1110011000011+10100 1 1 0 1+ 0 1 0 0 ---------- 0 0 0 1The basic operation in all digital computers is addition & subtraction.The arithmetic operations are implemented along with logic function AND,OR,NOT and XOR.The sign numbers are those numbers which has a sign associated with it ie for ve numbers and + for +ve numbers.

Here xi and yi are i/ps.si is the sum and ci is the carry out.Each stage of the addition must accommodate a carry bit.Ci represent carry in to the ith stage.The logic expression for si can be implemented in a 3 i/p XOR gate.The component symbol of a computer circuit for a single stage addition is called a full adder.ADDITION/SUBTRACTION LOGIC

This logic is used to perform the subtraction operation X-Y, ie finding the 2s complement of Y and add it to X .It is used to perform either addition or subtraction based on the value applied to the add/sub input control line.This line is set to 0 for addition, applying the Y vector unchanged to one of the adder inputs along with a carry-in signal,c0.When the add/sub control line is set to 1,the Y vector is 1s complemented by the XOR gates and c0 is set to 1 to complete the 2s complementation of Y.BINARY CODED DECIMAL ADDER(BCD)

BCD of a number is sum of the binary of that number and binary representation of six.Up to 9, BCD and binary representation are same.Above 9,add binary representation of 6 to that digit in binary form.4 bit representation of binary no: is called BCD number.Eg: 131101BCD of 13 1101+ 0110 ______ 10011In BCD numbers are usually represented by 4 bits.BCD represent the decimal range between 0 and 9.A pair of BCD digits can be added to generate a BCD result.A BCD adder is a circuit that adds 2 BCD digits in parallel and produces a sum which is also another BCD number. A BCD adder must include a correction logic in its digital construction. Its purpose is to add 6(0110) to its sum.For this ,a 2nd 4 digit binary adder is used.The two decimal digits together with i/p carry are 1st added in the top 4 bit adder to produce the binary sum. When the o/p carry=0,nothing is added to the binary sum.When it is equal to 1,add 0110 ie 6 is added to the binary sum through the bottom 4 bit binary adder.o/p carry generated from the bottom 4 bit binary adder is ignored.WHAT IS CARRY LOOK AHEAD ADDER ???

A carry-look ahead adder (CLA) is a type of adder used in digital logic to reduce carrypropagation time. Carry-look ahead adderCarry-lookahead logicB cellB cellB cellB cells3P3G3c3P2G2c2s2G1c1P1s1G0c0P0s0.c4x1y1x3y3x2y2x0y0 4-bit carry-look ahead adder61

Problem caused by ripple carry adder

Ripple Carry Adders take the time more to calculate the carry alongside the sum as well as to propagate the carry.Inventors of Carry Look Ahead Adder Charles Babbage first lighted on the problems caused by ripple carry adders. Gerald Rosenberger of IBM first gave a patent of Carry Look Ahead Adders.Propagate & generatePropagate P and Generate G in a CLA is given by,Pi=Ai Bi Gi=Ai Bi

AiBi

PiGiCarry outputsThe Boolean expressions for carry outputs of various stages can be written as follows : C1=G0+P0.C0

C2=G1+G0. P1+C0. P0. P1C3=G2+G1. P2+G0. P1. P2+C0. P0. P1. P2C4=G3+G2. P3+G1. P2. P3+G0. P1. P2. P3+C0. P0. P1. P2. P3Advantage of carry look ahead adder Like ripple carry adder we need not to wait for the propagation of carries to get the sum.

More efficient than carry save adder.

Disadvantage of carry look ahead addersThe disadvantage of CLA is that the carry logic block gets very complicated for more than 4-bits.

MultiplicationMultiplication of unsigned numbersProduct of 2 n-bit numbers is at most a 2n-bit number. Unsigned multiplication can be viewed as addition of shifted versions of the multiplicand.

69Multiplication of unsigned numbers (contd..)We added the partial products at end.Alternative would be to add the partial products at each stage.Rules to implement multiplication are:If the ith bit of the multiplier is 1, shift the multiplicand and add the shifted multiplicand to the current value of the partial product. Hand over the partial product to the next stageValue of the partial product at the start stage is 0.70Combinatorial array multiplierMultiplierMultiplicandm3m2m1m00000q3q2q1q00p2p1p0000p3p4p5p6p7PP1PP2PP3(PP0),Product is: p7,p6,..p0Multiplicand is shifted by displacing it through an array of adders.Combinatorial array multiplier71Multiplication of unsigned numbers

ith multiplier bitcarry incarry outjth multiplicand bitith multiplier bitBit of incoming partial product (PPi)Bit of outgoing partial product (PP(i+1))FATypical multiplication cell72Combinatorial array multiplierCombinatorial array multipliers are:Extremely inefficient.Perform only one function at one time.73Sequential multiplicationRecall the rule for generating partial products:If the ith bit of the multiplier is 1, add the appropriately shifted multiplicand to the current partial product. Multiplicand has been shifted left when added to the partial product.However, adding a left-shifted multiplicand to an unshifted partial product is equivalent to adding an unshifted multiplicand to a right-shifted partial product.74Sequential Circuit Multiplierqn1-mn1-n-bitAdderMultiplicand MControlsequencerMultiplier Q0CShift rightRegister A (initially 0)Add/Noaddcontrolan1-a0q0m00MUXThis circuit performs multiplication by using a single n-bit adder n times to implement the spatial addition performed by the n rows of ripple carry adders.Registers A and Q combined hold PPi while multiplier bit qi generates the signal Add/Noadd. This signal controls the addition of the multiplicand,M,to PPi to generate PP(i+1).The product is computed in n cycles.The product grows in length by one bit per cycle from PP0 .The carry out from the ladder is stored in flip-flop C.At the start, the multiplier is loaded into register Q, the multiplicand into register M and C and A are cleared to 0. At the end of each cycle, C , A and Q are shifted right one bit position to allow the growth of partial product and the multiplier is shifted out of register Q.Because of this shifting , multiplier bit qi appears at the LSB position of Q to generate the Add/ Noadd signal at the correct time.After they are used , the multiplier bits are discarded by the right-shift operation.The carry out from the adder is the leftmost bit of PP(i+1) and it must be held in C which is shifted right with the content of A and Q.After n cycles, the high-order half of the product is held in register A and the lower half is in register Q.Sequential multiplication (contd..)1 1 1 11 0 1 11 1 1 11 1 1 01 1 1 01 1 0 11 1 0 1Initial configurationAddM1 1 0 1CFirst cycleSecond cycleThird cycleFourth cycleNo addShiftShiftAddShiftShiftAdd1 1 1 10001000100 0 0 00 1 1 01 1 0 10 0 1 11 0 0 10 1 0 00 0 0 11 0 0 01 0 0 11 0 1 1QAProduct80Signed Multiplication81

Signed Multiplicationsign extension Sign extension of negative multiplicand.101111110011110110101000111011000000110011100000000110011111Sign extension isshown in blue82Signed MultiplicationFor a negative multiplier, a straightforward solution is to form the 2s-complement of both the multiplier and the multiplicand and proceed as in the case of a positive multiplier.This is possible because complementation of both operands does not change the value or the sign of the product.A technique that works equally well for both negative and positive multipliers Booth algorithm.83Booth Algorithm00010110100000001001101010110101011010101101000000000000000110001010100001+1+1+1+84Booth Algorithm0101011100000000000000000011111110100100000010110100000000011000100100012's complement ofthe multiplicand00001+1-00000000000000000000000000085Booth AlgorithmIn general, in the Booth scheme, -1 times the shifted multiplicand is selected when moving from 0 to 1, and +1 times the shifted multiplicand is selected when moving from 1 to 0, as the multiplier is scanned from right to left.Booth recoding of a multiplier.001101011100110100000000001+1-1-1+1-1+1-1+1-1+86Booth AlgorithmMultiplierBitiBiti1-Version of multiplicandselected by biti010001110 M1+ M1 M0 MBooth multiplier recoding table.XXXX87Booth Algorithm Booth multiplication with a negative multiplier.0101111011000000000000110000011011001110000000100011111110110111010X+11-1-88Booth AlgorithmBest case a long string of 1s (skipping over 1s)Worst case 0s and 1s are alternating

1011100001111100000011110110100011010101010101010000000000000000000001-1-1-1-1-1-1-1-1-1-1-1-1-1-1+1+1+1+1+1+1+1+1+1+1+1+1+Worst-casemultiplierOrdinarymultiplierGoodmultiplier89Integer DivisionManual Division Longhand division examples.11011131426212741000100101010111011111011011000013

1101

91Longhand Division StepsPosition the divisor appropriately with respect to the dividend and performs a subtraction.If the remainder is zero or positive, a quotient bit of 1 is determined, the remainder is extended by another bit of the dividend, the divisor is repositioned, and another subtraction is performed.If the remainder is negative, a quotient bit of 0 is determined, the dividend is restored by adding back the divisor, and the divisor is repositioned for another subtraction.92Circuit ArrangementFigure 6.21. Circuit arrangement for binary division.qn-1Divisor MControlSequencerDividend QShift leftN+1 bit adderq0Add/SubtractQuotientSettingAm00mn-1a0anan-193Restoring DivisionShift A and Q left one binary positionSubtract M from A, and place the answer back in AIf the sign of A is 1, set q0 to 0 and add M back to A (restore A); otherwise, set q0 to 1Repeat these steps n times94Examples10111A restoring-division example.1111101111000100000000000001000001011111010001SubtractShiftRestore100001000011InitiallySubtractShift10111100001100000000SubtractShiftRestore10111010001000011QuotientRemainderShift1011110000SubtractSecond cycleFirst cycleThird cycleFourth cycle00000010110000111000011111Restoreq0Setq0Setq0Setq0Set95Nonrestoring DivisionAvoid the need for restoring A after an unsuccessful subtraction.Any idea?Step 1: (Repeat n times)If the sign of A is 0, shift A and Q left one bit position and subtract M from A; otherwise, shift A and Q left and add M to A.Now, if the sign of A is 0, set q0 to 1; otherwise, set q0 to 0.Step2: If the sign of A is 1, add M to A96Examples A nonrestoring-division example.AddRestore remainderRemainder0000111111000111Quotient001011111000011111Shift0001100001111Add000110000100011101ShiftSubtractInitially000001000111000001110000011000ShiftAdd0010000111101ShiftSubtract000110000Fourth cycleThird cycleSecond cycleFirst cycleq0Setq0Setq0Setq0Set97