Computer Memory Storage Decoding Addressing 1. Memories We've Seen SIMM = Single Inline Memory...
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Transcript of Computer Memory Storage Decoding Addressing 1. Memories We've Seen SIMM = Single Inline Memory...
Computer Memory
Storage
Decoding
Addressing
1
Memories We've Seen
SIMM = Single Inline Memory Module
DIMM = Dual IMM
SODIMM = Small Outline DIMM
RAM = Random Access Memory
SDRAM = Synchronous Dynamic RAM
RDRAM = Direct Rambus DRAM A type of SDRAM
Rambus = The developing company
ROM = Read Only Memory
Some Definitions
DRAM Comparison
Levels of the Memory Hierarchy
5
Part of The On-chip CPU Datapath ISA 16-128 Registers
One or more levels (Static RAM):Level 1: On-chip 16-64K Level 2: On-chip 256K-2MLevel 3: On or Off-chip 1M-16M
Registers
CacheLevel(s)
Main Memory
Magnetic Disc
Optical Disk or Magnetic Tape
Farther away from the CPU:
Lower Cost/Bit
Higher Capacity
Increased AccessTime/Latency
Lower Throughput/Bandwidth
Dynamic RAM (DRAM) 256M-16G
Interface:SCSI, RAID, IDE, 139480G-300G
CPU
Memory Hierarchy Comparisons
6
CPU Registers100s Bytes<10s ns
CacheK Bytes10-100 ns1-0.1 cents/bit
Main MemoryM Bytes200ns- 500ns$.0001-.00001 cents /bitDiskG Bytes, 10 ms (10,000,000 ns)
10 - 10 cents/bit-5 -6
CapacityAccess TimeCost
Tapeinfinitesec-min10 -8
Registers
Cache
Memory
Disk
Tape
Instr. Operands
Blocks
Pages
Files
StagingXfer Unit
prog./compiler1-8 bytes
cache cntl8-128 bytes
OS4K-16K bytes
user/operatorMbytes
faster
Larger
Memory Arrays (Hierarchy)Memory Arrays
Random Access Memory Serial Access Memory Content Addressable Memory(CAM)
Read/Write Memory(RAM)
(Volatile)
Read Only Memory(ROM)
(Nonvolatile)
Static RAM(SRAM)
Dynamic RAM(DRAM)
Shift Registers Queues
First InFirst Out(FIFO)
Last InFirst Out(LIFO)
Serial InParallel Out
(SIPO)
Parallel InSerial Out
(PISO)
Mask ROM ProgrammableROM
(PROM)
ErasableProgrammable
ROM(EPROM)
ElectricallyErasable
ProgrammableROM
(EEPROM)
Flash ROM
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Memory Comparisons
Non-Volatile Memories (ROM / Flash)
Floating-gate transistor
Floating gate
Source
Substrate
Gate
Drain
n+ n+_p
tox
tox
Device cross-section Schematic symbol
G
S
D
9
6T SRAM Cell (6 transistors)
Cell size accounts for most of array size Reduce cell size at expense of complexity
6T SRAM Cell Used in most commercial chips Data stored in cross-coupled inverters
Read: Raise wordline Read bit, bit_b (complement of bit)
Write: Drive complementary data
onto bit, bit_b Raise wordline Bit lines overpower old data
bit bit_b
word
10
1-Transistor DRAM Cell Write: Cs is charged or discharged by asserting WL
and BL Read: Charge redistribution takes place between bit
line and storage capacitance Voltage swing is small; typically around 250 mV
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Read-Write Memories (RAM) Static (SRAM)
Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential
Dynamic (DRAM) Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended
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Connecting Memory
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Up to 2k addressableMDR
MAR
k-bitaddress bus
n-bitdata bus
Control lines
( , MFC, etc.)
Processor Memory
locations
Word length = n bits
WR /
MAR = Memory Address RegisterMDR = Memory Data RegisterMFC = Memory Function Complete signal
Memory Array Architecture 2n words of 2m bits each If n >> m, fold by 2k into fewer rows of more columns
Good regularity – easy to design Very high density if good cells are used
row decoder
columndecoder
n
n-kk
2m bits
columncircuitry
bitline conditioning
memory cells:2n-k rows x2m+k columns
bitlines
wordlines
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Decoders n:2n decoder consists of 2n n-input AND gates
One needed for each row of memory Build AND from NAND or NOR gates
word0
word1
word2
word3
A0A1
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Large Decoders For n > 4, NAND gates become slow
Break large gates into multiple smaller gates
word0
word1
word2
word3
word15
A0A1A2A3
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Column Circuitry Some circuitry is required for each column
Bitline conditioning Sense amplifiers Column multiplexing
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Column Multiplexing Recall that array may be folded for good aspect ratio Ex: 2 kword x 16 folded into 256 rows x 128 columns
Must select 16 output bits from the 128 columns Requires 16 8:1 column multiplexers
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Memory Timing: Approaches
DRAM TimingMultiplexed Adressing
SRAM TimingSelf-timed
Addressbus
RAS
RAS-CAS timing
Row Address
AddressBus
Address transitioninitiates memory operation
Address
Column Address
CAS
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DRAM Timing
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Serial Access Memories Serial access memories do not use an address
Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO)
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Shift Register Shift registers store and delay data Simple design: cascade of registers
Watch your hold times!
clk
Din Dout8
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Serial In Parallel Out 1-bit shift register reads in serial data
After N steps, presents N-bit parallel output
clk
P0 P1 P2 P3
Sin
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Parallel In Serial Out Load all N bits in parallel when shift = 0
Then shift one bit out per cycle
clkshift/load
P0 P1 P2 P3
Sout
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Queues Queues allow data to be read and written at
different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters
(pointers)
Queue
WriteClk
WriteData
FULL
ReadClk
ReadData
EMPTY
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FIFO, LIFO Queues First In First Out (FIFO)
Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer
Last In First Out (LIFO) Also called a stack Use a single stack pointer for read and write
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