Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

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Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236

Transcript of Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Page 1: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Computer Buses

Ref: Burd, Chp 6. 206 – 220

Englander, Chp 7 p 177-183

Chp 8, p 211- 218, 228-236

Page 2: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Outline

Definition of bus

Types of bus lines and their role

Interrupts

Bus standards

Ports

Page 3: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Buses

Data travels between components (CPU, memory & I/O devices) of the computer along communication paths called buses. (Note: can also have buses external to system)

Bus is made up of multiple lines, which may be wires or conductors on a printed board.

Bus may carry data between two components only (point-to-point) or it may be shared between many (multipoint). System bus connects CPU with main memory & other system components.

Page 4: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Buses

Multipoint / system bus

CPU

videocontroller

memory

disk controller

Point-to pointbus

ALU

Control unit

Buses may be serial (one bit at time) or parallel (multiple bits at time. Most internal buses are parallel, most external are serial.

Page 5: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Bus LinesBus lines classified as data, address, control and

power lines. Depending on the function of the bus, it may have all or some of these types.

Current system bus may have >100 lines, including all 4 types

Data lines provide path for moving data (including instructions) between system components. It’s width usually same or multiple of CPU word size (eg 64 bit CPU usually has 64 or 128 bit data bus) to enhance system performance

Page 6: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

MEMORY LOCATIONS

00

01

10

11

1 or 0

1 or 0

Possible combinations = 4 (or 22 )

00, 01, 10, 11

2 line addressBUS

Address lines used by the CPU to carry a digital code which uniquely identifies each memory location and I/O port. It’s size dictates maximum addressable memory. eg 8 bit address bus allows only 28 memory locations

Page 7: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Evolution of Intel Microprocessor

Name: 8080 80286 80386 Pentium PII

Year: 1974 1980 1985 1993 1997

Data Bus 8 16 32 64 64

Address 20 24 32 32 36

bus width

Addressable 1MB 16MB 4GB 4GB 64G

Memory

Page 8: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Bus lines

Control lines include

memory read/write & I/O read/write transfer acknowledge bus request/grant interrupt request/acknowledge clock used to synchronize operations

Control signals necessary to effectively share bus, but may consume many bus cycles => bus protocols designed to minimize these.

Page 9: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

CONTROLLINES

ADDRESSLINES

bus request

write

1

1

1000

When request granted, puts module address on address lines, and transfers data via data bus lines.

1101

DATA LINES

For module to send data to another, must obtain use of bus by sending bus request signal on control line

Page 10: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Bus Speed

Bus clock speed and data bus width together determine theoretical max data transfer rate of bus eg 64 bits * 100 mhz.

However, actual speeds are much less than this due to reliability problems caused by with electrical interference, slow peripheral devices etc.

Power lines carry electrical power to the module they are communicating with.

Page 11: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Interrupts

An interrupt is a signal that interrupts normal processing of CPU to indicate some event has occurred. It may be come from several sources:

I/O device ( e.g keyboard, printer, disk drive) timer (running from system clock) program (software interrupt) hardware failure (eg memory error)

Interrupts carried on special bus control lines to cpu, eg in pcs ~ 15 lines, IRQ1,IRQ8 etc

Page 12: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Interrupts

Interrupt Handlers are operating system service routines used to process each interrupt. They are loaded into memory at start up.

Interrupts are assigned priorities to allow some interrupts (eg hardware failure) to take precedence over less important ones.

I/O device controllers use interrupts to communicate with cpu as these devices are so slow compared to cpu.

Page 13: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

START

Execute the Instruction

Fetch the next instruction

Check for interrupt, process if req’d.

Interrupts enabled

Interrupts disabled

Fetch/Execute/InterruptCycle

Page 14: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Bus Standards

Many different standards (protocols) for BUS architecture

Standard specifies format & meaning of messages sent across bus

A computer system will contain multiple diff bus types, with some interconnected to form backplane or system bus.

Bus controller (bus interface unit) used to interconnect different bus types by converting signals to correct format.

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BUS standardsISA . Was standard system bus- initially 8 bit, then

16 bit when AT (286) introduced. Latest version – EISA is 32 bit. Still used to connect slow I/O devices

As processor speed and need for high volume high speed data transfer increase, bus can cause serious bottlenecks in I/O processing. One solution is Local BUS dedicated to input/output devices.

PCI is recent 32 (or 64) bit Local BUS standard used to connect many fast I/O devices. It multiplexes data & addresses on same lines

AGP - graphics only internal bus

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External bus standards

USB - recent standard for external serial bus with high throughput, allows daisychaining (up to 127 devices). Eliminates need for separate serial and parallel ports for common devices.

SCSI bus family - use a specialized parrallel port, that can accept and provide addressing for multiple different devices such as disk drives, CD-ROMs, scanners at very high data rates.

IEEE FireWire - extremely high speed external bus, developed for peripherals such as video cameras

Page 17: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Ports

Many I/O devices connect into bus via standard interface called a port. An I/O port is a connector at end of bus into which device can be plugged.

Older I/O ports were low speed, still in limited use Serial (e.g RS-232, 25 pin tech. spec, used for

mouse, modem,network interface) one bit at a time, over one line.

Parrallel (e.g. Centronics, used for printers) multiple bits at a time, over multiple lines.

Newer ports, eg USB port handle multiple devices and much higher data throughput

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Storage Device Controllers

Storage & I/O devices connected to system bus through a device controller.

Device Controller : implements bus interface standard. translates commands from cpu into device-specific

format Allows multiple devices to share bus connection

EIDE and SCSI controllers are complex devices with on-board processor, able to control large range of devices – disk, tape, CD, DVD drives.

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Technology Focus

Page 20: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

Bus Interface units

Systems frequently have many different types of buses within the one system.

The bus interface unit provides the translation mechanism for moving data from one type of bus to another.

Page 21: Computer Buses Ref: Burd, Chp 6. 206 – 220 Englander, Chp 7 p 177-183 Chp 8, p 211- 218, 228-236.

CPU MEMORY

VideoAdapter

SCSI Diskcontroller

CPU BUS

Serial Port Interface

Parallel Port Interface

bus interface

PCI BUS

bus interface

ISA BUS

modemprinter

bus interface

AGP BUSUSB Port Interface