Computer Architecture - ocw.snu.ac.krocw.snu.ac.kr/sites/default/files/NOTE/7105.pdf · Computer...
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Computer Architecture Multi-cycle Implementation
Transcript of Computer Architecture - ocw.snu.ac.krocw.snu.ac.kr/sites/default/files/NOTE/7105.pdf · Computer...
Computer Architecture
Multi-cycle Implementation
Computer Architecture & Network Lab 2
Outline
Disadvantages of the Single-cycle implementation Long cycle time, too long for all instructions except for the slowest
(lw instruction) Inefficient hardware utilization with unnecessarily duplicated
resources Multi-cycle implementation
Partition execution into small steps Process each step in one cycle Different numbers of cycles for different instructions
− Example R-format instruction (4 cycles): (1) Instruction fetch (2) Instruction decode/register
fetch (3) ALU operation (4) Register write Load instruction (5 cycles): (1) Instruction fetch (2) Instruction decode/register fetch
(3) address computation (4) memory read (5) Register write
Computer Architecture & Network Lab 3
Multiple-cycle Concept
Reduce resource requirements by using the same resource for different purposes during different cycles Single memory unit for instructions and data Single ALU
Use temporary registers to store intermediate results during execution Instruction register (IR), A register, B register, ALUOut
register, Memory data register (MDR) Partition criteria: at most one of the following operations
Memory access Register file access ALU operation
Computer Architecture & Network Lab 4
Multiple-cycle Datapath
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 5
Overview of Multi-cycle Execution
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 6
Instruction Fetch Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 7
Instruction Fetch Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 8
Instruction Decode/Register Fetch Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 9
Instruction Decode/Register Fetch Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 10
R-format Execution Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 11
R-format Execution Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 12
R-format Completion Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 13
R-format Completion Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 14
Load/Store Address Computation Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 15
Load/Store Address Computation Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 16
Load Memory Access Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 17
Load Memory Access Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 18
Load Completion Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 19
Load Completion Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 20
Store Memory Access Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 21
Store Memory Access Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 22
Branch Completion Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 23
Branch Completion Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 24
Jump Completion Step
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 25
Jump Completion Step
PC
Address
MemData
memory
Read data 1
Read data 2
Registers
0MUX1
Write data
ALUZeroALU
result
0MUX1
Writedata
0MUX1
Shift left 2
MUX
0123
0MUX1
A
B
MemoryData
Register
Instruction[31-26]
Instruction[25-21]
Instruction[20-16]
Instruction[15-0]
Instructionregister
Signextend
ALUOut
MUX
0
1
2
Readregister1
Readregister2
Writeregister
4
Shift left 2
Instruction[15-0]
Instruction[15-11]
16 32
26 28
PC[31-28]
Jumpaddress[31-0]Instruction[25-0]
Computer Architecture & Network Lab 26
Summary of Multi-cycle Steps
Step nameAction for R-type
instructionsAction for memory-reference
instructionsAction forbranches
Action forjumps
Instruction fetch IR = Memory[PC]PC = PC + 4
Instruction A = Reg [IR[25-21]]decode/register fetch B = Reg [IR[20-16]]
ALUOut = PC + (sign-extend (IR[15-0]) << 2)Execution, address ALUOut = A op B ALUOut = A + sign-extend if (A ==B) then PC = PC [31-28] IIcomputation, branch/ (IR[15-0]) PC = ALUOut (IR[25-0]<<2)jump completionMemory access or R-type Reg [IR[15-11]] = Load: MDR = Memory[ALUOut]completion ALUOut or
Store: Memory [ALUOut] = B
Memory read completion Load: Reg[IR[20-16]] = MDR
Computer Architecture & Network Lab 27
CPI of the Multi-cycle Implementation
Number of clock cycles Loads : 5 Stores : 4 R-format instructions : 4 Branches : 3 Jumps : 3
Instruction mix 22% loads, 11% stores, 49% R-format instructions, 16%
branches, and 2% jumps CPI = 0.22 x 5 + 0.11 x 4 + 0.49 x 4 + 0.16 x 3 + 0.02 x 3 = 4.04
Computer Architecture & Network Lab 28
Multiple-cycle Implementation (with control signals added)
Computer Architecture & Network Lab 29
Finite State Machine
Finite state machine There are a finite set of possible machine states The machine has two functions
−next state function dependent on current state and input values−output function dependent on current state and input values
Two kinds of state machines−Moore machine has output based only on current state−Mealy machine has output based on current state and input values−We use a Moore machine
Current state Next-statefunction
Outputfunction
Nextstate
Inputs
Outputs
Clock
Computer Architecture & Network Lab 30
High-Level Control Flow
Common 2-clock sequence to fetch/decode any instruction Separate sequence of 1 to 3 clocks to execute specific types
of instruction
Computer Architecture & Network Lab 31
Finite State Machine Diagram
PCWritePCSource = 10
ALUSrcA = 1ALUSrcB = 00ALUOp = 01PCWriteCond
PCSource = 01
ALUSrcA =1ALUSrcB = 00ALUOp= 10
RegDst = 1RegWrite
MemtoReg = 0MemWriteIorD = 1
MemReadIorD = 1
ALUSrcA = 1ALUSrcB = 10ALUOp = 00
RegDst=0RegWrite
MemtoReg=1
ALUSrcA = 0ALUSrcB = 11ALUOp = 00
MemReadALUSrcA = 0
IorD = 0IRWrite
ALUSrcB = 01ALUOp = 00
PCWritePCSource = 00
Instruction fetchInstruction decode/
register fetch
Jumpcompletion
BranchcompletionExecution
Memory addresscomputation
Memoryaccess
Memoryaccess R-type completion
Write-back step
(Op
=' J'
)
(Op
=' L
W')
4
01
9862
753
Start
Computer Architecture & Network Lab 32
Finite State Machine Controller
Computer Architecture & Network Lab 33
PLA Implementation
Outputs and next state are calculated by sum of products of inputs and current state
Columns in AND plane form products one column per unique product
term Rows in OR plane form sum Programmed by placing transistors
at intersection of row and column according to logic function
When the inputs are fully decoded (2N columns), a PLA is logically equivalent to a ROM
Optimization can be automated
Op5
Op4
Op3
Op2
Op1
Op0
S3
S2
S1
S0
IorD
IRWrite
MemReadMemWrite
PCWritePCWriteCond
MemtoRegPCSource1
ALUOp1
ALUSrcB0ALUSrcARegWriteRegDstNS3NS2NS1NS0
ALUSrcB1ALUOp0
PCSource0
ANDPlane
ORPlane
Computer Architecture & Network Lab 34
Exceptions and Interrupts
Exception: an unexpected event from within the processor that traps into an operating system service routine Arithmetic overflow Undefined instruction System call
Interrupt: an event that comes from outside of the processor that also traps into an operating system service routine I/O device request (I/O completion)
Handling of exceptions and interrupts in MIPS Saves PC (the address of the offending instruction) in EPC
(exception program counter) Records the reason for the exception or interrupt in the CAUSE
register Jumps to the operating system service routine rfe (return from exception) instruction restores the PC from EPC
Computer Architecture & Network Lab 35
Summary
Disadvantages of the Single-cycle implementation Long cycle time, too long for all instructions except for the slowest Inefficient hardware utilization with unnecessarily duplicated resources
Multiple-cycle implementation Partition execution into small steps of comparable duration Process each step in one cycle
Three general forms of control implementation Random logic PLA Microcode Clock
cycle time
CPI
Single-cycle implementation
Multi-cycle implementation
Pipelined implementation(next class)
