Computer Architecture

Lecture 10

EXCEPTIONS AND INTERRUPTS

Exceptions and Interrupts

Exception handling is a programming language construct or computer hardware mechanism designed to handle the occurrence of some condition that changes the normal flow of execution. The condition is called an exception. Alternative concepts are interrupt, signal and event handling.

In general, current state will be saved in a predefined location and execution will switch to a predefined handler (subroutine/procedure). Depending on the situation, the handler may later resume the execution at the original location, using the saved information to restore the original state. For example, an exception which will usually be resumed is a page fault, while a division by zero usually cannot be resolved transparently. (Wikipedia)

Common Exceptions

I/O Device Request Integer Arithmetic Overflow FP Arithmetic Anomaly Page Faults Memory Protection Violation Undefined Instruction Power Failure etc

Characterizing Exceptions

Synchronous vs. Asynchronous User Requested (system

calls)/Coerced (mouse click) Maskable vs. Non-maskable Within / Between Instructions Resume-able/Terminate

Resumable

Shut pipeline by converting all instruction after the instruction causing exception to NOP

Save processor state Call Handler Resume State

Precise Exception ???

MIPS Interrupts

IF – Page Fault, MPV ID – Undefined or Illegal Op

Code EX – Arithmetic MEM – Same as IF WB – None

MULTIPLE CYCLE PIPELINES

Single Cycle Computer

(One Big Clock Cycle to Accommodate Longest Latency)

IF ID EXE WB

Single Clock Cycle

Multiple Cycle Computers

IF ID EX WB IF ID EX WB IF ID EX WB

All Instruction Go through the Processing One-by-One

Classic 5-Stage Integer Pipeline

IF ID EX Mem WB

Almost 1 CPI except for LUD and Branch Hazards

A Multiple Cycle Pipeline

EX

Mem WBIF IDFP ADD

FP Multiply

Divide

Register File

(Integer/FP)

Register File

(Integer/FP)

Multiple Cycle Floating Point Pipeline

EX

Mem WBIF ID A1

A2

A3

A4

M1

M2

.

.M7

DivideFunction Unit Latency Initiation

/Re-Issue Interval

Integer ALU 0 1

Load/Store 1 1

FP Add 3 1

FP/Int Multiply

6 1

FP/Int Divide 24 25

Forwarding

EX

Mem WBIF ID A1

A2

A3

A4

M1

M2

.

.M7

Divide

ALU/FP Instructions

Example 1

L.D F10,0(R2) IF ID EXE MEM WB

ADD.D F0,F1,F10 IF ID ID ID A1 A2 A3 A4 MEM

Without Forwarding

L.D F10,0(R2) IF ID EXE MEM WB

ADD.D F0,F1,F10 IF ID ID A1 A2 A3 A4 MEM

With Forwarding

EXAMPLE 2

ADD.D F0,F1,F2 IF ID A1 A2 A3 A4 ME WB

ADD.D F5,F6,F7 IF ID A1 A2 A3 A4 ME WB

ADD.D F0,F1,F2IF

ID

A1

A2

A3

A4

ME

WB

ADD.D F5,F6,F0IF

ID

ID

I D

ID

A1

A2

A3

A4

ME

WB

EXAMPLE 3

DIV Unit is not Pipelined. So second instruction waits in ID stage although it is independent.

DIV.D F0,F1,F2 IF ID

D I V 1

D I V 2

D I V 3

D I V4

D I V5

o

o

o

D I V 24

ME

WB

ADD.D F5,F6,F7 IF ID ID ID ID ID

o

o

o

ID

D I V 1

Example 4 - Out Of Order Execution

L.DF10,0(R2)

IF ID EXE MEM WB

ADD.D F0,F1,F2

IF ID A1 A2 A3 A4 MEM WB

ADDI R5, R5, 10

IF ID EXE MEM WB

Mul.D F9,F6,F7

IF ID M1 M2 M3 M4 M4 M5

M6

M7 MEM WB

Add R3,R9,R10

IF ID EXE MEM WB

Sub R7,R8,R10

IF ID EXE MEM WB

Note All Instructions Independent

Out Of Order Completion

Example 5

Clock Cycle Number1 2 3 4 5 6 7 8 9 10 11

Mul.D IF ID M1 M2 M3 M4 M5 M6 M7 MEM WB

o o o IF ID EX MEM WB

o o o IF ID EXE MEM WB

Add.D IF ID A1 A2 A3 A4 MEM WB

o o o IF ID EXE MEM WB

o o o IF ID EXE MEM WB

L.D IF ID EXE MEM WB

Structural Hazard

Example 6 - WAW

1 2 3 4 5 6 7 8 9 10 11 12 13

MUL.D F3,F1,F2 IF ID

M1

M2

M3

M4

M5

M6

M7

MEM

WB

ADD.D F1,F5,F4 IF ID

A1

A2

A3

A4

MEM

WB

MUL.D F3,F9,F12 IF ID

ID

ID

ID

ID

ID

ID

ID

M1

M2

Reg Busy bit in Register FileA particular processor – it waits in ID stage in case of WAW not in WB, Page A-54, Paragraph 2

Example 7

L.D F4, 0(R2) MUL.D F0,F4,F6 ADD.D F2,F0,F8 S.D F2,0(R2)

Example 8 - EXCEPTIONS

DIV.D F0,F1,F2 ADD.D F10,F10,F8 SUB.D F12,F12,F14

Data Hazards

RAW HazardADD.D F3, F1, F2SUB.D F5, F6, F3

WAW HazardDIV.D F3, F1, F2SUB.D F3, F6, F5

WAR HazardDIV.D F3, F1, F2SUB.D F5, F6, F3ADD.D F3, F6, F7

TOO MANY ID STAGE

STALLS – SOLUTION?

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