Computer Architecture and Design – ECEN 350

Computer Architecture and Design – ECEN 350

Part 2

[Some slides adapted from M. Irwin, D. Paterson and others]

The Instruction Set Architecture (ISA)

instruction set architecture

software

hardware

The interface description separating the software and hardware

How Do the Pieces Fit Together?

I/O systemProcessor

Compiler

OperatingSystem

Applications

Digital DesignCircuit Design

Instruction Set Architecture

Firmware

Coordination of many levels of abstraction Under a rapidly changing set of forces Design, measurement, and evaluation

Memory system

Datapath & Control

network

The MIPS ISA Instruction Categories

Load/Store Computational Jump and Branch Floating Point

- coprocessor Memory Management Special

R0 - R31

PCHILO

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Registers

Assembly Language Instructions The language of the machine

Want an ISA that makes it easy to build the hardware and the compiler while maximizing performance and minimizing cost

Stored program (von Neumann) concept Instructions are stored in memory (as is the data)

Our target: the MIPS ISA similar to other ISAs developed since the 1980‘s

Design goals: maximize performance, minimize cost, reduce design time (time-to-market), minimize memory

space (embedded systems), minimize power consumption (mobile systems)

RISC - Reduced Instruction Set Computer RISC philosophy

fixed instruction lengths load-store instruction sets limited number of addressing modes limited number of operations

MIPS, Sun SPARC, HP PA-RISC, IBM PowerPC … Instruction sets are measured by how well compilers

use them as opposed to how well assembly language programmers use them

CISC (C for complex), e.g., Intel x86

The Four Design Principles

1. Simplicity favors regularity.2. Smaller is faster.3. Make the common case fast.4. Good design demands good compromises.

The MIPS ISA

Instruction Categories Load/Store Computational Jump and Branch Floating Point

- coprocessor Memory Management Special

R0 - R31

PCHILO

Registers

MIPS Registers Unlike HLL like C or Java, assembly cannot use

variables Why not? Keep Hardware Simple

Assembly Operands are registers limited number of special locations built directly into the

hardware operations can only be performed on these!

Benefit: Since registers are directly in hardware, they are very fast (faster than 1 billionth of a second)

MIPS Registers Drawback: Since registers are in hardware, there are

a predetermined number of them Solution: MIPS code must be very carefully put together to

efficiently use registers 32 registers in MIPS

Why 32? - Large for the time, easier compiling- Small now (but we are stuck with it)

Each MIPS register is 32 bits wide Groups of 32 bits called a word in MIPS

0 $zero constant 0 (Hdware)1 $at reserved for assembler2 $v0 expression evaluation &3 $v1 function results4 $a0 arguments5 $a16 $a27 $a38 $t0 temporary: caller saves. . . (callee can clobber)15 $t7

Naming Conventions for Registers

16 $s0 callee saves. . . (caller can clobber)23 $s724 $t8 temporary (cont’d)25 $t926 $k0 reserved for OS kernel27 $k128 $gp pointer to global area29 $sp stack pointer30 $fp frame pointer31 $ra return address (Hdware)

MIPS Arithmetic Instruction MIPS assembly language arithmetic statement

add $t0, $s1, $s2sub $t0, $s1, $s2

Each arithmetic instruction performs only one operation

Each arithmetic instruction specifies exactly three operands

destination source1 op source2 Operand order is fixed (the destination is specified first)

The operands are contained in the datapath’s register file ($t0, $s1, $s2)

Compiling More Complex Statements Assuming variable b is stored in register $s1, c is

stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement

h = (b - c) + d

Compiling More Complex Statements Assuming variable b is stored in register $s1, c is

stored in $s2, and d is stored in $s3 and the result is to be left in $s0, what is the assembler equivalent to the C statement

h = (b - c) + d

sub $t0, $s1, $s2

add $s0, $t0, $s3

Compiling More Complex Statements One particular immediate, the number zero (0),

appears very often in code. So we define register zero ($0 or $zero) to always

have the value 0; egadd $s0,$s1,$zero (in MIPS)f = g (in C)

where MIPS registers $s0,$s1 are associated with C variables f, g

defined in hardware, so an instruction add $zero,$zero,$s0

will not do anything!

Instructions, like registers and words of data, are also 32 bits long Example: add $t0, $s1, $s2registers have numbers $t0=$8,$s1=$17,$s2=$18

Instruction Format:

Can you guess what the field names stand for?

Machine Language - Arithmetic Instruction

op rs rt rd shamt funct

000000 10001 10010 01000 00000 100000

R-format Example

add $t0, $s1, $s2

special $s1 $s2 $t0 0 add

0 17 18 8 0 32

000000 10001 10010 01000 00000 100000

000000100011001001000000001000002 = 0232402016

op rs rt rd shamt funct6 bits 6 bits5 bits 5 bits 5 bits 5 bits

MIPS Instruction Fields


op rs rt rd shamt funct6 bits 5 bits 5 bits 5

bits5 bits

6 bits

= 32 bits

opcode indicating operation to be performedaddress of the first register source operand

address of the second register source operand

the register destination address

shift amount (for shift instructions)function code that selects the specific variant of

the operation specified in the opcode field

Small constants are used quite frequently (50% of operands in many common programs)e.g., A = A + 5;

B = B + 1;C = C - 18;

Solutions? Why not? Put “typical constants” in memory and load them Create hard-wired registers (like $zero) for constants like 1,

2, 4, 10, …

Dealing with Constants

How do we make this work? How do we Make the common case fast !

Include constants inside arithmetic instructions Much faster than if they have to be loaded from memory (they

come in from memory with the instruction itself)

MIPS immediate instructions

addi $s3, $s3, 4 #$s3 = $s3 + 4

There is no subi instruction, can you guess why not?

Constant (or Immediate) Operands

What instruction format is used for the addi ?addi $s3, $s3, 4 #$s3 = $s3 + 4

Machine format:

Machine Language – Immediate Instructions


Machine format:


op rs rt 16 bit immediate I format

8 19 19 4

The constant is kept inside the instruction itself! So must use the I format – Immediate format Limits immediate values to the range +215–1 to -215

Given the following lines in MIPS Assembly Language

Assemble the MIPS object code for these four lines:


Memory is a large, single-dimensional array An address acts as the index into the memory array

Processor – Memory Interconnections

Processor

Memory

32 bits

?locations

read addr/write addr

read data

write data

32

32

32 232 Bytes (4 GB) 230

Words (1 GW)

= 4 Bytes = 1 Word

110110

048

The data stored in the memory

The word address of the

data

Consider memory to be a single huge array: Each cell of the array has an address associated with it. Each cell also stores some value. Do you think they use signed or unsigned numbers? Negative

address?! Don’t confuse the address referring to a memory

location with the value stored in that location.


23 42 ... ...101 102 103 104 105 ...

An address refers to a particular memory location. In other words, it points to a memory location.

Pointer: A variable that contains the address of a variable.


23 42 ... ...101 102 103 104 105 ...

x y

Location (address)

namep

104

How to create a pointer:& operator: get address of a variable

“dereference operator”: get value pointed to

printf(“p points to %d\n”,*p);


int *p, x; p ? x ?

x = 3; p ? x 3

p =&x; p x 3

How to change a variable pointed to? Use dereference * operator on left of =


p x 5*p = 5;

p x 3

MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)

lw $t0, 4($s3) #load word from memory

sw $t0, 8($s3) #store word to memory

The data transfer instruction must specify where in memory to read from (load) or write to (store) – memory

address where in the register file to write to (load) or read from (store) –

register destination (source) The memory address is formed by summing the constant

portion of the instruction and the contents of the second register

Accessing Memory

MIPS has two basic data transfer instructions for accessing memory (assume $s3 holds 2410)

lw $t0, 4($s3) #load word from memory

sw $t0, 8($s3) #store word to memory

The data transfer instruction must specify where in memory to read from (load) or write to (store) – memory

address where in the register file to write to (load) or read from (store) –

register destination (source) The memory address is formed by summing the constant

portion of the instruction and the contents of the second register

Accessing Memory

28

32

MIPS Memory Addressing The memory address is formed by summing the

constant portion of the instruction and the contents of the second (base) register

lw $t0, 4($s3) #what is loaded into $t0

sw $t0, 8($s3) #$t0 is stored where?

Memory

. . . 0 1 0 0Data Word Address

0

4

8

12

16

20

24

. . . 1 0 0 0

. . . 0 0 1 0

. . . 0 0 0 1

. . . 1 1 0 0

. . . 0 1 0 1

. . . 0 1 1 0$s3 holds 8

MIPS Memory Addressing The memory address is formed by summing the

constant portion of the instruction and the contents of the second (base) register

lw $t0, 4($s3) #what? is loaded into $t0

sw $t0, 8($s3) #$t0 is stored where?

Memory

. . . 0 1 0 032 bit Data Word Address

0

4

8

12

16

20

24

. . . 1 0 0 0

. . . 0 0 1 0

. . . 0 0 0 1

. . . 1 1 0 0

. . . 0 1 0 1

. . . 0 1 1 0$s3 holds 8

in location 16

. . . 0001

. . . 0001

Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base

address of array A is in $s3, what is the MIPS assembly code for the C statement

A[8] = A[2] - b

$s3

$s3+4

$s3+8

$s3+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]

Compiling with Loads and Stores Assuming variable b is stored in $s2 and that the base

address of array A is in $s3, what is the MIPS assembly code for the C statement

A[8] = A[2] - b

$s3

$s3+4

$s3+8

$s3+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]lw $t0, 8($s3)

sub $t0, $t0, $s2

sw $t0, 32($s3)

Compiling with a Variable Array Index Assuming that the base address of array

A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement

c = A[i] - b

add $t1, $s3, $s3 #array index i is in $s3

add $t1, $t1, $t1 #temp reg $t1 holds 4*i

$s4

$s4+4

$s4+8

$s4+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]

Compiling with a Variable Array Index Assuming that the base address of array

A is in register $s4, and variables b, c, and i are in $s1, $s2, and $s3, respectively, what is the MIPS assembly code for the C statement

c = A[i] - b

add $t1, $s3, $s3 #array index i is in $s3

add $t1, $t1, $t1 #temp reg $t1 holds 4*i

$s4

$s4+4

$s4+8

$s4+12

. . .

A[2]

A[3]

. . .

A[1]

A[0]

add $t1, $t1, $s4 #addr of A[i] now in $t1

lw $t0, 0($t1)

sub $s2, $t0, $s1

Review: MIPS Instructions, so far

Category Instr Op Code

Example Meaning

Arithmetic add 0 & 32

add $s1, $s2, $s3 $s1 = $s2 + $s3

subtract 0 & 34

sub $s1, $s2, $s3 $s1 = $s2 - $s3

Arithmetic add immediate

8 addi $s1, $s2, 4 $s1 = $s2 + 4

Datatransfer

load word 35 lw $s1, 100($s2) $s1 = Memory($s2+100)

store word 43 sw $s1, 100($s2) Memory($s2+100) = $s1

The MIPS ISA

OP

OP

OP

rs rt rd sa funct

rs rt immediate

jump target

3 Instruction Formats: all 32 bits wide

Review: Unsigned Binary RepresentationHex Binary Decimal

0x00000000 0…0000 00x00000001 0…0001 10x00000002 0…0010 20x00000003 0…0011 30x00000004 0…0100 40x00000005 0…0101 50x00000006 0…0110 60x00000007 0…0111 70x00000008 0…1000 80x00000009 0…1001 9

…0xFFFFFFFC 1…11000xFFFFFFFD 1…11010xFFFFFFFE 1…11100xFFFFFFFF 1…1111 232 - 1

232 - 2232 - 3232 - 4

232 - 1

1 1 1 . . . 1 1 1 1 bit

31 30 29 . . . 3 2 1 0 bit position

231 230 229 . . . 23 22 21 20 bit weight

1 0 0 0 . . . 0 0 0 0 - 1

Review: Signed Binary Representation

2’sc binary decimal1000 -81001 -71010 -61011 -51100 -41101 -31110 -21111 -10000 00001 10010 20011 30100 40101 50110 60111 7

23 - 1 =

-(23 - 1) =

-23 =

1010

complement all the bits

1011

and add a 1

complement all the bits

0101

and add a 1

0110

MIPS Instruction Fields


op rs rt rd shamt funct6 bits 5 bits 5 bits 5

bits5 bits

6 bits

= 32 bits

opcode indicating operation to be performedaddress of the first register source operand

address of the second register source operand

the register destination address

shift amount (for shift instructions)function code that selects the specific variant of

the operation specified in the opcode field

Consider the load-word and store-word instr’s What would the regularity principle have us do?

- But . . . Good design demands compromise Introduce a new type of instruction format

I-type for data transfer instructions (previous format was R-type for register)

Example: lw $t0, 24($s2)

Machine Language - Load Instruction

op rs rt 16 bit number

23hex 18 8 24

100011 10010 01000 0000000000011000

Quiz #1 Take out a sheet of paper Write your name and UIN at the top

Translate the following instructions into machine code add $t0, $zero, $zero lw $t2, 32 ($t2)

Memory Address Location Example: lw $t0, 24($s2)

Memory

data word address (hex)0x000000000x000000040x000000080x0000000c

0xf f f f f f f f

$s2 0x12004094

0x00000002

2410 + $s2 =

Note that the offset can be positive or negative

Memory Address Location Example: lw $t0, 24($s2)

Memory

data word address (hex)0x000000000x000000040x000000080x0000000c

0xf f f f f f f f

$s2 0x12004094

0x00000002

2410 + $s2 =

Note that the offset can be positive or negative

. . . 1001 0100+ . . . 0001 1000 . . . 1010 1100 = 0x120040ac

0x120040ac

$t0

Example: sw $t0, 24($s2)

A 16-bit offset means access is limited to memory locations within a range of 213 = 8,192 words (215 = 32,768 bytes) of the address in the base register $s2 2’s complement (1 sign bit + 15 magnitude bits)

Machine Language - Store Instruction


43 18 8 24

101011 10010 01000 0000000000011000

Example: sw $t0, 24($s2)

A 16-bit offset means access is limited to memory locations within a range of +213-1 to -213 (~8,192) words (+215-1 to -215 (~32,768) bytes) of the address in the base register $s2 2’s complement (1 sign bit + 15 magnitude bits)

Machine Language - Store Instruction


43 18 8 24

101011 10010 01000 0000000000011000


Machine format:



Machine format:


op rs rt 16 bit immediate I format

8 19 19 4

The constant is kept inside the instruction itself! So must use the I format – Immediate format Limits immediate values to the range +215–1 to -215

Instruction Format Encoding Can reduce the complexity with multiple formats by

keeping them as similar as possible First three fields are the same in R-type and I-type

Each format has a distinct set of values in the op field

Instr Frmt op rs rt rd shamt funct addressadd R 0 reg reg reg 0 32ten NAsub R 0 reg reg reg 0 34ten NAaddi I 8ten reg reg NA NA NA constantlw I 35ten reg reg NA NA NA addresssw I 43ten reg reg NA NA NA address

OP

OP

rs rt rd sa funct

rs rt immediate

Byte Addresses

Since 8-bit bytes are so useful, most architectures address individual bytes in memory

Therefore, the memory address of a word must be a multiple of 4 (alignment restriction)

Big Endian: leftmost byte is word address IBM 360/370, Motorola 68k, MIPS, Sparc, HP PA

Little Endian: rightmost byte is word addressIntel 80x86, DEC Vax, DEC Alpha (Windows NT)

Endianess

Big Endian: leftmost byte is word address Little Endian: rightmost byte is word address

msb lsb

little endian

big endian

Endianess

Example: consider the number 1025 (0x401) stored in a 4-byte integer

In binary 00000000 00000000 00000100 00000001

00 01 02 0300000000 00000000 00000100 0000000100000001 00000100 00000000 00000000

Big EndianLittle Endian

Alignment

Alignment restriction: requires that objects fall on address that is a multiple of their size.

0 1 2 3Aligned

NotAligned

Mips and Alignment MIPS supports byte addressability:

A byte is the smallest unit with its address; MIPS restricts memory accesses to be aligned as

follows: 32-bit word has to start at byte address that is multiple of 4;

Thus, 32-bit word at address 4n includes four bytes with addresses: 4n, 4n+1, 4n+2, and 4n+3.

16-bit half word has to start at byte address that is multiple of 2; Thus, 16-bit word at address 2n includes two bytes with addresses: 2n and 2n+1.

MIPS supports 32-bit addresses: An address is given as 32-bit unsigned integer;

Decision making instructions alter the control flow i.e., change the "next" instruction to be executed

MIPS conditional branch instructions:

bne $s0, $s1, Lbl #go to Lbl if $s0$s1 beq $s0, $s1, Lbl #go to Lbl if $s0=$s1

Example: if (i==j) h = i + j;

bne $s0, $s1, Lbl1add $s3, $s0, $s1

Lbl1: ...

Instructions for Making Decisions

Specifying Branch Destinations

bne $s0,$s1,Lbl1

add $s3,$s0,$s1

...Lbl1:

The branch distance is limited to -215 to +215-1 instructions from the (instruction after the) branch

- but most branches are local

PC

Another Instruction for Changing Flow MIPS also has an unconditional branch

instruction or jump instruction:

j Lbl #go to Lbl

Example: if (i!=j) h=i+j;

elseh=i-j;

beq $s0, $s1, Elseadd $s3, $s0, $s1j Exit

Else: sub $s3, $s0, $s1Exit: ...

Compiling While Loops Compile the assembly code for the C while loop where i is in $s0, j is in $s1, and k is in $s2 while (i!=k)

i=i+j;

Loop: beq $s0, $s2, Exitadd $s0, $s0, $s1j Loop

Exit: . . .

Basic block – A sequence of instructions without branches (except at the end) and without branch targets (except at the beginning)

Branching Far Away What if the branch destination is further away than can

be captured in 16 bits?

The assembler comes to the rescue – it inserts an unconditional jump to the branch target and inverts the condition

beq $s0, $s1, L1

becomesbne $s0, $s1, L2j L1

L2:

Example•Compile by hand

if (i == j) f=g+h; else f=g-h;

Example•Compile by hand

if (i == j) f=g+h; else f=g-h;

Final compiled MIPS code:

beq $s3,$s4,True # branch i==j sub $s0,$s1,$s2 # f=g-h(false) j Fin # goto FinTrue: add $s0,$s1,$s2 # f=g+h (true)Fin:Note: Compiler automatically creates labels to handle decisions (branches).Generally not found in HLL code.

Review: MIPS Instructions, so farCategory Instr OpCd Example Meaning

Arithmetic add 0 & 20 add $s1, $s2, $s3 $s1 = $s2 + $s3subtract 0 & 22 sub $s1, $s2, $s3 $s1 = $s2 - $s3

add immediate 8 addi $s1, $s2, 4 $s1 = $s2 + 4Datatransfer

load word 23 lw $s1, 100($s2) $s1 = Memory($s2+100)store word 2b sw $s1, 100($s2) Memory($s2+100) = $s1

Cond. branch

br on equal 4 beq $s1, $s2, L if ($s1==$s2) go to Lbr on not equal 5 bne $s1, $s2, L if ($s1 !=$s2) go to L

Review: Instruction Format Encoding

Instr Frmt op rs rt rd shamt funct addressadd R 0 reg reg reg 0 32ten NAsub R 0 reg reg reg 0 34ten NAaddi I 8ten reg reg NA NA NA constantlw I 35ten reg reg NA NA NA addresssw I 43ten reg reg NA NA NA address

Instructions:bne $s0, $s1, Lbl #go to Lbl if

$s0$s1 beq $s0, $s1, Lbl #go to Lbl if

$s0=$s1

Machine Formats:

How is the branch destination address specified?

Assembling Branches

op rs rt 16 bit number I format

5 16 17 ????

4 16 17 ????

Specifying Branch Destinations

Could use a “base” register and add to it the 16-bit offset

which register?- Instruction Address Register (PC

= program counter) - its use is automatically implied by branch

- PC gets updated (PC+4) during the fetch cycle so that it holds the address of the next instruction

limits the branch distance to -215 to +215-1 instr’s from the (instruction after the) branch

- but most branches are local anyway

bne $s0,$s1,Lbl1

add $s3,$s0,$s1

...Lbl1:

Could specify the memory address but that would require a 32 bit field

PC

Disassembling Branch Destinations The contents of the updated PC (PC+4) is added to the 16

bit branch offset which is converted into a 32 bit value by concatenating two low-order zeros to make it a word address and

then sign-extending those 18 bits The result is written into the PC if the branch condition is

true - before the next Fetch cycle

PCAdd

32

32 3232

32

offset

16

32

00

sign-extend

from the low order 16 bits of the branch instruction

branch dstaddress

?Add

4 32

Offset Tradeoffs Why not just store the word offset in the low order 16

bits? Then the two low order zeros wouldn’t have to be concatenated, it would be less confusing, …

But that would limit the branch distance to -213 to +213-1 instr’s from the (instruction after the) branch

And concatenating the two zero bits costs us very little in additional hardware and has no impact on the clock cycle time

Assembly code bne $s0, $s1, Lbl1

add $s3, $s0, $s1Lbl1: ...

Machine Format of bne:

Assembling Branches Example

op rs rt 16 bit offset I format

5 16 17

Remember After the bne instruction is fetched, the PC is updated so

that it is addressing the add instruction (PC = PC + 4). The offset (plus 2 low-order zeros) is sign-extended and

added to the (updated) PC

Assembly code bne $s0, $s1, Lbl1

add $s3, $s0, $s1Lbl1: ...

Machine Format of bne:

Assembling Branches Example

op rs rt 16 bit offset I format

5 16 17

Remember After the bne instruction is fetched, the PC is updated so

that it is addressing the add instruction (PC = PC + 4). The offset (plus 2 low-order zeros) is sign-extended and

added to the (updated) PC

0x0001

Instruction: j Lbl #go to Lbl

Machine Format:

Assembling Jumps

op 26-bit address J format

2 ????

How is the jump destination address specified? As an absolute address formed by

- concatenating 00 as the 2 low-order bits to make it a word address

- concatenating the upper 4 bits of the current PC (now PC+4)

Disassembling Jump Destinations The low order 26 bits of the jump instr converted into a 32

bit jump destination address by concatenating two low-order zeros to create an 28 bit (word)

address and then concatenating the upper 4 bits of the current PC (now PC+4) to create a 32 bit (word) address

that is put into the PC prior to the next Fetch cycle

PC4 32

26

32

00

from the low order 26 bits of the jump instruction

Assemble the MIPS machine code (in decimal is fine) for the following code sequence. Assume that the addr of the beq instr is 0x00400020hex



Assembling Branches and Jumps

Assemble the MIPS machine code (in decimal is fine) for the following code sequence. Assume that the addr of the beq instr is 0x00400020hex



Assembling Branches and Jumps

0x00400020 4 16 17 20x00400024 0 16 17 19 0 0x20

0x00400028 2 0000 0100 0 ... 0 0011 002

0x0040002c 0 16 17 19 0 0x220x00400030 ...

jmp dst = (0x0) 0x040003 002(002) = 0x00400030

We have beq, bne, but what about branch-if-less-than? New instruction: slt $t0, $s0, $s1 # if $s0 < $s1

# then# $t0 = 1

# else # $t0 = 0

Machine format:

2

More Instructions for Making Decisions

op rs rt rd funct

0 16 17 8 0 42 = 0x2a

R format

Since constant operands are popular in comparisons, also have slti

New instruction: slti $t0, $s0, 10 # if $s0 < 10

# then# $t0 = 1

# else # $t0 = 0

Machine format:

2

Yet More Instructions for Making Decisions


a 16 8 0x000a

I format

Other Branch Instructions Can use slt, beq, bne, and the fixed value of 0 in $zero to create all relative conditions

less than blt $s1, $s2, Lbl

less than or equal to ble $s1, $s2, Lbl greater than bgt $s1, $s2, Lbl great than or equal to bge $s1, $s2, Lbl

As pseudo instructions they are recognized (and expanded) by the assembler

The assembler needs a reserved register ($at) so there are policy of use conventions for registers

Other Branch Instructions Can use slt, beq, bne, and the fixed value of 0 in $zero to create all relative conditions

less than blt $s1, $s2, Lbl

less than or equal to ble $s1, $s2, Lbl greater than bgt $s1, $s2, Lbl great than or equal to bge $s1, $s2, Lbl

As pseudo instructions they are recognized (and expanded) by the assembler

The assembler needs a reserved register ($at) so there are policy of use conventions for registers

slt $at, $s1, $s2 #$at set to 1 ifbne $at, $zero, Lbl # $s1 < $s2

Most higher level languages have case or switch statements allowing the code to select one of many alternatives depending on a single value

Instruction:

jr $t1 #go to address in $t1

Machine format:

Another Instruction for Changing Flow

op rs funct

0 9 0 0 0 8 = 0x08

R format

MIPS Data TypesBit: 0, 1

Bit String: sequence of bits of a particular length 4 bits is a nibble 8 bits is a byte 16 bits is a half-word 32 bits is a word 64 bits is a double-word

Character: ASCII 7 bit code

Decimal: digits 0-9 encoded as 00002 thru 10012

two decimal digits packed per 8 bit byte

Integers: 2's complement

Floating Point

Beyond Numbers Most computers use 8-bit bytes to represent characters

with the American Std Code for Info Interchange (ASCII)

So, we need instructions to move bytes around

ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char ASCII Char0 Null 32 space 48 0 64 @ 96 ` 112 p

1 33 ! 49 1 65 A 97 a 113 q

2 34 “ 50 2 66 B 98 b 114 r

3 35 # 51 3 67 C 99 c 115 s

4 EOT 36 $ 52 4 68 D 100 d 116 t

5 37 % 53 5 69 E 101 e 117 u

6 ACK 38 & 54 6 70 F 102 f 118 v

7 39 ‘ 55 7 71 G 103 g 119 w

8 bksp 40 ( 56 8 72 H 104 h 120 x

9 tab 41 ) 57 9 73 I 105 i 121 y

10 LF 42 * 58 : 74 J 106 j 122 z

11 43 + 59 ; 75 K 107 k 123 {

12 FF 44 , 60 < 76 L 108 l 124 |

15 47 / 63 ? 79 O 111 o 127 DEL

Loading and Storing Bytes MIPS provides special instructions to move byteslb $t0, 1($s3) #load byte from memorysb $t0, 6($s3) #store byte to memory

What 8 bits get loaded and stored? load byte places the byte from memory in the rightmost 8 bits of

the destination register- what happens to the other bits in the register?

store byte takes the byte from the rightmost 8 bits of a register and writes it to the byte in memory- leaving the other bytes in the memory word

unchanged


Example of Loading and Storing Bytes Given following code sequence and memory state what is

the state of the memory after executing the code?add $s3, $zero, $zerolb $t0, 1($s3)sb $t0, 6($s3)

Memory

0x 0 0 9 0 1 2 A 0Data Word

Address (Decimal)

0

4

8

12

16

20

24

0x F F F F F F F F

0x 0 1 0 0 0 4 0 2

0x 1 0 0 0 0 0 1 0

0x 0 0 0 0 0 0 0 0

0x 0 0 0 0 0 0 0 0

0x 0 0 0 0 0 0 0 0

What value is left in $t0?

What if the machine was little Endian?

What word is changed in Memory and to what?

Example of Loading and Storing Bytes Given following code sequence and memory state what is

the state of the memory after executing the code?add $s3, $zero, $zerolb $t0, 1($s3)sb $t0, 6($s3)

Memory

0x 0 0 9 0 1 2 A 0Data Word

Address (Decimal)

0

4

8

12

16

20

24

0x F F F F F F F F

0x 0 1 0 0 0 4 0 2

0x 1 0 0 0 0 0 1 0

0x 0 0 0 0 0 0 0 0

0x 0 0 0 0 0 0 0 0

0x 0 0 0 0 0 0 0 0$t0 = 0x00000090

mem(4) = 0xFFFF90FF

mem(4) = 0xFF12FFFF

What value is left in $t0?

What if the machine was little Endian?

What word is changed in Memory and to what?

$t0 = 0x00000012

MIPS Organization

ProcessorMemory

32 bits

230

words

read/write addr

read data

write data

word address(binary)

0…00000…01000…10000…1100

1…1100

Register File

src1 addr

src2 addr

dst addr

write data

32 bits

src1data

src2data

32registers

($zero - $ra)

32

32

32

32

32

32

5

5

5

ALU32

32

32 0 1 2 37654

byte address(big Endian)

Arithmetic instructions – to/from the register fileLoad/store instructions - to/from memory

MIPS Register File

Operands of arithmetic instructions must be from a limited number of special locations contained in the datapath’s register file Thirty-two 32-bit registers

- Two read ports - One write port

Register File

src1 addr

src2 addr

dst addr

write data

32 bits

src1data

src2data

32locations

325

32

5

5

32

MIPS Register File Registers are

Fast- Smaller is faster & Make the common case fast

Easy for a compiler to use- e.g., (A*B) – (C*D) – (E*F) can do multiplies in any

order Improves code density

- Since register are named with fewer bits than a memory location

Register addresses are indicated by using $

Two Key Principles of Machine Design1. Instructions are represented as numbers2. Programs are stored in memory to be read or written,

just like numbers

Stored-program concept Programs can be shipped as

files of binary numbers – binary compatibility

Computers can inherit ready-made software provided they are compatible with an existing ISA – leads industry to align around a small number of ISAs

Accounting prg (machine code)

C compiler (machine code)

Payroll data

Source code in C for Acct prg

Memory

Computer Architecture and Design – ECEN 350

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Transcript of Computer Architecture and Design – ECEN 350