Comprehensive Optimization Method forThermal Properties and Parasitics in Power Modules

Ole Muhlfeld, Friedrich W. FuchsChristian-Albrechts-University of Kiel, Germany

Institute of Power Electronics and Electrical DrivesKaiserstr. 2, 24143 Kiel, Germany

Email: om@tf.uni-kiel.de

Abstract—A combined optimization approach regarding ther-mal properties and parasitic elements inside power semiconduc-tor modules for power electronic converters is presented. Theproposed method allows the determination of the best suited semi-conductor positions on the DBC substrate as well as optimizationof the substrate structure. The optimization procedure leads to amatrix representation illustrating the results in a concrete way.

Keywords—Thermal design, EMC/EMI, Packaging, Simulation

I. INTRODUCTION

Due to the ongoing increase of power density in powermodules for power DC to AC converters the coupling betweenthermal properties and parasitic elements becomes more andmore relevant. Optimization of the DBC (direct bondedcopper) layout and the chips’ positions in these moduleshelps to improve the electro-thermal performance and toenhance reliability. Several investigations have been made tofind optimal layouts for the reduction of stray inductance [1],[2] or to increase the cooling efficiency [3].For comprehensive optimization the coupling of electricaland thermal properties inside power modules has to beconsidered, i.e., a large distance between chips improvesthe heat spreading, but the stray inductance of the moduleincreases due to the necessarily longer commutation path.The use of broad tracks reduces stray inductances [4],however parasitic capacitances increase at the same time [5].These examples show that the optimization process of powermodules is a nontrivial task, as the demands for optimizationare contradicting.Suggestions for a combined optimization approach havebeen made [6], [7]. In [6] the optimization process involvesthermal behavior and parasitic capacitors, whereas inductanceis neglected. A complex numerical algorithm restricted by anextensive set of boundary conditions was used. [7] mainlyfocuses on thermal issues and parasitic inductances. Thethermal issues are investigated first, parasitic inductances areoptimized in a second step.This paper proposes another systematic approach for acombined optimization process for power modules. It hasthe benefit of being very concrete and applicable withoutthe necessity for a major programming effort. Differentoptimization targets can be investigated within one overall

model. The approach can be generalized to arbitrary layoutsand different boundary conditions. The method is presentedbased on simulation. All simulations were carried out bymeans of the software INCA3d [8] and Comsol Multiphysics[9], using PEEC and FEM algorithms, respectively. A simpleMOSFET half-bridge configuration is used as an example,but the stated methods can be used for other circuits as well.Following this introduction a systematic approach for powermodule design is stated. The third part introduces anexemplary half-bridge optimization problem that is solvedwith the suggested approach in the fourth section. In the fifthpart the overall performance is evaluated and the paper isfinished with the conclusion.

II. SYSTEMATIC OPTIMIZATION APPROACH

The systematic optimization approach consists of threesteps: first, the basic boundaries for the layout of the DBCare determined. Therefore the minimum required surface areaand cross-section of the copper areas on the DBC are assigned.They arise from thermal spreading requirements and the in-tended minimization of copper losses.Additionally, assembly constraints such as that on the minimaldistance between components and edges of the DBC andthe placement and size of the pads for power terminalsand gate contacts define the DBC size. In the second step,all eligible power semiconductor positions are evaluated andthe electro-thermal optimization is carried out by means ofsimulation. In the third step, the final DBC structuring isdone, following common design rules for the minimizationof parasitic elements [4], [5].For the evaluation of the ideal semiconductor position, allsuitable positions for chip placement on the copper tracks areevaluated. Within the resulting areas, a fine grid of equidistantpoints is defined, representing the possible center points ofthe semiconductors. For each point, the thermal properties, theparasitic inductances consisting of DBC inductance and bondwire inductance, and the parasitic capacitances are simulated.The results for each parameter are stored within a matrix.Thus, every parameter to be optimized has its own matrix. Thematrix elements represent the discrete values for the accordingchip position and can be visualized in a two dimensionalplot. The matrix elements are standardized and a weighted

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summation of all matrices (with weight factors wi) can becarried out, leading to the optimization matrix providing in-stantaneously a result for an optimal semiconductor placement,combining thermal and parasitics optimization. Fig. 1 presentsthe schematic flow diagram for this optimization.In the last step, the final DBC structuring is carried out, align-ing with the final semiconductor positions. This structuringdefines the area of the copper tracks, influencing the parasiticcapacitances as the potentials of the phase track changes withtime.The analysis of the optimization process through a two dimen-sional graphical matrix representation has additional benefits,i.e. it allows the definition of an acceptance range for eachparameter, leading to the definition of tolerance zones for thechip position, depending on the parameter.Additionally, the matrix can be used to obtain an estimationof the success of the optimization, as the theoretical possibleminimum and maximum values for each parameter are evi-dently given. The proposed approach is demonstrated on anexemplary power module in the next chapter.

Fig. 1. Schematic flow diagram for the suggested optimization approach:Inductive, thermal and capacitive simulation results for each chip position arestored in standardized matrices. These matrices are multiplied with the weightfactors wi. Summation of the resulting matrices leads to the optimizationmatrix.

III. OPTIMIZATION OF A HALF-BRIDGE POWER MODULE

The fictive half-bridge power module (Fig. 2) investigatedhere is chosen to show the optimization process for a simplegeometry. The points to start from are the given technical andgeometrical boundary conditions.The minimum size of the module is given through thermalboundaries, as there are given demands on heat spreadingand minimization of copper losses, defining the surface areaneeded and the cross-section of the copper tracks required.

Here, the boundary conditions given by assembly constraintslike the minimal distance between components and edges ofthe DBC and the minimal size of the pads for power terminalsand gate contacts could only be given marginal consideration.First, the minimal required DBC size is estimated based onthe given thermal boundary conditions and thermal constraints.For the given example a minimum of 720 mm2 is specified.This arises from the sum of the areas of the chips (60 mm2

each), the targeted filling degree of 25%, the estimated spacerequired for the terminal contacts and to comply with thenecessary distance between components and edges of the cop-per tracks respectively. The degrees of freedom for reshaping

Fig. 2. Exemplary half bridge power module (a) schematic and (b) exemplarylayout with changeable geometrical shape (green arrows) for optimization

and optimization of this layout have to be well-known. Beingrestricted for this example by the given assembly limitationsand the convention that DC and phase tracks have to be onopposite sides of the module, the prospects for variation ofgeometrical shape and component placement are shown inFig. 2 as green arrows. The position of the high-side powersemiconductor, here a MOSFET is taken for example, inthe lower left corner was previously defined by analyticalconsiderations, as the position close to the positive DC-trackaccounts for a short commutation path and therefore low strayinductance. The distance of 2 mm to the edges of the DBCguarantees good heat spreading [10]. The placement of thesecond semiconductor (low-side MOSFET) is more difficultas it is influenced by the thermal coupling with the otherMOSFET. The optimization of its position on the track isshown in the following.

Chip Size 60 mm2

DBC Size 720 mm2

DBC Stack (Cu/Al2O3/Cu) 300µm / 400µm / 300µmBase Plate (area/thickness) 1280 mm2 / 2mmlosses of each chip 30 Wambient temperature 300 Khtc (heat sink) h = 500W/m2K

TABLE ITHERMAL PARAMETERS

A. Thermal Optimization

The requirement for a thermally optimized module is toexhibit a low thermal resistance Rth to the ambient, acceptablemaximum temperature Tmax during operation and a lowtemperature gradient ∆T on the DBC.

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The relevant constraints are the shape of the copper tracks,the thickness of the substrate, and the location of the semi-conductors. With [11] the minimal thermally required copperarea for a single chip can be calculated. If more than one chipis placed, the thermal coupling has to be considered, too. Inthe selected example, the two MOSFETs both exhibit a chiparea of 60 mm2. For the simulations performed with ComsolMultiphysics [9], total losses are assumed to be of 30 W each.The thermal stack is shown in Fig. 3. The DBC (30 mm x24 mm) consists of the upper copper layer with thicknessof 300 µm, the Al203 ceramic of 400 µm and the backsidecopper metallization of 300 µm. The DBC is mounted on acopper base plate (40 mm x 32 mm) with a thickness of 2 mmand cooled by an arbitrary heat sink of the same base area,simulated through an extended surface heat transfer coefficient(htc) h = 500W/m2 K. Only the steady-state condition isregarded here.

Fig. 3. Thermal structure used for simulations.

From the thermal optimization point of view, a low andisothermal temperature all over the DBC is beneficial, as itavoids hotspots and allows good heat spreading and cooling.Therefore the deviation from an isothermal DBC is investi-gated. This means the difference in DBC surface temperatureis calculated ∆T = TDBC,max − TDBC,min for possiblesemiconductor positions, where TDBC,max is the junctiontemperature found in the center of the MOSFETs.Simulations of possible semiconductor positions and theirgraphical appearance are shown in Fig. 4. Blue indicates lowtemperature, red, high temperature. The matrix values are onlyshown for areas suitable for semiconductor placement, i.e.the phase track. It can be seen that from a thermal point ofview, the best place for semiconductors would be close to thecenter of the copper area, shifted a little to the upper right forreducing thermal coupling to the first chip located close to thelower left corner.

Fig. 4. Simulation results for different semiconductor positions on the phasetrack. Colors are indicating the variation of ∆T , blue color indicates lowtemperatur, red color inducates high temperature.

B. Stray Inductance Optimization

The second property to optimize is the stray inductance ofthe power module. They should be kept below an acceptablevalue. In case of the half-bridge configuration the general aimfor this is to keep the commutation path short. The lengthis affected by the position of the second MOSFET, hence itsparticular influence on the modules inductance is investigatedin this section. For an estimation of the overall stray inductancethe terminals inductances and the fraction of the high-sidebond wire connection have to be added.The current is guided to the semiconductor in two layers:The substrate metallization on the one hand, and the top sideconnection by bond wires on the other. This has to be takeninto account when calculating the inductance values for eachpossible chip position of the low side MOSFET.Fig. 5 shows the DBC stray inductance simulations for vari-ation in chip positions on the copper metallization. Blueindicates low and red indicates high stray inductance. It isobvious that semiconductor placement on the lower left cornerwould minimize stray inductance contributed by the phasetrack, as the current path through the two semiconductors isshort when placed close together.Fig. 6 shows the stray inductance for the bond wire connec-tions. It can be seen, that the fraction of the bond wire strayinductance increases with the distance to the negative DCtrack in a radial manner. The bondwires exhibit a larger strayinductance compared to the current path through the substratein general, because they have smaller cross-section and arespanned as an arc, thus having increased length.By plotting these values, the given visualization is made,simplifying the optimization of stray inductance by indicatingsuitable chip positions.

Fig. 5. Simulation results for the variation of stray inductance for the currentpath through the substrate for different semiconductor positions on the phasetrack.

C. Capacitance Optimization

The third characteristic to optimize is the stray capacitance.This is responsible for the amount of common mode inter-ference [6] and should be reduced to low, acceptable values.The capacitance is influenced by the thickness of the substrateand the size of the copper area of the tracks. The capacitanceof the phase track is the most relevant, as its potential isfast changing within every switching operation, while the DCtracks have the fixed potential of the DC link. Thus the primaryaim is to reduce the copper area of the phase tracks and to

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Fig. 6. Simulation results for the variation of stray inductance for the currentpath through the bondwires for different semiconductor positions on the phasetrack.

enlarge the thickness of the substrate, but this contradicts therequirements of thermal optimization as the Al203 ceramicsexhibit poor thermal conductivity (20-170W/mK) comparedwith the copper layer (395W/mK) [12].Fig. 7 (a) shows the decrease of calculated parasitic capaci-tance for substrate thickness increasing from 200µm to 1200µm for a copper area size of 500 mm2. Fig. 7 (b) shows thelinear correlation between capacitance and decreasing size ofthe copper area starting from the maximum (500 mm2) to thelowest possible value (150 mm2) in the given example.

Fig. 7. Parasitic capacitance (a) decreasing with increase of substrate thick-ness (constant copper area: 500 mm2) and (b) linear increase of capacitancewith increasing size of the copper areas (constant substrate thickness: 400µm).

As not all substrate thicknesses are commercially avail-able we concentrate on the thickness of 400 µm which iswidespread and offers good thermal performance. Thus thesize of the phase track copper area is the major variable ofinterest. As seen in Fig. 7 (b), the optimization can be done bydownsizing the phase track: the smallest size yields the lowestcapacitance.Placement of the low-side MOSFET close to the phase termi-nal (right side of Fig. 8) allows the reduction of the the size ofthe phase track copper area. The optimization can be found bycalculating the required copper area for a set of possible chippositions, thereby the phase track length is shortened linearly,while the width is kept constant.Fig. 8 shows the results for the phase track optimization. Againit can be seen that the optimal position (indicated with blue)differs from the optimal chip positions from a thermal orinductance point of view.In the next chapter an approach for combined optimization ofthese opposing demands is suggested.

Fig. 8. Simulation for the variation of stray capacitance for different semi-conductor positions on the phase track. Blue color indicates low capacitance,red color inducates high stray capacitance.

IV. COMBINED OPTIMIZATION

The results from the last section have to be combined,taking all couplings into consideration. In the previous sec-tion the optimal semiconductor placement depending on thecorresponding parameter was calculated. All simulated valuesare given in one matrix for each parameter: M∆T , Lsub, Lbond,Capacitance.The idea of the combined optimization approach discussedhere is to perform a weighted summation of these matrices,where the weighting factors are defined by the demands ofthe application. Before this summation can be carried out, thematrices have to be standardized in order to be comparable.Therefore, the elements of each matrix are scaled to valuesbetween 0 and 1, where 0 represents the minimum and 1the maximum value of the particular matrix. The matrixsummation leads to the optimization matrix A depending onthe weighting factors wi, where

∑i

wi = 1 is defined as

follows:

A = w1 ·M∆T + w2 · Lsub + w3 · Lbond + w4 · C (1)

The weighting factors can be given as percentage values.Figure 9 demonstrates the results of a combined optimizationof thermal, inductive and capacitive properties. All theseparameters are equally weighted in this example. Blue in-dicates optimal chip position under these boundaries. If thepower module application requires an emphasis on one specialfeature, the weighting can be changed to priorize specificoptimization matrices, or to exclude applications dependingon negligible parameters.Fig. 10 shows the optimization results for the assumptionof an exemplary power module using low voltage MOSFET,where stray inductances are a major concern in module design.Therefore the optimization weighting is chosen as follows:80% stray inductance, 10% thermal performance, 10% straycapacitance.A high voltage application might focus more on thermalissues and stray capacitance, which can easily be investigatedby changing the weighting to: 10% stray inductance, 60%thermal, 30% stray capacitance. This result is shown in Fig. 11.Another approach for chip placement is to define regions ofacceptance for each parameter and to find the intersection ofthese areas for placing the semiconductors in acceptable areas.

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Fig. 9. Optimization results for semiconductor placement with equalweighting of each optimization parameter; w(M∆T )=25%, w(Lsub)=25%,w(Lbond)=25%, w(C=25%).

Fig. 10. Combined optimization results for parameters: w(M∆T )=10%,w(Lsub)=40%, w(Lbond)=40%, w(C)=10%.

Fig. 11. Combined optimization results for parameters: w(M∆T )=60%,w(Lsub)=5%, w(Lbond)=5%, w(C)=30%.

V. EVALUATION OF OVERALL PERFORMANCE

The last step of the optimization process is to estimate thetotal performance of the power module using the optimizedparameters. This can be done by using the results found inChapter III from which the theoretical optimum for each singleparameter is known. To get an idea of the expected valuesfor thermal and electric properties, they are derived from theappropriate matrices for the chip positions found in ChapterIV. Table II shows the resulting values for the optimizationboundaries given in Fig. 9, Fig. 10 and Fig. 11.They show, for the equal weighed optimization of the powermodule, values close to the mean value of the particular value.The stray inductance optimization (case 2) leads to noticeablylower values for Lsub and Lbond, but higher values for Cand ∆T . While in the high voltage model (case 3) a low ∆Tis achieved and low C. This is beneficial for high voltageMOSFET as high dU/dt occurs during switching processesand hence common mode noise occures if stray capacitanceis too high. These examples show the practicability of this

method for a combined optimization approach. Other examplescan be calculated depending on the demands of the intendedapplication.

Optimization Demand Estimated ValueswM∆T

wLs wLbwC M∆T Lsub Lbond C

25% 25% 25% 25% 24 K 4.6 nH 8.1 nH 45 pF10% 40% 40% 10% 38 K 2.1 nH 3.5 nH 102 pF60% 5% 5% 30% 23 K 4.9 nH 8.4 nH 40 pF

TABLE IIOVERALL PERFORMANCE

VI. CONCLUSION

A combined optimization approach regarding thermal prop-erties, stray inductances, and stray capacitances inside powersemiconductor modules was presented. The method allowsthe finding and comparision of the best suited positions forpower semiconductors on the DBC substrate as well as anoptimization of the substrate structuring. The results of theoptimization are given in a matrix representation illustratingthe performance achieved in a concrete way.Different optimization tasks can be carried out in one completemodell consisting of the single optimization matrices with thefeasibility for a parameter dependent weighted optimizationor the optimization with the assignment of tolerance areas forchips positions.This approach has the advantage of being simple to use andmight be an aid to guide development engineers on the wayto an optimized power module.For obtaining the optimization matrices it is advantageous touse a software algorithm varying the chip positions automati-cally, calculating all parameters in one cycle.For a generalization of the proposed method for multichippower module optimization it is required to find an adaptedapproach. A practicable way might be to add chips succes-sively to the DBC, repeating the steps described in this paperafter every semiconductor placement. The investigation of thisis still in progress.

ACKNOWLEDGMENT

This work has partly been supported by the European Unionand the state of Schleswig-Holstein, Germany.

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