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COMPREHENSIVE EXAM FOR Ph.D CONFIRMATION

Name Of The Candidate : V.JEAN SHILPA Date : 1!"!1

Time : #.1$a.m % 1&.1$ '.m T(ta) Ma*+, : 1--

ANSER ALL /0ESTIONS

PART A 1- X & &- MAR2S

1. Which hazard is more critical in pipelines and how can it be avoided?

2. What are the merits and demerits of static branch prediction?

3. Define multithreading and mention the importance of it.

4. What is the need for cache coherency?

. What are the features of heterogeneous multicore architecture!"#$%? &ive few

e'amples where "#$ are implemented.

(. Differentiate deadloc) and live loc).

*. What are the overheads involved in a thread?

+. ,ompare the sources of power dissipation between static and dynamic ,#- circuits.

/. What is glitching power dissipation? "ow can it be minimized?

10. When do reuire distributed buffers in a digital system?

PART 3 $ X 14 5- MAR2S

11. $% uppose you have two e'ecution pipelines each capable of beginning e'ecution of oneinstruction per cycle and enough fetchdecode bandwidth in the front end so that it will notstall your e'ecution. $ssume results can be immediately forwarded from one e'ecution unit

to another or to itself. urther assume that the only reason an e'ecution pipeline would stall

is to observe a true data dependence. 5ow how many cycles does the loop reuire in the

following code?

LATENC66oop7 6D 20!8'% #emory 6D 93

:-7 #;6 90

:27 6D 40!8y% >ranches 91

:37 $DDD 404 $DDD 92

:47 $DDD 10+2 #;6 820848'

:/7 >5@ 8206oop

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!-8%

b% Describe how a thread level parallelism can be converted into :6A using imultaneous

#ultithreading with an e'ample.

12a% B'plain the basics of DirectoryC>ased ,ache ,oherence Arotocol

!-8%

b%$ssume that words '1 and '2 are in the same cache bloc) which is in the shared state in

the caches of both A1 and A2. $ssuming the following seuence of events identif7 ea8h

mi,,as a true sharing miss a false sharing miss or a hit. $ny miss that would occur if thebloc) size were one word is designated a true sharing miss.

Time P1 P&

1 Write '1

2 8ead '2

3 Write '14 Write '2

8ead '2

13 a%i% ,alculatethe speedup of pipelining that can be obtained with * tas)s if the meanoverhead of a pipeline is considered as and an e'ecution time per stage of 1 cycle? !+%

ii% What will bethe mean overhead of a pipeline with stages and an e'ecution

time per stage of 1 cycle? !+%

!-8%

b% ,lassify and e'plain the parallel programming models used on hybrid platforms

14 a%

!-8%

b%!i% Derive an e'pression for short circuit power dissipation of a ,#- inverter. !10% !ii% Write a short note on drain induced barrier lowering. !(%

1a% !i% "ow can power be reduced in write driver circuits and sense amplifier circuits?

B'plain. !10%

!ii% Differentiate #

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!ii% Design a full adder using $diabatic logic. !(%