Complex Digital Circuit Design for LHC Low Level RF

Complex Digital Circuit Design for Complex Digital Circuit Design for LHC Low Level RFLHC Low Level RF

John Molendijk CERN AB/RF/csJohn Molendijk CERN AB/RF/cs

LLRF05 J.Molendijk CERN AB/RLLRF05 J.Molendijk CERN AB/RF/csF/cs

22

PresentationPresentation Design Flow OverviewDesign Flow Overview

FPGA Design ToolsFPGA Design Tools PCB Related ToolsPCB Related Tools

ImplementationsImplementations Digital Signal Treatment ModulesDigital Signal Treatment Modules General Controls ModulesGeneral Controls Modules

Acquisition ExamplesAcquisition Examples Tuner Calibrate SweepTuner Calibrate Sweep Tuner Stepping Noise ObservationTuner Stepping Noise Observation


33

Design Flow Overview 1/2Design Flow Overview 1/2

FPGA FPGA Visual EliteVHDL text / Block Diagram /State Diagram / FlowChart /Truth Table

FPGA Design Flow

SynplifySynthesisTarget architecture mappingDesign Constraint Entry

Generic Design Entry &Functional Simulation

FPGA VendorDev. Sys.ISE / Quartus...

Place and route

NC-Sim

edf / vqm. file

VHDL fileTarget Simulationwith delays

FPGA Downloader /PROM prog.

Configuration file (bit)

VHDL file

VHDL TestBench

VHDL file

Import Externallycreated VHDL source

Concept (Cadence)

Cadence SymbolCreation

Schematic Entry

VHDL file

Allegro (Cadence)

PCB Design

SDF file

SDF file

SpectraQuest(Cadence)

Signal Integrity


44

Visual EliteVisual Elite Advantages Visual Elite toolAdvantages Visual Elite tool

Generates Device independent portable VHDL code.Generates Device independent portable VHDL code. Code reusabilityCode reusability Graphical Design BuilderGraphical Design Builder Graphics to text, text to graphics conversionGraphics to text, text to graphics conversion Powerful auto-documenting creates htmlPowerful auto-documenting creates html

DisadvantagesDisadvantages Need a synthesizer AND the FPGA dev. Sys.Need a synthesizer AND the FPGA dev. Sys. Multiple work directories, more complex environmentMultiple work directories, more complex environment Need to include Device / Vendor specific library if Need to include Device / Vendor specific library if

device specific features are required (reducing device specific features are required (reducing portability)portability)


55

Design Flow Overview 2/2Design Flow Overview 2/2

PCB PCB

Visual EliteVHDL text / Block Diagram /State Diagram / FlowChart /Truth Table

FPGA Design Flow

SynplifySynthesisTarget architecture mappingDesign Constraint Entry

Generic Design Entry &Functional Simulation

FPGA VendorDev. Sys.ISE / Quartus...

Place and route

NC-Sim

edf / vqm. file

VHDL fileTarget Simulationwith delays

FPGA Downloader /PROM prog.

Configuration file (bit)

VHDL file

VHDL TestBench

VHDL file

Import Externallycreated VHDL source

Concept (Cadence)

Cadence SymbolCreation

Schematic Entry

VHDL file

Allegro (Cadence)

PCB Design

SDF file

SDF file

SpectraQuest(Cadence)

Signal Integrity


66

PresentationPresentation

Design Flow OverviewDesign Flow Overview FPGA Design ToolsFPGA Design Tools PCB Related ToolsPCB Related Tools




77

Tuner Loop Module [7],[8]Tuner Loop Module [7],[8] Vacc Reference Channel &Vacc Reference Channel & IcFwd Channel IcFwd Channel

Tuner Loop FPGALast update: 05/07/2004

V acc x

38

0M

Hz

ADC

80

MH

z

Ic fwd x

38

0M

Hz

ADC

80

MH

z

Ic rev

x

38

0M

Hz

ADC

80

MH

z

Ig

x

38

0M

Hz

ADC

80

MH

z

Digital I/QDemod

80

MH

z

40

MH

z

20

MH

z

I

Q

Co

s(

)

Sin

()

PhaseRotation

I

Q

to RAM

Digital I/QDemod

80

MH

z

40

MH

z

20

MH

z

Q

Digital I/QDemod

80

MH

z

40

MH

z

20

MH

z

Digital I/QDemod

80

MH

z

40

MH

z

20

MH

z

I

to RAM

Q

I

to RAM

Q

I

to RAM

DecimatingLPF 1/16

2.5

MH

z

DecimatingLPF 1/16

DecimatingLPF 1/16

Cross-productVacc Ic fwd

x1 x2

y1y2

x1y2-x2y1

9.7

66

kH

z

MIN

MAX

c fwd

Power-product|Vacc|

2

x1

x2

DecimatingLPF 1/256

9.7

66

kH

z

X12+x2

2 |Vacc|2

Data rate = 80 MHz 40 MHz = 80 MHz/2 2.5 MHz = 40 MHz/16 9.766 kHz = 40 MHz/ 4096

to DSP tuning algotithm:f/f0)n+1=f/f0)n+a n/|Vacc|

2

virtualtrombone

PhaseRotation

Demux

0

1

Sin

Co

s

be

am

in tim

ing

before injafter inj

detuningangle

to RAM

to RAM

to RAM

to RAM

Data logging (RAM)Setting (via VME)

Sin(')

Cos(')Predictive detuning

(task in CPU?)

Sin

()

Co

s(

)

be

am

in tim

ing

scaling factor

error signal using cavity fwd

Cross-productVacc Ig

x1 x2

y1y2

x1y2-x2y1

MIN

MAX

g

to RAMto RAM

error signal using generator fwd

9.7

66

kH

z

Cross-productVacc Ic rev

x1 x2

y1y2

x1y2-x2y1

MIN

MAX

to RAMto RAM

9.7

66

kH

z

c reverror signal using cavity rev

DecimatingLPF 1/16

DecimatingLPF 1/16

DecimatingLPF 1/16

DecimatingLPF 1/16

DecimatingLPF 1/16

DecimatingLPF 1/16

2-stages CIC, D=2

[(1-z-32)/(1-z-1)]2

DecimatingLPF 1/256

FPGA: XC2V2000-6FG676C

DSP: ADSP TS101S BGA625

40MSPS80MSPS 2.5MSPS 9.766kSPS \ 1.22kSPS


88

Tuner Loop ModuleTuner Loop Module


99

Digital I/Q Demodulator 1/2 [1]Digital I/Q Demodulator 1/2 [1]

I1 Q1 -I2 -Q2

Inverted Signal

I3 Q3 -I4Signal

Offs

TunerCtrl applies 2 stage CIC with R=16 => Average over I/Q 16 (even) samples => Offset Cancelled.

0Intended Signal

Moving Average over 1 cyclefor PM & Observation MemoryFull 40MSPS rate & Offset compensation!

(Ii + Offs) - (-Ii+1 + Offs)

2I'i =

(Qi + Offs) - (-Qi+1 + Offs)

2Q'i =

12.5 ns

20050615 J.C.Molendijk CERN AB/RF


1010

Digital I/Q Demodulator 2/2Digital I/Q Demodulator 2/2


1111

Phase RotatorPhase Rotator


1212

2 Stage CIC16 2/2 [3]2 Stage CIC16 2/2 [3]

I I C C

R = 16

z-1 z-D

S = 2

26 26 26 26 262616SignExtend

MS16Scaling

Bgrow = (RD)S = 1024 = 10 bit

D = 2

1 - z-RD 1 - z-1

F(z) =S 1 - z-32

1 - z-1

2

=

A 2 stage Decimate by 16 CIC filter

+10

=> RDS (64) zeros and S poles (2)

Resource economic solution for decimating filters.

Rise-time = 0.9 μs to allow LHC abort gap to remain visible


1313

2 Stage CIC16 2/22 Stage CIC16 2/2


1414

Power ProductPower Product


1515

Cross Product as Phase DiscriCross Product as Phase Discri u x v = uu x v = uxx v vyy – u – uyy v vxx |u x v| = |u| x |v| sin|u x v| = |u| x |v| sinθθ = = εε IcFwd IcFwd u = Vacc, v = IcFwdu = Vacc, v = IcFwd


1616

MinMaxMinMax


1717

Decimating LPF256Decimating LPF256 Cascade of CIC16_2, 2x F2, F3 & F5.Cascade of CIC16_2, 2x F2, F3 & F5.

calculates average |Vacc|^2 over an LHC turn.calculates average |Vacc|^2 over an LHC turn. Design according to Goodman and Carey [2], [3]Design according to Goodman and Carey [2], [3]

Rise-time = 200 μs ~ -60dB at LHC Frev of 11kHz


1818

F3 Halfband filter 1/2F3 Halfband filter 1/2

Z-1

Z-2 Z-1F0-F1-F3

Z-2F1F3

f(1) = 9/32 f(0) = 16/32f(3) = -1/32

HB3 Out

HB3 In

F3 Halfband Filter

f(1) = 9/32 = 1/32 + 8/32

<<2

<<3

1/321/4

9/32

2 x (9 - 1) + 16 = 32

F0 F1-F1

-F3 F3

t

Impulse Response


1919

F3 Halfband Filter 2/2F3 Halfband Filter 2/2

Pipeline Registers


2020

Variable Rate Integrating filter for Variable Rate Integrating filter for Observation Buffer Observation Buffer

Bgrow = n


2121

Limiting AdderLimiting Adder

Xnor

Xor


2222

PresentationPresentation

Design Flow OverviewDesign Flow Overview FPGA Design ToolsFPGA Design Tools PCB Related ToolsPCB Related Tools




2323

Read Modify Write RegisterRead Modify Write Register

A Read Modify Write Register avoids data corruption if control register bits are used by different threads. The register is updated in 1 single access cycle.


2424

LFSR Counter 1/2LFSR Counter 1/2

0 10SR

17

characteristic polynomial: f(x) = X10 + X17

maximum sequence length => 2n - 1 => 218 - 1 = 262143

lockup state SR = 0 needs detection and recovery.

18 bit LFSR example

linear feedback xor

Linear Feedback Shift Register

tap

primitive non reducible polynomial yields


2525

LFSR Counter 2/2LFSR Counter 2/2

0 10SR 17

18 bit LFSR implementation example

SR(17 downto 0)

&SlowClk

Seed

Pre(17 downto 0)PresetEnable

0 1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 1 0

All '1'

By seeding the LFSR with "01" & X"CA3E" upon SlowClk outwe divide the Clk by 250000

Clk


2626

PresentationPresentation Design Flow OverviewDesign Flow Overview

FPGA Design ToolsFPGA Design Tools PCB Related ToolsPCB Related Tools




2727

-5000

-4000

-3000

-2000

-1000

0

1000

2000

3000

4000

5000

1 1001 2001 3001 4001 5001 6001 7001

-50

-40

-30

-20

-10

0

10

20

30

40

50

Vacc^2EIcFwdRatio

Tuner Calibration SweepTuner Calibration Sweep Output buffer |Vacc|Output buffer |Vacc|22 & & εεIIcFwd acquired with Tsample = 1.635 ms, cFwd acquired with Tsample = 1.635 ms,

buffer length = 13.4sbuffer length = 13.4s

Ratio ScaleRatio = εIcFwd / Vacc2

Quantization effects in the Denominator

Q = 60k Pfwd = 100kW

F = 400.789 MHz

Vcav @ resonance ~1.5MV


2828

12345

12346

12347

12348

12349

12350

1 1001 2001 3001 4001 5001 6001 7001 8001

-0.1

-0.05

0

0.05

0.1

0.15

Pos

Ratio

Tuner Stepping, Noise ObservationTuner Stepping, Noise Observation Output buffer |VaccOutput buffer |Vacc22| |

& & εεIIcFwd. Tsample = cFwd. Tsample = 1.635 ms, buffer 1.635 ms, buffer length = 13.4slength = 13.4s

12347

12348

12349

12350

1 101 201 301 401

-0.06

-0.04

-0.02

0

0.02

0.04

0.06

0.08

PosRatio

144 Hz ringing after a step probably due to Mechanical cavity resonance.

Steady Tuned Condition, only 4 tuning steps (back and forth) over 13.4s. Slow Ratio drift phenomena probably due to He fluctuations.

1 Step ~25Hz


2929

ReferencesReferences

Digital I/Q demodulatorDigital I/Q demodulator [1] Ziomek, C. and Corredoura, P: “Digital I/Q Demodulator” PAC’95[1] Ziomek, C. and Corredoura, P: “Digital I/Q Demodulator” PAC’95

CIC and Halfband filter designCIC and Halfband filter design [2] D.J. Goodman, M.J. Carey: “Nine Digital Filters for Decimation abd [2] D.J. Goodman, M.J. Carey: “Nine Digital Filters for Decimation abd

Interpolation,” IEEE transactions on acoustics, and signal processing, vol. ASSP-Interpolation,” IEEE transactions on acoustics, and signal processing, vol. ASSP-25, No. 2, April 197725, No. 2, April 1977

[3] Uwe Meyer-Baese: “Digital Signal Processing with Field Programmable Gate [3] Uwe Meyer-Baese: “Digital Signal Processing with Field Programmable Gate Arrays”.Arrays”.

Principles of LHC Tuner LoopPrinciples of LHC Tuner Loop [4] P. Baudrenghien: “Principles of the LHC Tuner Loop” (in work)[4] P. Baudrenghien: “Principles of the LHC Tuner Loop” (in work)

LFSRLFSR [5] [5] http://direct.xilinx.com/bvdocs/appnotes/xapp052.pdfhttp://direct.xilinx.com/bvdocs/appnotes/xapp052.pdf [6] [6] http://en.wikipedia.org/wiki/LFSRhttp://en.wikipedia.org/wiki/LFSR

LHC Tuner Loop Module HardwareLHC Tuner Loop Module Hardware https://edms.cern.chhttps://edms.cern.ch -> Global Database -> Search -> Global Database -> Search

• [7] LHC Tuner RF Front-end EDA-00331[7] LHC Tuner RF Front-end EDA-00331• [8] LHC Tuner Control card EDA-00572[8] LHC Tuner Control card EDA-00572


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SoftwareSoftware

Visual Elite (Summit)Visual Elite (Summit) Synplify (Synplicity)Synplify (Synplicity) ISE (Xilinx)ISE (Xilinx) Quartus (Altera)Quartus (Altera) Concept, PartDeveloper, Allegro, Spectra Quest, NC-sim Concept, PartDeveloper, Allegro, Spectra Quest, NC-sim

(Cadence)(Cadence)

Complex Digital Circuit Design for LHC Low Level RF

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