Complementary MOS

8/3/2019 Complementary MOS

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ComplementaryMOS fabrication


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CMOS Technology has both N-Type and P-Type MOSFETs on the same chip.

VDD

A Y

GND

n+

p substrate

p+

n well

A

YGND V

DD

n+ p+

SiO2

n+ diffusion

p+ diffusion

polysilicon

metal1

nMOS transistor pMOS transistor


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The two main technologies to do this task are:

P-Well

Substrate N-type

P-type well inside the N-type wafer where N-channel MOSFET is built N-channel MOSFET is built directly inside the substrate

N-Well

Substrate P-type

N-type well inside the P-type wafer where P-channel MOSFET is built

P-channel MOSFET is built directly inside the substrate

To improve the device performance and density two advanced technologies for

CMOS fabrication are

Twin Tub

Both an N-Well and a P-Well are manufactured on a lightly doped N-type

substrate.

Silicon-on-Insulator (SOI) CMOS Process

SOI allows isolated nMOS and pMOS transistors side-by-side on an

insulating substrate

Advantages : prevents latch up, increases integration density, reduces

parasitic capacitance


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N well process

Substrate must be tied to GND and n-well to VDD

Metal to lightly-doped semiconductor forms poor

connection called Shottky Diode

Use heavily doped well and substrate contacts / taps

Adv:-lesser effect of substrate bias on Threshold voltageand lesser parasitic capacitances. Also the process steps

are similar to conventional N-channel MOS fabrication.

n+

p substrate

p+

n well

A

Y

GND VDD

n+p+

substrate tap well tap

n+ p+


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Cross-section taken along dashed line

GND VDD

Y

A

substrate tap well tap

nMOS transistor pMOS transistor


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Six masks

n-well

Polysilicon

n+ diffusion

p+ diffusion

Contact

Metal

Metal

Polysilicon

Contact

n+ Diffusion

p+ Diffusion

n well


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Processing steps

p substrate

p substrate

SiO2

Start with blank wafer

First step will be to form the n-well

For that first deposit SiO2 and pattern it using lithography

p substrate

SiO2

PhotoresistSpin Photo resist


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p substrate

SiO2

Photoresist

Expose photoresist through n-well mask

Strip off exposed photoresist

p substrate

SiO2

Photoresist

Etch oxide with hydrofluoric acid (HF)


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p substrate

SiO2

Strip off remaining photoresist

n-well is formed with diffusion or ion implantation

n well

SiO2

p substrate

n well

Strip off the remaining oxide using HF


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Thin gate oxide

Polysilicon

p substraten well

Deposit very thin layer of gate oxide and a thin layer of polysilicon

Heavily doped to be good conductor

Polysilicon

p substrate

Thin gate oxide

Polysilicon

n well

Polysilicon Patterning


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p substraten well

Deposit oxide and pattern to expose where n+ dopants should be diffused or

implanted to form n+ source and drain implants and substrate

p substraten well

n+ is diffused through the patterned oxide. This is a self-aligned process where

gate blocks diffusion

n+ Diffusion

p substrate

n well


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n wellp substrate

n+n+ n+

After n+ diffusion

n wellp substrate

n+n+ n+

Remove the oxide completely

Next step is to form p+ diffusion regions for pMOS source and drain and

substrate contact

p+ Diffusion

p substrate

n well

n+n+ n+p+p+p+


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Fabrication and Layout Slide 13

To wire together the devices cover chip with thick field oxide and etch oxide where

contact cuts are needed

p substrate

Thick field oxide

n well

n+n+ n+p+p+p+

Contact

Deposit aluminium over the wafer and pattern to remove excess metal, leaving wires

Metal

p substrate

Metal

Thick field oxide

n well

n+n+ n+p+p+p+


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Latch up in CMOS

Latchup is defined as the generation of a low impedance path in CMOS chips

between power supply rail and the ground rail due to interaction of parasitic pnp

and npn bipolar transistors. This causes excessive current flows and potential

permanent damage to the devices

If some external disturbance occurs, causing the collector current of one of the

parasitic transistors to increase, the resulting feedback loop causes the current

perturbation to be multiplied by F1.F2

This event triggers the silicon-controlled rectifier and each transistor drives the

other with positive feedback eventually creating and sustaining a low impedance

path between power and the ground rails resulting in latch-up.


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How to avoid latch up

Use p+ guardband rings connected to groundaround nMOS transistors and n+ guard ringsconnected to VDD around pMOS transistors toreduce R

wand R

suband to capture injected minority

carriers before they reach the base of the parasiticBJT.

Increase the substrate doping to minimise itsresistance

Provide isolation between the n type and ptypedevices

SOI technology


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Twin tub process

Provide separate optimization of the n-type and p-type transistors

Make it possible to optimize "Vt", "body effect", and the "gain" of n, p devices

independently.

Starting material: an n+ or p+ substrate with lightly doped - "epitaxial" or "epi"

layer to protect "latch up

Process sequence

a. Tub formation

b. Thin-Oxide construction

c. Source & drain implantations

d. Contact cut definition

e. Metallization


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Partially Depleted : In this type of SOI

MOSFET, the maximum depletionwidth is lesser than the thickness of

SOI when the channel is inverted.

Advantages: Easy to manufacture and

easily understood

Fully Depleted : In this type, the doping

and the thickness of the SOI is varied

such that the SOI is fully depleted

when the channel is inverted. The

maximum depletion width is greaterthan the thickness of the SOI

Advantages:Leakage and power

consumption drastically reduced.

Easier to contain short channel effects

Silicon-on-Insulator (SOI)CMOS Process


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A thin film of very lightly doped

semiconductor is grown over sapphire or

SiO2

Anisotropic etching is done to form n

islands


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P type implant is done by masking the other n

island with photoresist. p-island will form n-

channel device

N type implant is done by masking the p island

with photoresist. n-island will form p-channel

device

Gate oxide is grown through thermal oxidation

Next deposit Doped Polysilicon on top of this


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Pattern and Etch the polysilicon

n-implantation for source & drain of p channel

device

p-implantation for source & drain of n channel

device


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Grow phosphorus glass or Silicon dioxide over the entire surface

Etch glass to form contact cut

Evaporating alumnium over the surface and etch it for desired metal connections


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Advantages :

increases integration density, reduces parasitic capacitance,

reduced leakage currents

No body effect problems Enhanced radiation tolerance

Disadvantages

Manufacturing complexity

Cost


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Dielectric deposition

Dielectric films:- isolation and passivation of

devices

Commonly used deposition methods APCVD-atmospheric pressure CVD

LPCVD-Low pressure CVD

PECVD-Plasma enhanced CVD

Plasma energy+thermal energy

Considerations in selecting deposition process- substrate

temperature, deposition rate, film uniformity etc


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Si02 deposition

CVD oxides used to complement thermal oxide

Si02 -insulate multilevel metallization

-to mask ion implantation and diffusion

-to increase the thickness of thermally grown field oxide.

Reaction

Low temp reaction

SiH4(gas)+O2(gas)SiO2(solid)+2H2(gas)

This reaction takes place at 450oC.It can be done by APCVD orLPCVD

Moderate temp reactionSi(OC2H5)4 SiO2+ byproducts

Usually done by LPCVD

Done at 700oC


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High temperature reaction

-SiCl2H2+ 2N2OSiO2+2N2+2HCl

-Done at 900oC

Deposition temperature increases purityincreases

At high temperature composition of oxide issimilar to thermally grown SiO2

Step coverage

Surface topology of a deposited film to various

steps on the semiconductor substrate

Conformal step coverage due to rapid migration ofreactants after adsorption on the step surface


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Non conformal step- reactants adsorb andreact without significant migration

High temperature-good conformal coverage

Conformal step coverage Non Conformal step coverage


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Silicon nitride (Si3N4)

Used to passivate devices-barrier to diffusion of water and Na

Selective oxidation-nitrides oxidises slowly-prevents underlyingsilicon from oxidising

Low deposition temp deposited over fabricated devices and serveas final passivation .

Difficult to grow thermal nitride-Slow growth rate & high growthtemperature

Deposited at intermediate temperature

LPCVD or low temp Plasma assisted CVD

SiCl2H2+4NH2Si3N4+6HCl+6H2Good film uniformity and high wafer throughput

PECVD

3SiH4(gas)+4NH3(gas)Si3N4(solid)+12H2(gas)


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r


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Low k dielectric materials Multilevel metallization-minimise time delay due to

parasitic resistance R and Capacitance C

Interconnect materials with low resistivity and interlayerfilms with low capacitance

C=EA/d

To reduce the capacitance low k materials are used whereE=E0k

Eg:-Fluorinated hydrocarbon,Fluorosilicate glass

Storage Capacitance in DRAM needs to a high value

A minimum d is determined for maximum allowed leakagecurrent and minimum required braekdown voltage

Area can be increased by usingstacked or trench structures

For planar structure area is reduced by increasing theDRAM density.

So go for High k materials

Eg:-Ta2O5,TiO2etc

High k dielectric materials


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Poly silicon deposition

For aluminium the time to breakdown decreases as thethickness decreases.But for polysilicon it remains almostconstant.

As device dimensions shrink the gate oxide becomes very

thin .So aluminium not preferred. This happens because of the migration ofAluminium atoms

through the gate oxide at high electric fields

Also polysilicon can withstand high temp compared toaluminium.

It is used as the gate material for MOSFETs It is also used for fabrication of resistors

It adheres well to SiO2

SiH4Si+2H2. This reaction takes place at about 600oC

Complementary MOS

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