COMPARATIVAS

COP8 vs. PIC

COMPARATIVAS

COP8 vs. PIC

COP8SAC Diagrama en Bloques

Interrupt

16 bit Timer

T1

Instr. Decoder

ALU

SOSK

SI

(E6-E7)(EA-ED)

ROM Ad.

RAM Ad.

EPROM4 K

Bytes

(0-3FFF)

MARPC

FEATURE CORE

RAM128

Bytes

ClockHalt / IdleWake Up

Reset

I/O PortsG

8-bitsL

8-bitsD

8-bitsF

8-bitsC

8-bits

(D4-D6) (D0-D2) (D8-DA) (DC) (94-96)

WatchDog

Logic

(C7)

MultiInputWake

Up

(C8-CA)16 BitIdle

TimerT0

A

B

X

SP

PSW

CNTRL

(FE)

(FC)

(FD)

(EF)

(EE)

S (FF)

(E9)

Micro-Wire/Plus

Modified Harvard Architecture

Comparativa de características COP8 vs. PIC16C5x

COP8SAx PIC16C5X

Internal RC Oscillator Yes No

Serial Interface Yes No

EMI Reduction Circuitry Yes No

Interrupts 8 0

On-Chip Memory 1K / 2K / 4K 1K / 2K

I/O Efficiency 88,6% 60%

Schmitt Trigger Inputs 16 0

Programmable Pull-ups Yes No

High Sink Capability 12 pins 12 pins

Programmable MIWU Yes No

Number of Timers 2 1

COP8SAx PIC16C5X

Internal RC Oscillator Yes No

Serial Interface Yes No

EMI Reduction Circuitry Yes No

Interrupts 8 0

On-Chip Memory 1K / 2K / 4K 1K / 2K

I/O Efficiency 88,6% 60%

Schmitt Trigger Inputs 16 0

Programmable Pull-ups Yes No

High Sink Capability 12 pins 12 pins

Programmable MIWU Yes No

Number of Timers 2 1

BenchmarksBenchmarks

• Transferencia de 5 bytes de RAM a RAM

• Suma Binaria de 4 bytes

• Resta BCD de 8 Dígitos

• Uso de los Puertos de I/O

• I/O Serial + Acceso a tabla

• Búsqueda de 3 chars (string) en una tabla de 200

Diagrama en bloques del sistemaDiagrama en bloques del sistema

COP8

PIC

DAQ

Timer

Timer

GateReset

Selección de benchmark

GateReset

START

STOP

Benchmark #1

Cargar registrosindice

Copiar byteorigen a destino

5 bytes ?

Incrementarlos indices

NO

SI

Código fuente ...

START

STOP

Benchmark #2

Cargar registrosindice

A i <— B i + A i

4 bytes ?

Incrementarlos indices

NO

SI

Código fuente ...

START

STOP

Benchmark #3

Cargar registrosindice

Restar dos digitosy corregir

4 bytes ?

Incrementarlos indices

NO

SI

Código fuente ...

Res. Neg.?

SI

NO

Complementarel resultado

START

STOP

Benchmark #4

Cargar punteropara tabla

Char 3 ?

Incrementarpuntero

Char 1 ?

Char 2 ?

SI

SI

SI

NO

NO

NO

Fin tabla ?

SI

NO

STOP

START

STOP

Benchmark #5

Leer puertos(P1, P2)

P1 = P2 ?

NO

SI

P1 > P2 ?

NO

SI

P3 <— 9

P1 <— P2

P3 = l_P1 | h_P1

START

STOP

Benchmark #6

Cargarcontadores

Leer direccion ydato1 (serie)

100 bytes ?

dato2 <— [dirección]

NO

SI

Enviardato1 + dato2

Código Fuente #1

Benchmarks

COP8 PIC

START

LD B, #14 ; 1LD X, #50 ; 2

BM1LOOP: LD A, [B+] ; 1X A, [X+] ; 1IFBNE #3 ; 1JP BM1LOOP ; 1

STOP

START

MOVLW 5 MOVWF B1CNTRMOVLW 10

B1LOOP: MOVWF B1BASEMOVWF FSR MOVF INDF, W MOVWF B1TEMP MOVLW 5ADDWF FSR, F MOVF B1TEMP, W MOVWF INCF B1BASE, F DECFSZ B1CNTR, F GOTO B1LOOP

STOP

Código Fuente #2

Benchmarks

COP8 PIC

START

LD B, #10 ; 1LD X, #20 ; 2 RC ; 1

BM2LOOP: LD A, [X+] ; 1 ADC A, [B] ; 1 X A, [B+] ; 1 IFBNE #14 ; 1 JP BM2LOOP ; 1

STOP

START

MOVLW 4 MOVWF B2CNTRMOVLW 10 MOVWF B2BASEBCF STATUS, 0

B2LOOP: MOVF B2BASE, W MOVWF FSR MOVF INDF, W MOVWF B2TEMP MOVLW 4 SUBWF FSR, FMOVF B2TEMP, WADDWF INDF, FMOVLW 4ADDWF FSR, FINCF B2BASE, FDECFSZ B2CNTR, FGOTO B2LOOP

STOP

Código Fuente #3 - COP

START

LD B, #14 ; 1LD X, #20 ; 2SC ; 1

BM3LOOP: LD A, [X+] ; 1X A, [B] ; 1SUBC A, [B] ; 1DCOR A ; 1X A, [B+] ; 1IFBNE #2 ; 1JP BM3LOOP ; 1IFNC ; 1JP BM3NEGR ; 1RC ; 1

STOP

BM3NEGR: SC ; 1LD B, #14 ; 1

BM3LUP: CLR A ; 1SUBC A, [B] ; 1DCOR A ; 1X A, [B+] ; 1IFBNE #2 ; 1JP BM3LUP ; 1SC ; 1

STOP

Código Fuente #3 - PIC

Benchmarks

START

MOVLW . 4MOVWF B3CNTRMOVLW 0x20MOVWF B3BASEBSF STATUS, 0

B3LOOP: MOVF B3BASE, WMOVWF FSRMOVF INDF, WMOVWF B3TEMPMOVLW . 4SUBWF FSRCALL B3CORRMOVLW . 4ADDWF FSRDECFSZ B3CNTRGOTO B3LOOPBTFSS STATUS, 0GOTO B3NEGRBCF STATUS, 0

STOPgoto $

B3NEGR: MOVLW . 4MOVWF B3CNTRMOVLW 0x20MOVWF B3BASEBSF STATUS, 0

B3LUP: MOVF B3BASE, WMOVWF FSRMOVF INDF, WMOVWF B3TEMPCLRF INDFCALL B3CORRDECFSZ B3CNTRGOTO B3LUPBSF STATUS, 0

STOPgoto $

B3CORR: CLRF B3FLAGMOVF B3TEMP, WSUBWF INDFCLRF B3TEMPBTFSC STATUS, 0GOTO B3BYP1MOVLW 60HADDWF B3TEMP

B3BYP1: BSF B3FLAG, 0BTFSC STATUS, 1GOTO B3BYP2MOVLW 06HADDWF B3TEMP

B3BYP2: MOVF B3TEMP, WBSF STATUS, 0SUBWF INDFBTFSC B3FLAG, 0BCF STATUS, 0INCF B3BASERETLW 0

COP8 RAM Organization

F0-FFS = FF

80-FF

70-7F

00-6F

Unused(Reads as all ones)

On-ChipRAM

(64 Bytes)

Unused(Reads as all ones)

(S) = 00

(S) = 01 (S) = XX

017F

013F

0100 XX00

XX7F

Segment N

Segment 1

Segment 0

Base Address Range

If bit #7 of an address = 0, S is used to extend base address range, example shows a device with 192 bytes RAM

COP8 Data Memory Organization

F0-FFOn Chip User RAM, B&X ind. memory pointers, Stackpointer. Some special instr. (DRSZ) support onlyin this memory area (16 bytes)

E0-EFOn Chip Function Registers (Timer1,MICROWIRE/PLUS, PSW, CNTRL-Reg., etc.)

D0-DFOn Chip I/O Registers80-CFOn Chip Function Registers (Timers, Multi-Input

Wakeup, A/D, UART, etc.) Unused locations readundefined data

70-7FUnused RAM Address Space (reads all ones)00-6FOn Chip User RAM (112 Bytes)

COP8 Interrupt Structure

GIEINTERRUPT ENABLE

PENDING FLAGSOFTWARE TRAP

TIMER T1

EXTERNAL

MIWU

MICROWIRE/PLUS

FUTURE PER.

IDLE TIMER

PE

ND

ING

F LA

G

INTERRUPT

VIS FlowchartVIS

STPND SET?

EXTERNAL INTERRUPT

ACTIVE?

PORT L/WAKEUP

INTERRUPTACTIVE?

JUMP TO VECTOR AT 0yE0/0yE1

END

JUMP TO VECTOR AT 0yFE/0yFF

JUMP TO VECTOR AT 0yFA/0yFB

JUMP TO VECTOR AT 0yE2/0yE3

COP8 Port Structure

Pin

Pin

INTERNAL BUS

DataRegister

ConfigurationRegister

DataRegister

Bidirectional I/O Port

Output-Only Port

• HALT mode• IDLE mode• Multi-Input-Wake-Up (MIWU), to exit

power save modes via any of up to eight external events

Power Save Modes

HALT Mode

• HALT can be disabled via OTP configuration register or mask option

• All activities stopped except clock monitor– Enter HALT mode

• Setting the G7 data bit (program)

– Exit HALT mode• RESET• Low to high transition on CKO• Multi-Input Wakeup

IDLE Mode

• All activities stopped except– Oscillator– WATCHDOG logic– Clock monitor– IDLE timer (T0)

• Enter IDLE Mode by– Setting the G6 data bit (program)

• Exit IDLE Mode– Reset– Multi-Input Wakeup– T0 13-bit toggles

Instruction Set - Addressing Modes

• Direct: LD A, 05• Register Indirect X A, [B]• Register Indirect with X A, [B±]

Post Inc / Dec X A, [X±]• Immediate LD A, #05• Immediate Short LD B, #07• Indirect from Program

Memory LAID• Jump Relative JP 0A• Jump Absolute JP 013F• Jump Absolute Long JP 313F• Jump Indirect JID

Instruction Set - Types

• Arithmetic & Logic– ADD, SUBC, AND, OR, XOR

• A & C Specific– CLRA, SC, RC

• Transfer of Control– JMP, JSR, RET, NOP

• Memory Transfer– LD, X

• Conditionals

Instruction Set - Arithmetic

• ADD• ADC• SUBC• AND• OR• XOR• ANDSZ• DRSZ

Instruction Set - Accumulator and Carry

• CLRA• INCA• DECA• LAID• DCOR• RRCA• RLCA• PUSHA

• POPA• SWAPA• SC• RC• IFC• IFNC

LAID - instructionLAID - instruction

LAID

Load value toAccumulator

(0-256)

Accumulatorupdated from

table.

ROM TableLAID

000001

256

000

0EA

Instruction Set - Transfer of Control

• JMPL• JMP• JP• JSRL• JSR

• JID• RET• RETSK• RETI• INTR• NOP

Instruction Set - Memory Transfer

• LD A, address• LD B, immediate• LD Mem, immediate• LD Reg, immediate• X A, address

Conditionals

• IFEQ• IFNE• IFGT• IFBNE• IFBIT• IFC• IFNC

• Three Wire Serial Connection• Bidirectional• Flexible Frame Transmission• Programmable Transmission Speed• Master/Slave Mode• Short Message Length• Comparable Small Circuit

MICROWIRE/PLUS™

MICROWIRE/PLUS Circuit Block Diagram

PSW

7 6 5 4 3 2 1 0

CLK Select

Divider

TC1 TC2 TC3 TRUN MSEL IEDG SL1 SL0

Bit 7 Bit 0

Bit 7 Bit 0

Instruction Clock

SO

SI

SKSIOR

Internal

Data

Bus

BUSY

CNTRL

MICROWIRE/PLUS Example

COP8(Master)

COP8(Slave)

A/D E2 PLLLCD

Driver

DO DI CLK DO DI CLK DI CLK DI CLK

SISOSK

SISO

SK

Chip Select Lines

COP8 Timer Structure

T1RA

Timer T1

T1RB

IDLE TimerTimer T0

SELtC

T1B

T1A

tC

Internal Data Bus

IDLE Timer (T0)

WATCHDOG Logic

Down Counter (T0)

....... T0PND T0EN .......

IDLE

ChipClock

tC

0 10 15

11

57 4 0

ICNTRL Register

Multi-Input Wake-Up Logic

Interrupt

12-15

G6 Data Bit

S R

Internal Data Bus

Q