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http://vlsi-soc.blogspot.in/2013/05/combinational-loops.html

4thMay 2013

You would often hear backend engineers remonstrating the frontend

design folks on the presence of combinational loops in the design. But why

do they create such a hue and cry? What possibly could one or maybe few

combinational loops do? Well, potentially, they can render the entire

functionality of the SoC haywire and not taken care off. And some

combinational loops, on the other hand, are indispensable for the evolutionof a particular technology. We'll see how and why.

A combo loop is structure which is formed by a signal starting from

an input of a combinational gate, after passing through one or more

combinational gate, reaches the same combo gate from which it

started without encountering any sequential element in between.

Here's what a generalized combo loop looks like:

[http://2.bp.blogspot.com/-

H1rZifRhEaI/UYS2XUcBcSI/AAAAAAAAAYw/3npxw2AGx8s/s1600/Combo_1.bmp]

Unstable Loops: Let's start with a basic combo loop that you must

have studied in your academics or at least heard about it. The

reverend Ring Oscillator. It is an inveterate fallacy that a ring

oscillator can be used to make a clock generating circuit. Trust me,

clock generating or even divider circuits, for that matter, are not as

simple as the ring oscillator shown below.

[http://2.bp.blogspot.com/-

Combinational Loops

http://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-H1rZifRhEaI/UYS2XUcBcSI/AAAAAAAAAYw/3npxw2AGx8s/s1600/Combo_1.bmphttp://vlsi-soc.blogspot.com/2013/05/combinational-loops.htmlhttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmphttp://2.bp.blogspot.com/-H1rZifRhEaI/UYS2XUcBcSI/AAAAAAAAAYw/3npxw2AGx8s/s1600/Combo_1.bmphttp://vlsi-soc.blogspot.com/2013/05/combinational-loops.html

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ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmp]

Of what use could this simple circuit be? Well, if we can control any one

input of any of the three inverters shown here, we can know the delay of

an inverter which is often the first cell to be characterized in any

technology. Moreover, test structures like these also help the foundry guys

in determining the manufacturing process of a particular chip whether it

was WCS or BCS.

Stable Loops: Here's an example of a stable loop consisting of an

OR gate. Note that, as soon as the free input receives a logic 1, the

output goes to 1. And same signal is conveyed back to the another

input, and the loop is stable or rather stuck-at-1.

[http://2.bp.blogspot.com/-

JnY0OX_p-mk/UYS55-Z9zMI/AAAAAAAAAZU/LLcnr4bKqZg/s1600/stable_loop. bmp]

Note that stable loops would not pose problems of copious dynamic power

consumption. But such a loops pose headaches to DFT teams. Recall

from the post: Two Pillars of DFT: Controllability & Observability [http://vlsi-

soc.blogspot.in/2013/04/two-pillars-of-dft-controllability.html] , we talked abouthow stuck-at faults are simulated and detected. If such a loop would be

present in the design, any stuck-at faults in the vicinity of this gate cannot

be observed, and hence DFT team would lose their stuck-at coverage by a

considerable amount!!

STA Concerns: We started this post with a preamble talking about

backend engineers repining the frontend engineers. How would a backend

engineer be affected by a combo loop? Here's how.

Recall from the post: Factors Affecting Delays of Standard Cells [http://vlsi-soc.blogspot.in/2012/07/factors-affecting-delays-of-standard.html] that the delay

and output slew of any standard cell depends on the input slew and output

load. The below figure shows one such example, where slew can keep on

degrading indefinitely, and would ultimately impact the timing and more

importantly the power consumption of the SoC.

http://vlsi-soc.blogspot.in/2012/07/factors-affecting-delays-of-standard.htmlhttp://vlsi-soc.blogspot.in/2013/04/two-pillars-of-dft-controllability.htmlhttp://2.bp.blogspot.com/-JnY0OX_p-mk/UYS55-Z9zMI/AAAAAAAAAZU/LLcnr4bKqZg/s1600/stable_loop.bmphttp://2.bp.blogspot.com/-ZAxsquRsaPY/UYS3UbOx5PI/AAAAAAAAAY8/qrAw1ici8rM/s1600/Ring_Osc.bmp

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http://vlsi-soc.blogspot.in/2013/05/combinational-loops.html

[http://4.bp.blogspot.com/--

Rf8THNsxTw/UYTEVNL1EnI/AAAAAAAAAZg/C_Tocquhqx8/s1600/Slew_deg.bmp]

To sum up, combo loops must be avoided in all SoCs except for special

circumstances like ring oscillator circuit can be employed for testing

the characteristics of the SoC.

Posted 4th May 2013by Naman Gupta

Labels: Combinational Loops,Combo Loops,Ring Oscillator,SlewDegradation

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